>
> From my reply to v1 of this patch series:
>
> This is fragile since this information will be outdated if the C source
> code changes (e.g. renaming files or variables).
>
> Instead I would add the following comment:
>
> # This is the binary format that the QEMU "simple" trace backend
> #
> On 9 May 2023, at 16.38, Stefan Hajnoczi wrote:
>
> On Tue, May 02, 2023 at 11:23:31AM +0200, Mads Ynddal wrote:
>> From: Mads Ynddal
>>
>> The call to `getargspec` was deprecated and in Python 3.11 it has been
>> removed in favor of `getfullargspec`.
>
> Please add that getfullargspec() i
Halil Pasic writes:
> On Thu, 11 May 2023 14:20:51 +0200
> Markus Armbruster wrote:
> [..]
>> >
>> > In my opinion the best way to deal with such situations would be to
>> > abort() in test/development and log a warning in production. Of course
>>
>> Understand, but...
>>
>> > assert() would
On Sat Apr 29, 2023 at 12:30 AM AEST, Fabiano Rosas wrote:
> Vaibhav Jain writes:
>
> > Hi Fabiano,
> >
> > Thanks for looking into this patch and apologies for the delayed reponse.
> > Fabiano Rosas writes:
> >
> >> Narayana Murty N writes:
> >>
> >>> On PPC64 the HILE(Hypervisor Interrupt Litt
Emerald Rapids (EMR) is the next generation of Xeon server processor
after Sapphire Rapids (SPR).
Curretly, regarding the feature set that can be exposed to guest, there
isn't any one new comparing with SPR cpu model, except that EMR has a
different model number.
Though it's practicable to define
On Mon, May 8, 2023 at 11:48 AM Li, Yong wrote:
>
> Hi Alistair,
>
> Thanks for the information, what I'm doing is to implement the
> StandaloneMm and secure boot feature for RISC-V by following the ARM's way
>
> https://trustedfirmware-a.readthedocs.io/en/latest/components/secure-partition-manage
On Mon, May 8, 2023 at 10:04 PM Thomas Huth wrote:
>
> Now that the tswap() functions are available for target-independent
> code, too, we can move xilinx_ethlite.c from specific_ss to softmmu_ss
> to avoid that we have to compile this file multiple times.
>
> Signed-off-by: Thomas Huth
Reviewed
Maxim Kostin writes:
> Rename virtio_error function to virtio_error_impl and wrap it with
> virtio_error macro, it adds the "virtio" prefix to the error message.
>
> Remove redundant "virtio" prefixes in virtio_error calls.
>
> Signed-off-by: Maxim Kostin
Reviewed-by: Alex Bennée
--
Alex B
On Sun, May 14, 2023 at 03:55:11PM +0700, Bui Quang Minh wrote:
> On 5/12/23 21:39, Michael S. Tsirkin wrote:
> > On Tue, Apr 11, 2023 at 09:24:40PM +0700, Bui Quang Minh wrote:
> > > This commit adds XTSup configuration to let user choose to whether enable
> > > this feature or not. When XTSup is
Il ven 12 mag 2023, 14:41 Thomas Huth ha scritto:
> These tests rely on a default NIC to be available. Skip them if we
> used the "--without-default-devices" configure option.
>
> Signed-off-by: Thomas Huth
>
This is the only patch I have some qualms about, because it reduces
coverage in legiti
On Wed, May 10, 2023 at 12:30 PM wrote:
> From: qianfan Zhao
>
> TWI(i2c) is designed to be used as an interface between CPU host and the
> serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
> operated in standard mode(100kbit/s) or fast-mode, supporting data rate
> up to 400
Hi Qianfan,
On Wed, May 10, 2023 at 12:30 PM wrote:
> From: qianfan Zhao
>
> R40 has eight UARTs, support both 16450 and 16550 compatible modes.
>
> Signed-off-by: qianfan Zhao
> ---
> hw/arm/allwinner-r40.c | 31 ---
> include/hw/arm/allwinner-r40.h | 8
Hi Qianfan,
On Wed, May 10, 2023 at 12:30 PM wrote:
> From: qianfan Zhao
>
> Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
> and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
> for In-Car Entertainment usage, A40i and A40pro are variants that
> differ in a
On Wed, May 10, 2023 at 12:30 PM wrote:
> From: qianfan Zhao
>
> The CCU provides the registers to program the PLLs and the controls
> most of the clock generation, division, distribution, synchronization
> and gating.
>
> This commit adds support for the Clock Control Unit which emulates
> a si
On Wed, May 10, 2023 at 12:30 PM wrote:
> From: qianfan Zhao
>
> Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
> and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
> for In-Car Entertainment usage, A40i and A40pro are variants that
> differ in applicable temp
Hi,
I am going through some translation code for existing targets.
I would like to know if there are any good resources on deeper
understanding of translation blocks? Also some advice on the best way
to read code related to translation in Qemu and trying it out maybe
using the debugger, printing
Hello Avihai,
+static int loadvm_handle_initial_data_enable(MigrationIncomingState *mis)
+{
+InitialDataInfo buf;
+SaveStateEntry *se;
+ssize_t read_size;
+
+read_size = qemu_get_buffer(mis->from_src_file, (void *)&buf, sizeof(buf));
+if (read_size != sizeof(buf)) {
+
On 13/05/2023 12:53, Bernhard Beschow wrote:
Am 27. April 2023 12:31:10 UTC schrieb Mark Cave-Ayland
:
On 26/04/2023 19:25, Bernhard Beschow wrote:
Am 26. April 2023 11:33:40 UTC schrieb Mark Cave-Ayland
:
On 22/04/2023 16:07, Bernhard Beschow wrote:
isa_get_irq() asks for an ISADevice w
On 13/05/2023 11:09, Bernhard Beschow wrote:
The attribute isn't used since commit 5c9736789b79ea49cd236ac326f0a414f63b1015
"i82378: Cleanup implementation".
Signed-off-by: Bernhard Beschow
---
hw/isa/i82378.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/isa/i82378.c b/hw/isa/i8237
On 13/05/2023 11:09, Bernhard Beschow wrote:
Rather than using a string literal which is prone to typos let's use a macro
instead which is caught by the compiler if mistyped.
Signed-off-by: Bernhard Beschow
---
include/hw/char/parallel.h | 2 ++
hw/char/parallel-isa.c | 2 +-
hw/char/p
On 13/05/2023 11:09, Bernhard Beschow wrote:
The function is unused since commit
bdad3654d3c55f478e538037d9eccd204e5fc8ee ('hw/arm/nseries: Remove
invalid/unnecessary n8x0_uart_setup()').
Signed-off-by: Bernhard Beschow
---
include/hw/arm/omap.h | 1 -
hw/char/omap_uart.c | 9 -
On 13/05/2023 11:09, Bernhard Beschow wrote:
Both TYPE_KVM_I8254 and TYPE_I8254 have their own but same implementation of
the "iobase" property. The storage for the property already resides in
PITCommonState, so also move the property definition there.
Signed-off-by: Bernhard Beschow
---
hw/
On 5/12/23 03:04, Song Gao wrote:
When ipi mailbox is used, cpu_index is decoded from iocsr register.
cpu maybe does not exist. This patch adss NULL pointer check on
ipi device.
Signed-off-by: Song Gao
---
hw/intc/loongarch_ipi.c | 40 +---
hw/intc/trace-ev
On 5/12/23 10:02, Peter Maydell wrote:
In the vexpress board code, we allocate a new MemoryRegion at the top
of vexpress_common_init() but only set it up and use it inside the
"if (map[VE_NORFLASHALIAS] != -1)" conditional, so we leak it if not.
This isn't a very interesting leak as it's a tiny a
On 5/12/23 10:02, Peter Maydell wrote:
The IMPDEF sysreg L2CTLR_EL1 found on the Cortex-A35, A53, A57, A72
and which we (arguably dubiously) also provide in '-cpu max' has a
2 bit field for the number of processors in the cluster. On real
hardware this must be sufficient because it can only be co
On 5/12/23 21:39, Michael S. Tsirkin wrote:
On Tue, Apr 11, 2023 at 09:24:40PM +0700, Bui Quang Minh wrote:
This commit adds XTSup configuration to let user choose to whether enable
this feature or not. When XTSup is enabled, additional bytes in IRTE with
enabled guest virtual VAPIC are used to
Reviewed-by: Michael Rolnik
On Sun, May 14, 2023 at 12:54 AM ~rmsyn wrote:
> From: rmsyn
>
> Adds support for ATmega16u4 and ATmega32u4 MCU definitions.
>
> Defines interrupts, memory layout, and machine types for generic
> ATmega16u4 and ATmega32u4 MCUs.
>
> Signed-off-by: rmsyn
> ---
> hw/
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