On 3/27/23 20:06, Song Gao wrote:
+static bool do_cmp(DisasContext *ctx, arg_vvv *a, MemOp mop, TCGCond cond,
+ void (*func)(TCGCond, unsigned, uint32_t, uint32_t,
+uint32_t, uint32_t, uint32_t))
+{
+uint32_t vd_ofs, vj_ofs, vk_ofs;
+
+CHE
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VFCVT{L/H}.{S.H/D.S};
- VFCVT.{H.S/S.D};
- VFRINT[{RNE/RZ/RP/RM}].{S/D};
- VFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- VFTINT[RZ].{WU.S/LU.D};
- VFTINT[{RNE/RZ/RP/RM}].W.D;
- VFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- VFFINT.{S.W/D.L}[U];
- VFFINT.S.L, VFF
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VF{ADD/SUB/MUL/DIV}.{S/D};
- VF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- VF{MAX/MIN}.{S/D};
- VF{MAXA/MINA}.{S/D};
- VFLOGB.{S/D};
- VFCLASS.{S/D};
- VF{SQRT/RECIP/RSQRT}.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/cpu.h
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VFRSTP[I].{B/H}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 5 +++
target/loongarch/helper.h | 5 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +++
target/loongarch/insns.deco
On 3/27/23 20:06, Song Gao wrote:
+#define DO_BITCLR(a, bit) (a & ~(1ul << bit))
+#define DO_BITSET(a, bit) (a | 1ul << bit)
+#define DO_BITREV(a, bit) (a ^ (1ul << bit))
ul.
Also, the *i versions should always be inline.
And it should be trivial to expand the non-i versions inline, with shl.
On 3/27/23 20:06, Song Gao wrote:
+static uint64_t do_vpcnt(uint64_t u1)
+{
+u1 = (u1 & 0xULL) + ((u1 >> 1) & 0xULL);
+u1 = (u1 & 0xULL) + ((u1 >> 2) & 0xULL);
+u1 = (u1 & 0x0F0F0F0F0F0F0F0FULL) + ((u1 >> 4) & 0x0F0F0F
On 3/27/23 20:06, Song Gao wrote:
+#define DO_CLO_B(N) (clz32((uint8_t)~N) - 24)
+#define DO_CLO_H(N) (clz32((uint16_t)~N) - 16)
I think this is wrong. You *want* the high bits to be set, so that they are ones, and
included in the count, which you then subtract off. You want the "real" cou
On 3/27/23 20:06, Song Gao wrote:
+#define SSRLRNS(E1, E2, T1, T2, T3)\
+static T1 do_ssrlrns_ ## E1(T2 e2, int sa, int sh) \
+{ \
+T1 shft_res; \
+
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VSSRLN.{B.H/H.W/W.D};
- VSSRAN.{B.H/H.W/W.D};
- VSSRLN.{BU.H/HU.W/WU.D};
- VSSRAN.{BU.H/HU.W/WU.D};
- VSSRLNI.{B.H/H.W/W.D/D.Q};
- VSSRANI.{B.H/H.W/W.D/D.Q};
- VSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by:
On Wed Mar 29, 2023 at 3:51 PM AEST, Michael Neuling wrote:
> Nick,
>
> > +case POWERPC_EXCP_HV_EMU:
> > +env->spr[SPR_HEIR] = insn;
> > +if (is_prefix_excp(env, insn)) {
> > +uint32_t insn2 = ppc_ldl_code(env, env->nip + 4);
> > +env->spr[SPR_HEIR] |= (u
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For
pc_save for
PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env->pc + target_pc(from tb) - ctx->save_p
Am 30. März 2023 13:00:25 UTC schrieb Anthony PERARD
:
>On Sun, Mar 12, 2023 at 01:02:17PM +0100, Bernhard Beschow wrote:
>> This is a preparational patch for the next one to make the following
>> more obvious:
>>
>> First, pci_bus_irqs() is now called twice in case of Xen where the
>> second
On 4/1/23 04:03, liweiwei wrote:
mmap_unlock();
+
Blank line.
Yes, adding separation.
/*
* We add the TB in the virtual pc hash table
* for the fast lookup
*/
h = tb_jmp_cache_hash_
Hello Corey,
On 4/1/23 12:44 PM, Corey Minyard wrote:
On Fri, Mar 31, 2023 at 11:13:19AM -0500, Ninad Palsule wrote:
From: Ninad Palsule
Qemu already supports devices attached to ISA and sysbus. This drop adds
support for the I2C bus attached TPM devices. I2C model only supports
TPM2 protoco
On Sat, Apr 01, 2023 at 12:42:57PM +, Alexander Graf wrote:
> Add an option for hostmem-file to start the memory object at an offset
> into the target file. This is useful if multiple memory objects reside
> inside the same target file, such as a device node.
>
> In particular, it's useful to
On Fri, Mar 31, 2023 at 11:13:19AM -0500, Ninad Palsule wrote:
> From: Ninad Palsule
>
> Qemu already supports devices attached to ISA and sysbus. This drop adds
> support for the I2C bus attached TPM devices. I2C model only supports
> TPM2 protocol.
>
> This commit includes changes for the comm
On Fri, Mar 31, 2023 at 01:01:15AM +, Joe Komlodi wrote:
> Hi all,
>
> This series adds I3C bus support to QEMU and adds more functionality to the
> Aspeed I3C controller.
>
> This implementation is a basic implementation that introduces IBIs
> (including hot-join), CCCs, and SDR data transfe
These haven't even compiled in years. Last time I polled the NetBSD and
OpenBSD communities they weren't using this and had no plans to fix.
I'd be happy to work with anybody that wanted to fix that state of affairs.
Warner
On Sat, Apr 1, 2023, 7:00 AM Reinoud Zandijk wrote:
> Dear Qemu folks,
Dear Qemu folks,
I'll throw it in the NetBSD group for feedback.
With regards,
Reinoud
On Fri, Mar 31, 2023 at 08:18:26AM -0600, Warner Losh wrote:
> The NetBSD and OpenBSD support in bsd-user hasn't built since before the meson
> conversion. It's also out of sync with many of the recent changes
On 2023/4/1 20:39, Weiwei Li wrote:
This patchset tries to fix some problem in current implementation for pointer
mask, and add support for pointer mask of instruction fetch.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v5
v2:
* drop some error patchs
* A
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: LIU Zhiwei
---
target/riscv/csr.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/targe
This patchset tries to fix some problem in current implementation for pointer
mask, and add support for pointer mask of instruction fetch.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v5
v2:
* drop some error patchs
* Add patch 2 and 3 to fix the new problems
actual_address = (requested_address & ~mpmmask) | mpmbase.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vecto
The existence of CF_PCREL can improve performance with the guest
kernel's address space randomization. Each guest process maps
libc.so (et al) at a different virtual address, and this allows
those translations to be shared.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: LIU
Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc before misalign check, then update it into badaddr
and restore cpu_pc to curre
Add a base save_pc For PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env->pc + target_pc(from tb) - ctx->save_pc
Use gen_get_target_pc to compute target address of au
Transform the fetch address in cpu_get_tb_cpu_state() when pointer
mask for instruction is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 20 +++-
target/riscv/csr.c
Add an option for hostmem-file to start the memory object at an offset
into the target file. This is useful if multiple memory objects reside
inside the same target file, such as a device node.
In particular, it's useful to map guest memory directly into /dev/mem
for experimentation.
Signed-off-b
Add an option for hostmem-file to start the memory object at an offset
into the target file. This is useful if multiple memory objects reside
inside the same target file, such as a device node.
In particular, it's useful to map guest memory directly into /dev/mem
for experimentation.
Signed-off-b
The existence of CF_PCREL can improve performance with the guest
kernel's address space randomization. Each guest process maps
libc.so (et al) at a different virtual address, and this allows
those translations to be shared.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: LIU
Add a base save_pc For PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env->pc + target_pc(from tb) - ctx->save_pc
Use gen_get_target_pc to compute target address of au
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: LIU Zhiwei
---
target/riscv/csr.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/targe
Transform the fetch address in cpu_get_tb_cpu_state() when pointer
mask for instruction is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 20 +++-
target/riscv/csr.c
This patchset tries to fix some problem in current implementation for pointer
mask, and add support for pointer mask of instruction fetch.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v5
v2:
* drop some error patchs
* Add patch 2 and 3 to fix the new problems
actual_address = (requested_address & ~mpmmask) | mpmbase.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vecto
Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc before misalign check, then update it into badaddr
and restore cpu_pc to curre
On Sat, 1 Apr 2023 at 08:14, Alexander Graf wrote:
> diff --git a/qapi/qom.json b/qapi/qom.json
> index a877b879b9..8f5eaa8415 100644
> --- a/qapi/qom.json
> +++ b/qapi/qom.json
> @@ -635,6 +635,10 @@
> # specify the required alignment via this option.
> # 0 selects a default ali
Add an option for hostmem-file to start the memory object at an offset
into the target file. This is useful if multiple memory objects reside
inside the same target file, such as a device node.
In particular, it's useful to map guest memory directly into /dev/mem
for experimentation.
Signed-off-b
On 1 April 2023 12:57:33 BST, Michael Tokarev wrote:
>01.04.2023 14:45, Joao Martins пишет:
>> On 01/04/2023 09:40, Michael Tokarev wrote:
>>> After bringing in xen guest support, qemu fails to build on x32:
>>> Adding the folks who added the feature too
>>
>>> target/i386/kvm/xen-emu.c:876:5:
To clarify: I don't think this needs fixing for 8.0.
Yes, it's a regression on x32. Xen has never worked on x32,
this just looks like forgotten case when it needs to be disabled
in qemu for x86. It's trivial to work around by adding a --disable
argument to configure. And generally I don't know
01.04.2023 14:45, Joao Martins пишет:
On 01/04/2023 09:40, Michael Tokarev wrote:
After bringing in xen guest support, qemu fails to build on x32:
Adding the folks who added the feature too
target/i386/kvm/xen-emu.c:876:5: note: in expansion of macro ‘qemu_build_assert’
876 | qemu_buil
On 01/04/2023 09:40, Michael Tokarev wrote:
> After bringing in xen guest support, qemu fails to build on x32:
> Adding the folks who added the feature too
> target/i386/kvm/xen-emu.c:876:5: note: in expansion of macro
> ‘qemu_build_assert’
> 876 | qemu_build_assert(sizeof(struct vcpu_info)
On 2023/4/1 12:51, Richard Henderson wrote:
Assign pc and use store_release to assign tb.
Fixes: 2dd5b7a1b91 ("accel/tcg: Move jmp-cache `CF_PCREL` checks to caller")
Reported-by: Weiwei Li
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 17 +
1 file changed, 1
Allow TLB to be tagged with VMID.
If stage-1 is only supported, VMID is set to -1 and ignored from STE
and CMD_TLBI_NH* cmds.
Update smmu_iotlb_insert trace event to have vmid.
Signed-off-by: Mostafa Saleh
Reviewed-by: Eric Auger
---
Changes in v3:
- Collected Reviewed-by tag.
Changes in v2:
-
Right now, either stage-1 or stage-2 are supported, this simplifies
how we can deal with TLBs.
This patch makes TLB lookup work if stage-2 is enabled instead of
stage-1.
TLB lookup is done before a PTW, if a valid entry is found we won't
do the PTW.
To be able to do TLB lookup, we need the correct
In preparation for adding stage-2 support, rename smmu_ptw_64 to
smmu_ptw_64_s1 and refactor some of the code so it can be reused in
stage-2 page table walk.
Remove AA64 check from PTW as decode_cd already ensures that AA64 is
used, otherwise it faults with C_BAD_CD.
A stage member is added to SM
As everything is in place, we can use a new system property to
advertise which stage is supported and remove bad_ste from STE
stage2 config.
The property added arm-smmuv3.stage can have 3 values:
- "1": Stage-1 only is advertised.
- "2": Stage-2 only is advertised.
- "all": Stage-1 + Stage-2 are s
This patch series adds stage-2 translation support for SMMUv3. It is
controlled by a new system property “arm-smmuv3.stage”.
- When set to “1”: Stage-1 only would be advertised and supported (default
behaviour)
- When set to “2”: Stage-2 only would be advertised and supported.
- Value “all” is rese
In smmuv3_notify_iova, read the granule based on translation stage
and use VMID if valid value is sent.
Signed-off-by: Mostafa Saleh
Reviewed-by: Eric Auger
---
Changes in v3:
- Collected Reviewed-by tag.
---
hw/arm/smmuv3.c | 39 ++-
hw/arm/trace-events
CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
same as CMD_TLBI_NH_VAA.
CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID.
For stage-1 only commands, add a check to throw CERROR_ILL if used
when stage-1 is not supported.
Signed-off-by: Mostafa Saleh
---
Changes
In preparation for adding stage-2 support.
Add IDR0 fields related to stage-2.
VMID16: 16-bit VMID supported.
S2P: Stage-2 translation supported.
They are described in 6.3.1 SMMU_IDR0.
No functional change intended.
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Signed-off-by: Mostafa
In preparation for adding stage-2 support, add Stage-2 PTW code.
Only Aarch64 format is supported as stage-1.
Nesting stage-1 and stage-2 is not supported right now.
HTTU is not supported, SW is expected to maintain the Access flag.
This is described in the SMMUv3 manual(IHI 0070.E)
"5.2. Stream
In preparation for adding stage-2 support, add a S2 config
struct(SMMUS2Cfg), composed of the following fields and embedded in
the main SMMUTransCfg:
-tsz: Size of IPA input region (S2T0SZ)
-sl0: Start level of translation (S2SL0)
-affd: AF Fault Disable (S2AFFD)
-record_faults: Record fault ev
Parse stage-2 configuration from STE and populate it in SMMUS2Cfg.
Validity of field values are checked when possible.
Only AA64 tables are supported and Small Translation Tables (STT) are
not supported.
According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields
with an S2 prefix (with
20.02.2023 11:58, Mathis Marion пишет:
From: Mathis Marion
For a bit of context, I was trying to test a network border router [1]
daemon using the MIPS architecture (see [2]). I didn't have access to
real MIPS hardware so I figured I would emulate it using QEMU user mode.
I ran into a couple of
Fixes: f3034ad71fcd0a6a58bc37830f182b307f089159
Signed-off-by: Michael Tokarev
Reviewed-by: Stefan Weil
---
hw/virtio/virtio-qmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
This patch were previously sent at 5 Nov 2022, now the
code moved to another file, and the patch is still appl
Ping? :)
30.03.2023 13:18, Michael Tokarev wrote:
Hi!
Michael, there's the final step to do, after having the branch and increasing
version number, -
this is about to make the actual release. I see scripts/make-release which
apparently does what
it should, hopefully anyway. What's the final s
After bringing in xen guest support, qemu fails to build on x32:
target/i386/kvm/xen-emu.c:876:5: note: in expansion of macro ‘qemu_build_assert’
876 | qemu_build_assert(sizeof(struct vcpu_info) == 64);
| ^
This one should be easy to fix, but I wonder if there are
30.03.2023 13:11, Alex Bennée wrote:
We are a bit premature in recommending -blockdev/-device as the best
way to configure block devices, especially in the common case.
Improve the language to hopefully make things clearer.
Suggested-by: Michael Tokarev
Signed-off-by: Alex Bennée
---
qemu-op
59 matches
Mail list logo
