John Snow writes:
> This patch creates a new type, QAPIExpression, which represents a parsed
> expression complete with QAPIDoc and QAPISourceInfo.
>
> This patch turns parser.exprs into a list of QAPIExpression instead,
> and adjusts expr.py to match.
>
> This allows the types we specify in pars
John Snow writes:
> With the two major JSON-ish type hierarchies clarified for distinct
> purposes; QAPIExpression for parsed expressions and JSONValue for
The comment you remove talks about _ExprValue, not QAPIExpression.
> introspection data, remove this FIXME as no longer an action item.
>
>
John Snow writes:
> We can remove this alias as it only has two usages now, and no longer
> pays for the confusion of "yet another type".
>
> Signed-off-by: John Snow
Reviewed-by: Markus Armbruster
This is a ping to the patch below.
https://patchew.org/QEMU/ty0pr0101mb4285923fbe9ad97ce832d95ba4...@ty0pr0101mb4285.apcprd01.prod.exchangelabs.com/
Before this commit, when GDB attached an OS working on QEMU, order of FPU
stack registers printed by GDB command 'info float' was wrong. There was a
On 2023/2/9 14:23, Deepak Gupta wrote:
`zisslpcfi` extension adds two new CSRs. CSR_SSP and CSR_LPLR.
- CSR_SSP: This CSR holds shadow stack pointer for current privilege mode
CSR_SSP is accessible in all modes. Each mode must establish
it's own CSR_SSP.
- CSR_LPLR: Thi
On 2023/2/9 14:23, Deepak Gupta wrote:
Introducing riscv `zisslpcfi` extension to riscv target. `zisslpcfi`
extension provides hardware assistance to riscv hart to enable control
flow integrity (CFI) for software.
`zisslpcfi` extension expects hart to implement `zimops`. `zimops` stands
for "u
On 2023/2/10 20:38, Daniel Henrique Barboza wrote:
We have a RISCVCPU *cpu pointer available at the start of the function.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Regards,
Weiwei Li
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
At this moment, and apparently since ever, we have no way of enabling
RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
the nuts and bolts that handles how to properly write this CSR, has
always been a no-op as well becaus
On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
The masking done using env->misa_ext_mask already filters any extension
that QEMU doesn't support. If the hart supports the extension then QEMU
supports it as well.
If the masking done by env->misa_ext_mask is somehow letting unsupported
QEMU
RTCState only represents a Motorola MC146818 model,
not any RTC chipset. Rename the structure as MC146818RtcState
using:
$ sed -i -e s/RTCState/MC146818RtcState/g $(git grep -wl RTCState)
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/piix4.c | 2 +-
hw/isa/vt82c686.c
rtc_get_memory() and rtc_set_memory() helpers only work with
TYPE_MC146818_RTC devices. 'memory' in their name refer to
the CMOS region. Rename them as mc146818rtc_get_cmos_data()
and mc146818rtc_set_cmos_data() to be explicit about what
they are doing.
Mechanical change doing:
$ sed -i -e 's/r
rtc_get_memory() and rtc_set_memory() methods can not take any
TYPE_ISA_DEVICE object. They expect a TYPE_MC146818_RTC one.
Simplify the API by passing a MC146818RtcState.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/microvm.c| 6 ++
hw/i386/pc.c | 16 +
rtc_get_memory() and rtc_set_memory() helpers only work with
MC146818 RTC devices, not any ISA device. Rename accordingly
including 'MC146818' in the method names.
Philippe Mathieu-Daudé (3):
hw/rtc/mc146818rtc: Rename RTCState -> MC146818RtcState
hw/rtc/mc146818rtc: Pass MC146818RtcState inst
On Tue, 7 Feb 2023, Chuck Zmudzinski wrote:
> Commit 998250e97661 ("xen, gfx passthrough: register host bridge specific
> to passthrough") uses the igd-passthrough-i440FX pci host device with
> the xenfv machine type and igd-passthru=on, but using it for the pc
> machine type, xen accelerator, and
From: Juergen Lock
Helper functions for sysctl implementations. sysctl_name2oid and
sysctl_oidfmt convert oids between host and targets
Signed-off-by: Juergen Lock
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-sys.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/
From: Stacey Son
Connect up the sysarch system call.
Signed-off-by: Juergen Lock
Co-authored-by: Juergen Lock
Signed-off-by: Stacey Son
Reviewed-by: Warner Losh
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-syscall.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/bsd-user/
From: Doug Rabson
System call return values on FreeBSD are in a register (which is spelled
api_long in qemu). This was being assigned into an int variable which
causes problems for 64bit targets.
Resolves: https://github.com/qemu-bsd-user/qemu-bsd-user/issues/40
Signed-off-by: Doug Rabson
Revie
When building with clang, -no-pie gives a warning on every single build,
so remove it.
Signed-off-by: Warner Losh
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index 64960c6000f..eb284ccf308 100755
--- a/configure
+++ b/configure
@@ -1313
From: Kyle Evans
do_freebsd_sysctlbyname needs to translate the 'name' back down to a OID
so we can intercept the special ones. Do that and call the common wrapper
do_freebsd_sysctl_oid.
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-sys.c | 58 ++
From: Kyle Evans
Implement the wrapper function for sysctl(2). This puts the oid
arguments into a standard form and calls the common
do_freebsd_sysctl_oid.
Signed-off-by: Kyle Evans
Co-Authored-by: Juergen Lock
Signed-off-by: Juergen Lock
Co-Authored-by: Stacey Son
Signed-off-by: Stacey Son
From: Juergen Lock
do_freebsd_sysctl_oid filters out some of the binary and special sysctls
where host != target. This commit focuses on the simple sysctls that can
be done in a few lines.
Signed-off-by: Juergen Lock
Co-Authored-by: Stacey Son
Signed-off-by: Stacey Son
Signed-off-by: Warner L
From: Stacey Son
oidfmt uses undocumented system call to get the type of the sysctl.
sysctl_oldcvt does the byte swapping in the data to return it to the
target.
Co-Authored-by: Sean Bruno
Signed-off-by: Sean Bruno
Co-Authored-by: Juergen Lock
Signed-off-by: Juergen Lock
Co-Authored-by: Raph
This group of patches gets the basic framework for sysctl upstreamed. There's a
lot more to translate far too many binary blobs the kernel publishes via
sysctls, but I'm leaving those out in the name of simplicity.
There's also a bug fix from Doug Rabson that fixes a long int confusion leading
to
Most of the time, it's useful to make our best effort, but sometimes we
want to know right away when we don't implement something. First place
we use it is for unknown syscalls.
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-syscall.c | 4
bsd-user/main.c | 5 -
bsd-us
From: Stefano Stabellini
This patch does following:
1. creates arch_handle_ioreq() and arch_xen_set_memory(). This is done in
preparation for moving most of xen-hvm code to an arch-neutral location,
move the x86-specific portion of xen_set_memory to arch_xen_set_memory.
Also, move han
From: Vikram Garhwal
Add a new machine xenpvh which creates a IOREQ server to register/connect with
Xen Hypervisor.
Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
TPM emulator and connects to swtpm running on host machine via chardev socket
and support TPM functio
From: Stefano Stabellini
have_xen_pci_passthrough is only used for Xen x86 VMs.
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meson.build b/meson.build
index c626ccfa82..fb9fb97bb1 100644
--- a/meson.build
+++
From: Vikram Garhwal
Replace g_malloc with g_new and perror with error_report.
Signed-off-by: Vikram Garhwal
Reviewed-by: Stefano Stabellini
Reviewed-by: Paul Durrant
---
hw/xen/xen-hvm-common.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/xen/xen-hvm-c
From: Stefano Stabellini
This is done to prepare for enabling xenpv support for ARM architecture.
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails,
continue to the PV backends initialization.
Signed-off-by
From: Stefano Stabellini
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails continue
to the PV backends initialization.
Also, moved the IOREQ registration and mapping subroutine to new function
xen_do_ioreq_
From: Vikram Garhwal
xen-mapcache.c contains common functions which can be used for enabling Xen on
aarch64 with IOREQ handling. Moving it out from hw/i386/xen to hw/xen to make it
accessible for both aarch64 and x86.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
Reviewed-by:
From: Stefano Stabellini
In preparation to moving most of xen-hvm code to an arch-neutral location, move:
- shared_vmport_page
- log_for_dirtybit
- dirty_bitmap
- suspend
- wakeup
out of XenIOState struct as these are only used on x86, especially the ones
related to dirty logging.
Updated XenIOS
From: Vikram Garhwal
In preparation to moving most of xen-hvm code to an arch-neutral location,
move non IOREQ references to:
- xen_get_vmport_regs_pfn
- xen_suspend_notifier
- xen_wakeup_notifier
- xen_ram_init
towards the end of the xen_hvm_init_pc() function.
This is done to keep the common
From: Vikram Garhwal
Add CONFIG_XEN for aarch64 device to support build for ARM targets.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
inde
The following changes since commit 90595cc9396bb910b148391fea2e78dd8c6c8b27:
Merge tag 'migration-20230209-pull-request' of
https://gitlab.com/juan.quintela/qemu into staging (2023-02-10 10:50:21 +)
are available in the Git repository at:
https://gitlab.com/sstabellini/qemu.git xenpvh
GBPA register can be used to globally abort all
transactions.
It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
be zero(Do not abort incoming transactions).
Other fields have default values of Use Incoming.
If UPDATE is not set
On Fri, Feb 10, 2023 at 12:37:30AM +0100, Juan Quintela wrote:
> 0x80 is RAM_SAVE_FLAG_HOOK, it is in qemu-file now.
> Bigger usable flag is 0x200, noticing that.
> We can reuse RAM_SAVe_FLAG_FULL.
SAVE
>
> Signed-off-by: Juan Quintela
> ---
> migration/ram.c | 12
> 1 file change
Il ven 10 feb 2023, 19:09 Peter Maydell ha
scritto:
> On Fri, 10 Feb 2023 at 17:55, John Snow wrote:
> > (The problem with just allowing sphinx to be a black box and
> > continuing to happily use the 3.6-based versions is that we are
> > using QAPIDoc extensions from our own codebase, which woul
On Fri, Feb 10, 2023 at 10:28:42AM -0500, John Snow wrote:
> > > python=
> > > +first_python=
> > > explicit_python=no
> > > -for binary in "${PYTHON-python3}" python
> > > +# A bare 'python' is traditionally python 2.x, but some distros
> > > +# have it as python 3.x, so check in both places.
On 2/10/23 01:36, Peter Maydell wrote:
On Tue, 24 Jan 2023 at 00:01, Richard Henderson
wrote:
Test in_space instead of in_secure so that we don't switch
out of Root space. Handle the output space change immediately,
rather than try and combine the NSTable and NS bits later.
Signed-off-by: Ri
On Thu, Feb 09, 2023 at 10:40:30AM -0500, John Snow wrote:
> At the moment, we look for just "python3" and "python", which is good
> enough almost all of the time. But ... if you are on a platform that
> uses an older Python by default and only offers a newer Python as an
> option, you'll have to s
On Fri, Feb 10, 2023, 2:45 AM Thomas Huth wrote:
> On 10/02/2023 01.31, John Snow wrote:
> > If we begin requiring Python 3.7+, a few platforms are going to need to
> > install an additional package.
> >
> > This is at least mildly annoying to the user (and I hate negative
> > attention), so solv
On 2/10/23 18:15, Peter Maydell wrote:
Right. All of these things together seem to say:
* Python is not an unreasonable thing for the project
to depend on
* CentOS 8 is not an unreasonable distro for us to
want to continue to support
* Therefore we should continue to work with the P
On Fri, 10 Feb 2023 at 17:55, John Snow wrote:
> (The problem with just allowing sphinx to be a black box and
> continuing to happily use the 3.6-based versions is that we are
> using QAPIDoc extensions from our own codebase, which would lock
> those to 3.6. A big motivator for Markus is dropping
On Fri, Feb 10, 2023 at 04:11:37PM +, Peter Maydell wrote:
>
> I think we should check the whole register against its reset value,
> not just the ABORT bit. Otherwise if the guest writes the other fields
> to non default values we won't migrate them. That doesn't change the
> device behaviour
On Fri, Feb 10, 2023, 11:32 AM Peter Maydell
wrote:
> On Fri, 10 Feb 2023 at 16:01, John Snow wrote:
> > On Fri, Feb 10, 2023, 5:41 AM Peter Maydell
> wrote:
> >> On Fri, 10 Feb 2023 at 00:31, John Snow wrote:
> >> This confuses me. We work fine with Python 3.6 today.
> >
> >
> > That won't la
On Fri, Feb 10, 2023 at 03:36:30AM -0300, Leonardo Bras wrote:
> Current approach will only join threads that are still running.
>
> For the threads not joined, resources or private memory are always kept in
> the process space and never reclaimed before process end, and this risks
> serious memor
On Fri, Feb 10, 2023 at 03:36:29AM -0300, Leonardo Bras wrote:
> Before assigning "p->quit = true" for every multifd channel,
> multifd_load_cleanup() will call multifd_recv_terminate_threads() which
> already does the same assignment, while protected by a mutex.
>
> So there is no point doing the
On Fri, Oct 28, 2022 at 01:39:14PM +0300, Nikolay Borisov wrote:
> Add basic tests for file-based migration as well as for the 'fixed-ram'
> feature.
>
> Signed-off-by: Nikolay Borisov
> ---
> tests/qtest/migration-test.c | 46
> 1 file changed, 46 insertions
Leo,
Please still provide a cover letter as long as >1 patches will be posted as
a set.
Not only because it still always help to provide an overview for reviewers
before reading each of them (e.g. I have a habit of prioritizing reviews
based on cover letters first), but also when you're confident
On Fri, 10 Feb 2023 at 16:52, Daniel P. Berrangé wrote:
>
> On Fri, Feb 10, 2023 at 04:32:19PM +, Peter Maydell wrote:
> > On Fri, 10 Feb 2023 at 16:01, John Snow wrote:
> > > On Fri, Feb 10, 2023, 5:41 AM Peter Maydell
> > > wrote:
> > >> On Fri, 10 Feb 2023 at 00:31, John Snow wrote:
> >
On Fri, Oct 28, 2022 at 01:39:13PM +0300, Nikolay Borisov wrote:
> file-based migration requires the target to initiate its migration after
> the source has finished writing out the data in the file. Currently
> there's no easy way to initiate 'migrate-incoming', allow this by
> introducing migrate
On 10/2/23 17:27, Bernhard Beschow wrote:
Am 23. Januar 2023 15:51:49 UTC schrieb Bernhard Beschow :
Am 23. Januar 2023 09:25:51 UTC schrieb "Philippe Mathieu-Daudé"
:
On 20/1/23 13:22, Bernhard Beschow wrote:
Am 13. Januar 2023 17:39:45 UTC schrieb Bernhard Beschow :
Am 13. Januar 2023
On Fri, Oct 28, 2022 at 01:39:10PM +0300, Nikolay Borisov wrote:
> Implement 'fixed-ram' feature. The core of the feature is to ensure that
> each ram page of the migration stream has a specific offset in the
> resulting migration stream. The reason why we'd want such behavior are
> two fold:
>
>
Hi Francesco,
On 14/1/23 17:12, francesco.cag...@gmail.com wrote:
From: Francesco Cagnin
This patch series aims to add gdbstub support to HVF (the 'QEMU
accelerator on macOS that employs Hypervisor.framework') on Apple
Silicon hosts.
The patch has been most recently tested working on macOS
On Fri, Oct 28, 2022 at 01:39:08PM +0300, Nikolay Borisov wrote:
> preadv is going to be needed when 'fixed-ram'-enabled stream are to be
> restored. Add a minimal implementation of preadv for file channels and
> expose it via the generic io_preadv interface.
>
> Signed-off-by: Nikolay Borisov
>
- Use QOM macros
- Unify QOM type names
Based-on: <20230210163744.32182-1-phi...@linaro.org>
Philippe Mathieu-Daudé (4):
hw/southbridge/piix: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
hw/isa/piix: Batch register QOM types using DEFINE_TYPES() macro
hw/isa/piix: Unify QOM type name of PIIX ISA
On Fri, Oct 28, 2022 at 01:39:09PM +0300, Nikolay Borisov wrote:
> Restoring a 'fixed-ram' enabled migration stream would require reading
> from specific offsets in the file so add a helper to QEMUFile that uses
> the newly introduced qio_channel_file_preadv.
>
> Signed-off-by: Nikolay Borisov
>
Mechanical change doing:
$ sed -i -e 's/PIIX4_PCI_DEVICE/PIIX4_ISA/g' $(git grep -l PIIX4_PCI_DEVICE)
$ sed -i -e 's/PIIX3_XEN_DEVICE/PIIX3_ISA_XEN/g' $(git grep -l
PIIX3_XEN_DEVICE)
$ sed -i -e 's/PIIX3_DEVICE/PIIX3_ISA/g' $(git grep -l PIIX3_DEVICE)
$ sed -i -e 's/PIIX3_PCI_DEVICE/PIIX_
Unify PIIX ISA (PCI function #0) as:
pci-piix3 -> piix-isa (abstract base class)
PIIX3 -> piix3-isa (PIIX3 implementation)
PIIX3-xen -> piix3-isa-xen (PIIX3 implementation with Xen extensions)
piix4-isa -> piix4-isa (PIIX4 implementation)
Alias previous names in the QDevA
On Fri, Feb 10, 2023 at 04:26:22PM +, Daniel P. Berrangé wrote:
> On Fri, Oct 28, 2022 at 01:39:04PM +0300, Nikolay Borisov wrote:
> > Introduce basic pwriteve/preadv support in the generic channel layer.
> > SPecific implementation will follow for the file channel as this is
> > required in or
See rationale in commit 38b5d79b2e ("qom: add helper
macro DEFINE_TYPES()").
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/piix3.c | 53 +-
1 file changed, 22 insertions(+), 31 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index a9c
Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro,
similarly to automatic conversion from commit 8063396bf3
("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/southbridge/piix.h | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
On Fri, Feb 10, 2023 at 04:32:19PM +, Peter Maydell wrote:
> On Fri, 10 Feb 2023 at 16:01, John Snow wrote:
> > On Fri, Feb 10, 2023, 5:41 AM Peter Maydell
> > wrote:
> >> On Fri, 10 Feb 2023 at 00:31, John Snow wrote:
> >> This confuses me. We work fine with Python 3.6 today.
> >
> >
> > T
On Mon, 6 Feb 2023 at 20:20, Thomas Huth wrote:
>
> On 06/02/2023 18.13, Peter Maydell wrote:
> > The 'singlestep' global variable is badly misnamed, because it has
> > nothing to do with single-stepping the emulation either via the gdb
> > stub or by emulation of architectural debug facilities.
On 01/02/2023 14:31, David Woodhouse wrote:
From: David Woodhouse
The guest is permitted to specify an arbitrary domain/bus/device/function
and INTX pin from which the callback IRQ shall appear to have come.
In QEMU we can only easily do this for devices that actually exist, and
even that requ
On Sat, 14 Jan 2023 at 16:13, wrote:
>
> From: Francesco Cagnin
>
> These helpers will be also used for HVF. Aside from reformatting a
> couple of comments for 'checkpatch.pl' and updating meson to compile
> 'hyp_gdbstub.c', this is just code motion.
>
> Signed-off-by: Francesco Cagnin
> ---
>
Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set (except for the top byte when TBI is enabled). Fix
the TTB1 check.
Reported-by: Ola Hugosson
Signed-off-by: Jean-Philippe Brucker
---
hw/arm/smmu-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deleti
isa_bus_irqs() register an array of input IRQs on
the ISA bus. Rename it as isa_bus_register_input_irqs().
Mechanical change using:
$ sed -i -e 's/isa_bus_irqs/isa_bus_register_input_irqs/g' \
$(git grep -wl isa_bus_irqs)
Signed-off-by: Philippe Mathieu-Daudé
---
hw/hppa/machine.c| 2 +
Two small changes to support TTB1. Note that I had to modify the Linux
driver in order to test this (see below), but other OSes might use TTB1.
Jean-Philippe Brucker (2):
hw/arm/smmu-common: Support 64-bit addresses
hw/arm/smmu-common: Fix TTB1 handling
hw/arm/smmu-common.c | 4 ++--
1 file
Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set. Ensure the IOMMU region covers all 64 bits.
Signed-off-by: Jean-Philippe Brucker
---
hw/arm/smmu-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/smmu-common.c b/hw/arm
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/isa-bus.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index d19826f96e..d12973103f 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -114,7 +114,7
Keep reference to ISA input IRQs in EbusState.
To emphasize input/output distinction, rename arrays
as isa_irqs_in / isa_irqs_out.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc64/sun4u.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/sparc64/sun4u.c b/h
The following code:
/* ISA devices */
i8259 = i8259_init(isa_bus, ...);
gives the false idea that the function is creating a i8259
device. Instead this function returns an array of input IRQs.
Rename the variable to clarify:
/* ISA devices */
isa_irqs_in = i8259_init(isa_bus,
On Fri, Oct 28, 2022 at 01:39:06PM +0300, Nikolay Borisov wrote:
> Add a generic QIOChannel feature SEEKABLE which would be used by the
> qemu_file* apis. For the time being this will be only implemented for
> file channels.
>
> Signed-off-by: Nikolay Borisov
> ---
> include/io/channel.h | 1 +
>
From: Philippe Mathieu-Daudé
Directly dispatch ISA IRQs to 'cpu_intr' output IRQ
by removing the intermediate via_isa_request_i8259_irq()
handler. Rename ISA IRQs array as 'isa_irqs_in' to
emphasize these are input IRQs.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Sign
Separate functions taking an ISABus* argument versus
functions taking a ISADevice* one.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/isa/isa.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 25acd5c34c..e81cd3
From: Philippe Mathieu-Daudé
When the i82378 model was added in commit a04ff940974 ("prep:
Add i82378 PCI-to-ISA bridge emulation") the i8259 model was
not yet QOM'ified. This happened later in commit 747c70af78f
("i8259: Convert to qdev").
Directly dispatch ISA IRQs to 'cpu_intr' output IRQ
by
isa_get_irq() was added in commit 3a38d437ca
("Add isa_reserve_irq()" Fri Aug 14 11:36:15 2009) as:
a temporary interface to be used to allocate ISA IRQs for
devices which have not yet been converted to qdev, and for
special cases which are not suited for qdev conversions,
such as
No point in inlining isa_bus_from_device() which is only
used at device realization time.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/isa-bus.c | 5 +
include/hw/isa/isa.h | 6 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/i
Trying to clarify the ISA API.
Most patches should be trivial enough,
so not much to describe here :)
Philippe Mathieu-Daudé (11):
hw/intc/i8259: Document i8259_init()
hw/isa/i82378: Rename output IRQ as 'cpu_intr'
hw/isa/i82378: Remove intermediate IRQ forwarder
hw/isa/vt82c686: Remove in
i8259_init() helper creates a i8259 device on an ISA bus,
connects its IRQ output to the parent's input IRQ, and
returns an array of 16 ISA input IRQs.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/i8259.c | 4 ++--
include/hw/intc/i8259.h | 10 +-
2 files changed, 11 insert
Commit a04ff94097 ("prep: Add i82378 PCI-to-ISA bridge
emulation") aimed to model the 2 output IRQs: CPU intr
and NMI. Commit 5039d6e235 ("i8257: remove cpu_request_exit
irq") removed the NMI IRQ.
Since this model only use the CPU interrupt, replace the
'out[2]' array by a single 'cpu_intr'.
Signe
Am 9. Februar 2023 09:04:49 UTC schrieb Bernhard Beschow :
>On Wed, Feb 8, 2023 at 1:08 AM Philippe Mathieu-Daudé
>wrote:
>
>> TYPE_PIIX3_IDE is a PCI function inheriting from QOM
>> TYPE_PCI_DEVICE. To be able to call the ISA specific
>> ide_init_ioport_isa(), we call this function passing
>>
On Fri, Oct 28, 2022 at 01:39:05PM +0300, Nikolay Borisov wrote:
> The upcoming 'fixed-ram' feature would require qemu to write data at
> specific offsets of the file. Add a minimal implementation of pwritev
> and expose it via the io_pwritev interface.
>
> Signed-off-by: Nikolay Borisov
> ---
>
On Fri, 10 Feb 2023 at 16:01, John Snow wrote:
> On Fri, Feb 10, 2023, 5:41 AM Peter Maydell wrote:
>> On Fri, 10 Feb 2023 at 00:31, John Snow wrote:
>> This confuses me. We work fine with Python 3.6 today.
>
>
> That won't last - Many tools such as mypy, pylint and flake8 which I use to
> mana
Am 23. Januar 2023 15:51:49 UTC schrieb Bernhard Beschow :
>
>
>Am 23. Januar 2023 09:25:51 UTC schrieb "Philippe Mathieu-Daudé"
>:
>>On 20/1/23 13:22, Bernhard Beschow wrote:
>>> Am 13. Januar 2023 17:39:45 UTC schrieb Bernhard Beschow
>>> :
Am 13. Januar 2023 08:46:53 UTC schrieb "Phili
On Fri, Feb 10, 2023, 10:44 AM Markus Armbruster wrote:
> John Snow writes:
>
> > mypy can only narrow the type of `Mapping[str, ...].keys() & Set[str]`
> > to `AbstractSet[str]` and not a `Set[str]`. As a result, if the type of
> > an expression is changed to a Mapping[], mypy is unsure if the
On Fri, Feb 10, 2023 at 5:22 PM John Snow wrote:
>> Though part of me thinks that your new loop is slightly overengineered
>> and we should just require /usr/bin/env python3 and call it a day.
>
> Well, but that'd be a problem for CentOS 8, wouldn't it? python3 is gonna
> resolve to python3.6.
T
On Fri, Oct 28, 2022 at 01:39:04PM +0300, Nikolay Borisov wrote:
> Introduce basic pwriteve/preadv support in the generic channel layer.
> SPecific implementation will follow for the file channel as this is
> required in order to support migration streams with fixed location of
> each ram page.
>
On Fri, Feb 10, 2023, 11:17 AM Paolo Bonzini wrote:
> On Fri, Feb 10, 2023 at 4:28 PM John Snow wrote:
> > PS, while you're here, how does this new loop interfere with your
> "custom python specified" flag for meson? I think meson uses the version of
> python *it* detects and not the configure s
On Fri, Feb 10, 2023 at 4:28 PM John Snow wrote:
> PS, while you're here, how does this new loop interfere with your "custom
> python specified" flag for meson? I think meson uses the version of python
> *it* detects and not the configure script identified one, right? Does that
> mean that e.g.
On Fri, 10 Feb 2023 at 16:13, Juan Quintela wrote:
> Again, I don't know why it fails.
>
> diff --git a/tests/bench/meson.build b/tests/bench/meson.build
> index daefead58d..7477a1f401 100644
> --- a/tests/bench/meson.build
> +++ b/tests/bench/meson.build
> @@ -3,9 +3,11 @@ qht_bench = executable(
Peter Maydell wrote:
> On Fri, 10 Feb 2023 at 14:21, Juan Quintela wrote:
>>
>> Peter Maydell wrote:
>> > Fails to build the user-mode emulators:
>>
>> This is weird.
>
>> > https://gitlab.com/qemu-project/qemu/-/jobs/3749435025
>> >
>> > In file included from ../authz/base.c:24:
>> > ../authz/t
On Fri, Oct 28, 2022 at 01:39:03PM +0300, Nikolay Borisov wrote:
> In order to allow analyze-migration.py script to work with migration
> streams that have the 'fixed-ram' capability set it's required to have
> access to the stream's configuration object. This commit enables this
> by making migrat
On Tue, 7 Feb 2023 at 18:31, Mostafa Saleh wrote:
>
> GBPA register can be used to globally abort all
> transactions.
>
> It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
> ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
> be zero(Do not abort incoming transactions).
>
> Othe
Anton Kuchin wrote:
> On 02/02/2023 11:59, Juan Quintela wrote:
>> Anton Kuchin wrote:
>>> On 01/02/2023 16:26, Juan Quintela wrote:
Anton Kuchin wrote:
> On 19/01/2023 18:02, Stefan Hajnoczi wrote:
>> On Thu, 19 Jan 2023 at 10:29, Anton Kuchin
>> wrote:
>>> On 19/01/2023
Hi Thomas!
On Fri, 2023-02-10 at 16:52 +0100, Thomas Huth wrote:
> On 10/02/2023 16.23, John Paul Adrian Glaubitz wrote:
> > Hi!
> >
> > There is an unaddressed issue in qemu-user [1] which results in getresuid()
> > returning an incorrect UID due to a byte-swapping issue on sparc64.
>
> Oh, the
On Fri, 3 Feb 2023 at 18:16, Alex Bennée wrote:
>
> The two TCG tests for GICv2 and GICv3 are very heavy weight distros
> that take a long time to boot up, especially for an --enable-debug
> build. The total code coverage they give is:
>
> Overall coverage rate:
> lines..: 11.2% (59584 o
On Mon, 6 Feb 2023 at 22:35, Philippe Mathieu-Daudé wrote:
>
> Missing review: 1-3, 5, 9-10
>
> Few cleanups while using link properties between CPU/NVIC:
> - Simplify ID_PFR1 on useremu
> - Move NVIC helpers to "hw/intc/armv7m_nvic.h"
>
> Since v1: addressed Richard's reviews
> - Do not restrict
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