On 1/3/23 01:38, fanwenjie wrote:
On linux user mode, CPUX86State::gdt::base from Different CPUX86State Objects
have same value, It is incorrect! Every CPUX86State::gdt::base Must points to
independent memory space.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1405
Signed-off-by: fa
Ping.
r~
On 1/6/23 15:06, Richard Henderson wrote:
Although we still can't use ldrd and strd for all operations,
increase the chances by getting the register allocation correct.
Signed-off-by: Richard Henderson
---
v3 was patch 5 in a larger patch set:
https://lore.kernel.org/qemu-devel
Ping.
r~
On 1/8/23 15:42, Richard Henderson wrote:
Small patch for exit_tb. Large reorg for goto_tb, primarily aimed at
fixing a race condition in which a host thread gets suspended in the
middle of executing a two insn sequence, and the sequence is updated.
The updated second insn does not ma
On 1/14/23 13:29, Mark Cave-Ayland wrote:
The FPSR quotient byte should be set to the value of the quotient and not the
result. Manually calculate the quotient in the frem helper in round to nearest
even mode (note this is different from the quotient calculated internally for
fmod), and use it to
On 1/12/23 05:28, Alessandro Di Federico wrote:
fpu/softfloat.c
Something I happened to notice while doing other triage:
https://gitlab.com/qemu-project/qemu/-/issues/1375
This is an x86 problem that currently has no solution, but ought to be trivial with the
changes to softfloat re
Failure to truncate the inputs results in garbage for the carry-out.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1373
Signed-off-by: Richard Henderson
---
tests/tcg/x86_64/adox.c | 69
target/i386/tcg/emit.c.inc | 2 +
tests/tcg/x86_64
We did not correctly handle N >= operand size.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1374
Signed-off-by: Richard Henderson
---
tests/tcg/i386/test-i386-bmi2.c | 3 +++
target/i386/tcg/emit.c.inc | 14 +++---
2 files changed, 10 insertions(+), 7 deletions(-)
diff
The FPSR quotient byte should be set to the value of the quotient and not the
result. Switch from using floatx80_mod() to floatx80_modrem() which returns
the quotient as a uint64_t which can be used for the quotient byte.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: R
This enables the quotient parameter to be changed from int32_t to uint32_t and
also allows the extra sign logic in make_quotient() to be removed.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Reviewed-by: Laurent Vivier
---
target/m68k/fpu_helper.c | 23 +--
This series is taken from my MacOS branch and fixes setting the FPSR quotient
byte for the fmod and frem instructions which was causing the MacOS _Pack5
SANE trancendentals implementation to return incorrect values for sin() and
cos().
The first 2 patches update make_quotient() to take separate si
The FPSR quotient byte should be set to the value of the quotient and not the
result. Manually calculate the quotient in the frem helper in round to nearest
even mode (note this is different from the quotient calculated internally for
fmod), and use it to set the quotient byte accordingly.
Signed-
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
target/m68k/fpu_helper.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
index fdc4937e29..0932c464fd 1006
Fix the instruction, and improve the test harness to better
handle 32-bit insns with 64-bit inputs.
r~
Richard Henderson (2):
tests/tcg/i386: Introduce and use reg_t consistently
target/i386: Fix BEXTR instruction
tests/tcg/i386/test-i386-bmi2.c | 194 +---
targ
There were two problems here: not limiting the input to operand bits,
and not correctly handling large extraction length.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1372
Signed-off-by: Richard Henderson
---
tests/tcg/i386/test-i386-bmi2.c | 12
target/i386/tcg/emit.c.in
Define reg_t based on the actual register width.
Define the inlines using that type. This will allow
input registers to 32-bit insns to be set to 64-bit
values on x86-64, which allows testing various edge cases.
Signed-off-by: Richard Henderson
---
tests/tcg/i386/test-i386-bmi2.c | 182
January 13, 2023 7:30 AM, "Philippe Mathieu-Daudé" wrote:
> On 13/1/23 12:05, Philippe Mathieu-Daudé wrote:
>
>> Per https://www.haiku-os.org/guides/daily-tasks/updating-system we
>> can keep the box image in sync with its repo by using:
>> # pkgman add https://eu.hpkg.haiku-os.org/haiku/r1beta3
Signed-off-by: Bernhard Beschow
---
hw/i386/acpi-microvm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c
index d8a444d06c..fec22d85c1 100644
--- a/hw/i386/acpi-microvm.c
+++ b/hw/i386/acpi-microvm.c
@@ -26,6 +26,7 @@
#incl
Ammends commit 3db119da7915 'pc: acpi: switch to AML API composed DSDT'.
Signed-off-by: Bernhard Beschow
---
hw/i386/acpi-build.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 0be3960a37..428328dc2d 100644
--- a/hw/i386/acpi-build.c
+++ b/
The only function ever assigned to AcpiDeviceIfClass::madt_cpu is
pc_madt_cpu_entry() which doesn't use the AcpiDeviceIf parameter.
Signed-off-by: Bernhard Beschow
---
include/hw/acpi/acpi_dev_interface.h | 3 +--
include/hw/i386/pc.h | 6 ++
hw/acpi/acpi-x86-stub.c
This series resolves the AcpiDeviceIfClass::madt_cpu function pointer. It turns
out that it isn't needed and it even frees the ACPI controllers from assigning
it an x86 specific function. This is especially interesting for the PIIX4 PM
which is also used in MIPS only contexts.
Furthermore, the ser
Signed-off-by: Bernhard Beschow
---
include/hw/acpi/acpi_aml_interface.h | 11 +++
hw/i2c/smbus_ich9.c | 5 +
hw/isa/lpc_ich9.c| 5 +
hw/isa/piix3.c | 5 +
4 files changed, 14 insertions(+), 12 deletions(-)
diff --
When removing the "hw/boards.h" include from
hw/acpi/acpi_dev_interface.h, these include directives must be added to make
the code compile again.
Signed-off-by: Bernhard Beschow
---
hw/acpi/hmat.h | 3 ++-
hw/acpi/cpu.c| 2 ++
hw/acpi/hmat.c | 1 +
hw/acpi/memory_
Signed-off-by: Bernhard Beschow
---
include/hw/isa/isa.h | 1 -
hw/isa/isa-bus.c | 10 --
2 files changed, 11 deletions(-)
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 6c8a8a92cb..25acd5c34c 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -86,7 +86,
This class attribute was always set to pc_madt_cpu_entry().
pc_madt_cpu_entry() is architecture dependent and was assigned to the
attribute even in architecture agnostic code such as in hw/acpi/piix4.c
and hw/isa/lpc_ich9. Not having to set madt_cpu there resolves the
assumption that these device m
It should be possible to reuse cache built by previous iteration
to process next executables. Processed dependencies are already
skipped later based on dll name.
Changes for v2:
(1) changed variable name
(2) changed wording in description
Signed-off-by: Arthur Sengileyev
Reviewed-by: Bin Meng
-
On Sat, 14 Jan 2023, Akihiko Odaki wrote:
On 2023/01/13 22:43, BALATON Zoltan wrote:
On Thu, 5 Jan 2023, BALATON Zoltan wrote:
Hello,
I got reports from several users trying to run AmigaOS4 on sam460ex on
Apple silicon Macs that they get missing graphics that I can't reproduce
on x86_64. Wit
We forgot to set cc_src, which is used for computing C.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1370
Signed-off-by: Richard Henderson
---
target/i386/tcg/emit.c.inc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
inde
On Sat, Jan 14, 2023 at 09:01:45AM -0800, Peter Delevoryas wrote:
> This cleans up some of the code we have creating at24c-eeprom objects in the
> Aspeed and Nuvoton files, and adds an example of how to initialize a FRUID
> EEPROM with static data using I2C transfers.
>
> Initially I was going to
Signed-off-by: Peter Delevoryas
---
hw/arm/aspeed.c | 95 ++---
1 file changed, 43 insertions(+), 52 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 1f9799d4321e..c929c61d582a 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -660
Signed-off-by: Peter Delevoryas
---
hw/nvram/eeprom_at24c.c | 15 +++
include/hw/nvram/eeprom_at24c.h | 2 ++
2 files changed, 17 insertions(+)
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
index 0c27eae2b354..69565a420c28 100644
--- a/hw/nvram/eeprom_at24c.
This cleans up some of the code we have creating at24c-eeprom objects in the
Aspeed and Nuvoton files, and adds an example of how to initialize a FRUID
EEPROM with static data using I2C transfers.
Initially I was going to propose a patch to update the at24c-eeprom realize
function to incorporate s
Signed-off-by: Peter Delevoryas
---
hw/arm/npcm7xx_boards.c | 20 +---
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 6bc6f5d2fe29..9b31207a06e9 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards
Signed-off-by: Peter Delevoryas
---
hw/arm/aspeed.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 55f114ef729f..1f9799d4321e 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -17,6 +17,7 @@
#include "hw/i2c/i2c_mux_pca95
Signed-off-by: Peter Delevoryas
---
hw/arm/aspeed.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index c929c61d582a..4ac8ff11a835 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -922,6 +922,52 @@ sta
Signed-off-by: Peter Delevoryas
---
hw/nvram/eeprom_at24c.c | 10 ++
include/hw/nvram/eeprom_at24c.h | 10 ++
2 files changed, 20 insertions(+)
create mode 100644 include/hw/nvram/eeprom_at24c.h
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
index 2d4d8b9
From: Francesco Cagnin
Signed-off-by: Francesco Cagnin
---
target/arm/hvf/hvf.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index c63e8da6a5..87c531508e 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1807,6 +1807,10 @@ in
From: Francesco Cagnin
This patch series aims to add gdbstub support to HVF (the 'QEMU
accelerator on macOS that employs Hypervisor.framework') on Apple
Silicon hosts.
The proposed implementation, structured like the KVM counterpart,
handles single-stepping, software breakpoints, hardware breakp
From: Francesco Cagnin
Support is added for single-stepping, software breakpoints, hardware
breakpoints and watchpoints. The code has been structured like the KVM
counterpart (and many parts are basically identical).
Guests can be debugged through the gdbstub.
While guest debugging is enabled,
From: Francesco Cagnin
These helpers will be also used for HVF. Aside from reformatting a
couple of comments for 'checkpatch.pl' and updating meson to compile
'hyp_gdbstub.c', this is just code motion.
Signed-off-by: Francesco Cagnin
---
target/arm/hyp_gdbstub.c | 242 +
https://patchew.org/QEMU/20230114125029.7395a547.hc...@poolhem.se/
complains that "patch is empty", so here is my fifth attempt...
regards Henrik
SUN Type 4, 5 and 5c keyboards have dip switches to choose the language
layout of the keyboard. Solaris makes an ioctl to query the value of the
dipsw
On Sat, Jan 14, 2023 at 1:18 AM Daniel Henrique Barboza
wrote:
>
> Recent hw/risc/boot.c changes caused a regression in an use case with
> the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel'
> stopped working. The reason seems to be that Xvisor is using 64 bit to
> encode the 32 bit
This is my fourth attempt to contribute the patch which allows the emulation
of different keyboard layouts on sparc which uses a dip switch on the keyboard
for those settings.
After my third attempt I falsely thought that sourcehut stripped off my
signed-off line, but it was me who forgot to call
42 matches
Mail list logo
