On 06/12/2022 23.22, Richard Henderson wrote:
On 12/6/22 13:29, Ilya Leoshkevich wrote:
On Thu, Dec 01, 2022 at 10:51:49PM -0800, Richard Henderson wrote:
This reverts 829e1376d940 ("tcg/s390: Introduce TCG_REG_TB"), and
several follow-up patches. The primary motivation is to reduce the
less-t
On 3/12/22 18:57, Richard Henderson wrote:
Failure to set pc_succ_insn may result in a TB covering zero bytes,
which triggers an assert within the code generator.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224
Signed-off-by: Richard Henderson
---
targe
On Sun, Dec 4, 2022 at 3:58 AM Richard Henderson
wrote:
>
> Failure to set pc_succ_insn may result in a TB covering zero bytes,
> which triggers an assert within the code generator.
>
> Cc: qemu-sta...@nongnu.org
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224
> Signed-off-by: Richa
On Tue, Dec 06, 2022 at 08:02:24PM +0800,
Chao Peng wrote:
> On Mon, Dec 05, 2022 at 02:49:59PM -0800, Isaku Yamahata wrote:
> > On Fri, Dec 02, 2022 at 02:13:45PM +0800,
> > Chao Peng wrote:
> >
> > > A large page with mixed private/shared subpages can't be mapped as large
> > > page since its
On Tue, Dec 06, 2022 at 07:56:23PM +0800,
Chao Peng wrote:
> > > - if (unlikely(kvm->mmu_invalidate_in_progress) &&
> > > - hva >= kvm->mmu_invalidate_range_start &&
> > > - hva < kvm->mmu_invalidate_range_end)
> > > - return 1;
> > > + if (unlikely(k
pcie_sriov.h needs PCI_NUM_REGIONS from pci.h, but doesn't include it.
pci.h must be included before pcie_sriov.h or else compile fails.
Adding #include "pci/pci.h" to pcie_sriov would be wrong, because it
would close an inclusion loop: pci.h includes pcie.h (for
PCIExpressDevice) includes pcie_sr
On Sun, Dec 4, 2022 at 3:58 AM Richard Henderson
wrote:
>
> Failure to set pc_succ_insn may result in a TB covering zero bytes,
> which triggers an assert within the code generator.
>
> Cc: qemu-sta...@nongnu.org
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224
> Signed-off-by: Richa
On Mon, Dec 5, 2022 at 4:54 PM Bin Meng wrote:
>
> The priv spec v1.12 says:
>
> If no PMP entry matches an M-mode access, the access succeeds. If
> no PMP entry matches an S-mode or U-mode access, but at least one
> PMP entry is implemented, the access fails. Failed accesses generate
> an
On Fri, Dec 2, 2022 at 12:10 AM Bin Meng wrote:
>
> The pending register upper limit is currently set to
> plic->num_sources >> 3, which is wrong, e.g.: considering
> plic->num_sources is 7, the upper limit becomes 0 which fails
> the range check if reading the pending register at pending_base.
>
On Fri, Dec 2, 2022 at 12:09 AM Bin Meng wrote:
>
> "hartid-base" and "priority-base" are zero by default. There is no
> need to initialize them to zero again.
What is the defaults change though? I feel like these are worth leaving in
Alistair
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/op
On Fri, Dec 2, 2022 at 12:10 AM Bin Meng wrote:
>
> At present the SiFive PLIC model "priority-base" expects interrupt
> priority register base starting from source 1 instead source 0,
> that's why on most platforms "priority-base" is set to 0x04 except
> 'opentitan' machine. 'opentitan' should ha
On Fri, Dec 2, 2022 at 12:11 AM Bin Meng wrote:
>
> Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt
> machine")
> changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which
> is VIRTIO_NDEV and also used as the value of "riscv,ndev" property
> in the dtb. Unf
On Fri, Dec 2, 2022 at 12:11 AM Bin Meng wrote:
>
> At present magic number is used to create "riscv,ndev" property
> in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
> is used to instantiate the PLIC model instead.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alista
On Fri, Dec 2, 2022 at 12:12 AM Bin Meng wrote:
>
> Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
> supports 52 interrupt sources while G000 supports 51 interrupt sources.
>
> We use the value of G002 and G003, so it is 53 (including source 0).
>
> [1] G000 manual:
> https:/
On Fri, Dec 2, 2022 at 12:11 AM Bin Meng wrote:
>
> Per chapter 6.5.2 in [1], the number of interupt sources including
> interrupt source 0 should be 187.
>
> [1] PolarFire SoC MSS TRM:
> https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_So
On Fri, Dec 2, 2022 at 12:12 AM Bin Meng wrote:
>
> At present the default value of "num-sources" property is zero,
> which does not make a lot of sense, as in sifive_plic_realize()
> we see s->bitfield_words is calculated by:
>
> s->bitfield_words = (s->num_sources + 31) >> 5;
>
> if the we don
On Fri, Dec 2, 2022 at 12:15 AM Bin Meng wrote:
>
> At present the PLIC config parser can only handle legal config string
> like "MS,MS". However if a config string like ",MS,MS,,MS,MS,," is
> given the parser won't get the correct configuration.
>
> This commit improves the config parser to make
On Wed, Nov 30, 2022 at 11:56 AM Tommy Wu wrote:
>
> The watchdog timer is in the always-on domain device of HiFive 1 rev b,
> so this patch added the AON device to the sifive_e machine. This patch
> only implemented the functionality of the watchdog timer.
>
> Signed-off-by: Tommy Wu
> ---
> hw
On Thu, Oct 6, 2022 at 12:52 AM Christoph Muellner
wrote:
>
> This patch adds support for the Zawrs ISA extension.
> Given the current (incomplete) implementation of reservation sets
> there seems to be no way to provide a full emulation of the WRS
> instruction (wake on reservation set invalidati
On Mon, Nov 28, 2022 at 2:59 AM Jim Shu wrote:
>
> If the number of interrupt is not multiple of 32, PLIC will have
> out-of-bound access to source_priority array. Compute the number of
> interrupt in the last word to avoid this out-of-bound access of array.
>
> Signed-off-by: Jim Shu
Thanks!
A
Hi,
This patch implements CANFD controller for xlnx-versal-virt machine. There are
two controllers CANFD0@0xFF06_ and CANFD1@0xFF07_ are connected to the
machine.
Also, added basic qtests for data exchange between both the controllers in
various supported configs.
Changelog:
v2->v3:
C
The Xilinx Versal CANFD controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.
Signed-off-by: Vikram Garhwal
---
hw/net/can/meson.build |1 +
hw/net/can/trace-events
Signed-off-by: Vikram Garhwal
Reviewed-by: Peter Maydell
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6966490c94..a76221f260 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1753,7 +1753,7 @@ M: Francisco Iglesias
S: Maintain
Connect CANFD0 and CANFD1 on the Versal-virt machine and update xlnx-versal-virt
document with CANFD command line examples.
Signed-off-by: Vikram Garhwal
---
docs/system/arm/xlnx-versal-virt.rst | 31 ++
hw/arm/xlnx-versal-virt.c| 48
hw/a
The QTests perform three tests on the Xilinx VERSAL CANFD controller:
Tests the CANFD controllers in loopback.
Tests the CANFD controllers in normal mode with CAN frame.
Tests the CANFD controllers in normal mode with CANFD frame.
Signed-off-by: Vikram Garhwal
Acked-by: Thomas Huth
R
Connect CANFD0 and CANFD1 on the Versal-virt machine and update xlnx-versal-virt
document with CANFD command line examples.
Signed-off-by: Vikram Garhwal
---
docs/system/arm/xlnx-versal-virt.rst | 31 ++
hw/arm/xlnx-versal-virt.c| 48
hw/a
On 12/6/22 16:22, Richard Henderson wrote:
Wouldn't it be worth keeping XILF/XIFH here?
I don't know. It's difficult for me to guess whether a dependency chain like
val -> xor -> xor
(3 insns with serial dependencies) is better than
val --> xor
load -/
(3 insns, but only
在 2022/12/6 18:45, Philippe Mathieu-Daudé 写道:
On 6/12/22 11:28, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) wrote:
在 2022/12/6 17:07, Philippe Mathieu-Daudé 写道:
On 6/12/22 09:18, Longpeng(Mike) via wrote:
From: Longpeng
This allows the vhost device to batch the setup of
Connect CANFD0 and CANFD1 on the Versal-virt machine and update xlnx-versal-virt
document with CANFD command line examples.
Signed-off-by: Vikram Garhwal
---
docs/system/arm/xlnx-versal-virt.rst | 31 ++
hw/arm/xlnx-versal-virt.c| 48
hw/a
The Xilinx Versal CANFD controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.
Signed-off-by: Vikram Garhwal
---
hw/net/can/meson.build |1 +
hw/net/can/trace-events
Connect CANFD0 and CANFD1 on the Versal-virt machine and update xlnx-versal-virt
document with CANFD command line examples.
Signed-off-by: Vikram Garhwal
---
docs/system/arm/xlnx-versal-virt.rst | 31 ++
hw/arm/xlnx-versal-virt.c| 48
hw/a
Signed-off-by: Vikram Garhwal
Reviewed-by: Peter Maydell
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6966490c94..a76221f260 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1753,7 +1753,7 @@ M: Francisco Iglesias
S: Maintain
The QTests perform three tests on the Xilinx VERSAL CANFD controller:
Tests the CANFD controllers in loopback.
Tests the CANFD controllers in normal mode with CAN frame.
Tests the CANFD controllers in normal mode with CANFD frame.
Signed-off-by: Vikram Garhwal
Acked-by: Thomas Huth
R
Am 6. Dezember 2022 20:06:41 UTC schrieb Thomas Huth :
>The only code that is really, really target dependent is the apic-related
>code in rtc_policy_slew_deliver_irq(). By moving this code into the hw/i386/
>folder (renamed to rtc_apic_policy_slew_deliver_irq()) and passing this
>function as pa
On Tue, 6 Dec 2022, Thomas Huth wrote:
The only code that is really, really target dependent is the apic-related
code in rtc_policy_slew_deliver_irq(). By moving this code into the hw/i386/
folder (renamed to rtc_apic_policy_slew_deliver_irq()) and passing this
function as parameter to mc146818_r
Hi Peter,
On 11/10/22 9:07 AM, Peter Maydell wrote:
On Sat, 22 Oct 2022 at 06:48, Vikram Garhwal wrote:
The Xilinx Versal CANFD controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.
On 12/6/22 13:29, Ilya Leoshkevich wrote:
On Thu, Dec 01, 2022 at 10:51:49PM -0800, Richard Henderson wrote:
This reverts 829e1376d940 ("tcg/s390: Introduce TCG_REG_TB"), and
several follow-up patches. The primary motivation is to reduce the
less-tested code paths, pre-z10. Secondarily, this a
It seems not super clear on when iova_tree is used, and why. Add a rich
comment above iova_tree to track why we needed the iova_tree, and when we
need it.
Also comment for the map/unmap messages, on how they're used and
implications (e.g. unmap can be larger than the mapped ranges).
Suggested-by
On Tue, Dec 06, 2022 at 05:10:39PM -0500, Peter Xu wrote:
> It seems not super clear on when iova_tree is used, and why. Add a rich
> comment above iova_tree to track why we needed the iova_tree, and when we
> need it.
>
> Also comment for the map/unmap messages, on how they're used and
> implica
It seems not super clear on when iova_tree is used, and why. Add a rich
comment above iova_tree to track why we needed the iova_tree, and when we
need it.
Also comment for the map/unmap messages, on how they're used and
implications (e.g. unmap can be larger than the mapped ranges).
Suggested-by
On Tue, Dec 06, 2022 at 05:28:01PM +0100, Eric Auger wrote:
>
>
> On 12/6/22 17:05, Peter Xu wrote:
> > On Tue, Dec 06, 2022 at 02:16:32PM +0100, Eric Auger wrote:
> >> Hi Peter,
> >> On 12/6/22 00:28, Peter Xu wrote:
> >>> On Mon, Dec 05, 2022 at 12:23:20PM +0800, Jason Wang wrote:
> On Fri
On Thu, Dec 01, 2022 at 10:52:00PM -0800, Richard Henderson wrote:
> There is an older form that produces per-byte results,
> and a newer form that produces per-register results,
> and a vector form that produces per-element results.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-tar
On Tue, 2022-12-06 at 15:35 +0100, Pierre Morel wrote:
>
> On 12/6/22 14:35, Janis Schoetterl-Glausch wrote:
> > On Tue, 2022-12-06 at 11:32 +0100, Pierre Morel wrote:
> > >
> > > On 12/6/22 10:31, Janis Schoetterl-Glausch wrote:
> > > > On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
> >
On Thu, Dec 01, 2022 at 10:51:59PM -0800, Richard Henderson wrote:
> Reuse code from movcond to conditionally copy a2 to dest,
> based on the condition codes produced by FLOGR.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target-con-set.h | 1 +
> tcg/s390x/tcg-target.c.inc |
On Thu, Dec 01, 2022 at 10:51:58PM -0800, Richard Henderson wrote:
> The new select instruction provides two separate register inputs,
> whereas the old load-on-condition instruction overlaps one of the
> register inputs with the destination.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390
On Thu, Dec 01, 2022 at 10:51:57PM -0800, Richard Henderson wrote:
> Generalize movcond to support pre-computed conditions, and the same
> set of arguments at all times. This will be assumed by a following
> patch, which needs to reuse tgen_movcond_int.
>
> Signed-off-by: Richard Henderson
> ---
On Tue, 6 Dec 2022, 14:02 Ilya Leoshkevich, wrote:
> On Thu, Dec 01, 2022 at 10:51:53PM -0800, Richard Henderson wrote:
> > The MIE2 facility adds 3-operand versions of multiply.
> >
> > Signed-off-by: Richard Henderson
> > ---
> > tcg/s390x/tcg-target-con-set.h | 1 +
> > tcg/s390x/tcg-target
On 6/12/22 21:06, Thomas Huth wrote:
The only code that is really, really target dependent is the apic-related
code in rtc_policy_slew_deliver_irq(). By moving this code into the hw/i386/
folder (renamed to rtc_apic_policy_slew_deliver_irq()) and passing this
function as parameter to mc146818_rtc
On Thu, Dec 01, 2022 at 10:51:56PM -0800, Richard Henderson wrote:
> Return both regular and inverted condition codes from tgen_cmp2.
> This lets us choose after the fact which comparision we want.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target.c.inc | 25 +
On 6/12/22 20:23, Vladimir Sementsov-Ogievskiy wrote:
IF addrstr == "[" and websocket is true, hostlen becomes 0 and we try
to access addrstr[hostlen-1] which is bad idea.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
ui/vnc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
On Thu, Dec 01, 2022 at 10:51:55PM -0800, Richard Henderson wrote:
> This is andc, orc, nand, nor, eqv.
> We can use nor for implementing not.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target-con-set.h | 1 +
> tcg/s390x/tcg-target.h | 25 +
> tcg/s390x/tcg-ta
The only code that is really, really target dependent is the apic-related
code in rtc_policy_slew_deliver_irq(). By moving this code into the hw/i386/
folder (renamed to rtc_apic_policy_slew_deliver_irq()) and passing this
function as parameter to mc146818_rtc_init(), we can make the RTC completely
On Thu, Dec 01, 2022 at 10:51:54PM -0800, Richard Henderson wrote:
> The MIE2 facility adds a 3-operand signed 64x64->128 multiply.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target-con-set.h | 1 +
> tcg/s390x/tcg-target.h | 2 +-
> tcg/s390x/tcg-target.c.inc | 8 +++
On Thu, Dec 01, 2022 at 10:51:53PM -0800, Richard Henderson wrote:
> The MIE2 facility adds 3-operand versions of multiply.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target-con-set.h | 1 +
> tcg/s390x/tcg-target.h | 1 +
> tcg/s390x/tcg-target.c.inc | 34 +
On Thu, Dec 01, 2022 at 10:51:52PM -0800, Richard Henderson wrote:
> There are multiple variations, with different fields.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target.c.inc | 47 +-
> 1 file changed, 26 insertions(+), 21 deletions(-)
Rev
On Thu, Dec 01, 2022 at 10:51:51PM -0800, Richard Henderson wrote:
> One has 3 register arguments; the other has 2 plus an m3 field.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target.c.inc | 57 +-
> 1 file changed, 32 insertions(+), 25 deletio
On Thu, Dec 01, 2022 at 10:51:50PM -0800, Richard Henderson wrote:
> Add one instead of dropping odd addresses to the constant pool.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target.c.inc | 15 ---
> 1 file changed, 8 insertions(+), 7 deletions(-)
Reviewed-by: Ilya
On Thu, Dec 01, 2022 at 10:51:49PM -0800, Richard Henderson wrote:
> This reverts 829e1376d940 ("tcg/s390: Introduce TCG_REG_TB"), and
> several follow-up patches. The primary motivation is to reduce the
> less-tested code paths, pre-z10. Secondarily, this allows the
> unconditional use of TCG_TA
IF addrstr == "[" and websocket is true, hostlen becomes 0 and we try
to access addrstr[hostlen-1] which is bad idea.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
ui/vnc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ui/vnc.c b/ui/vnc.c
index 88f55cbf3c..8830bfe382 1006
This was added to support passt:
https://passt.top
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1903470
Title:
qemu 5.1.0: Add UNIX socket support for netdev socket
Status in QEMU:
Expired
Bu
This will be available in the next QEMU release (7.2) under a sligthly
different form:
"-netdev stream" for TCP socket and "-netdev dgram" for UDP socket.
Both support inet and unix sockets. See qemu(1).
--
You received this bug notification because you are a member of qemu-
devel-ml, which is
On Tue, Dec 6, 2022 at 5:32 AM Dr. David Alan Gilbert
wrote:
> From intel arch manual 19.3:
> '..16-bit ports should be aligned to even addresses (0, 2, 4, ...) so
> that all 16 bits can be transferred in a
> single bus cycle. Likewise, 32-bit ports should be aligned to addresses
> that are mu
在 2022/12/7 0:00, Peter Xu 写道:
Hi, Shivam,
On Tue, Dec 06, 2022 at 11:18:52AM +0530, Shivam Kumar wrote:
[...]
Note
--
--
We understand that there is a good scope of improvement in the current
implementation. Here is a list of things we are working on:
1) Adding dirty quot
On 12/6/22 11:09, Philippe Mathieu-Daudé wrote:
On 6/12/22 16:38, Claudio Fontana wrote:
On 12/6/22 15:53, Claudio Fontana wrote:
On 5/17/21 13:11, Philippe Mathieu-Daudé wrote:
Guard declarations within hwaddr.h against inclusion
from user-mode emulation.
To make it clearer this header is sy
On 6/12/22 16:38, Claudio Fontana wrote:
On 12/6/22 15:53, Claudio Fontana wrote:
On 5/17/21 13:11, Philippe Mathieu-Daudé wrote:
Guard declarations within hwaddr.h against inclusion
from user-mode emulation.
To make it clearer this header is sysemu specific,
move it to the sysemu/ directory.
JFYI I miss the ability to use Unix socket right now.. I'm trying to use
vagrant + vagrant-qemu + socket_vmnet on Macbook m1. It'd be MUCH easier
to connect QEMU to the socket_vmnet' Unix socket directly w/o any
wrappers..
--
You received this bug notification because you are a member of qemu-
de
On 12/6/22 17:05, Peter Xu wrote:
> On Tue, Dec 06, 2022 at 02:16:32PM +0100, Eric Auger wrote:
>> Hi Peter,
>> On 12/6/22 00:28, Peter Xu wrote:
>>> On Mon, Dec 05, 2022 at 12:23:20PM +0800, Jason Wang wrote:
On Fri, Dec 2, 2022 at 12:25 AM Peter Xu wrote:
> It seems not super clear o
On 12/6/22 10:02, Peter Maydell wrote:
On Tue, 6 Dec 2022 at 15:56, Philippe Mathieu-Daudé wrote:
On 6/12/22 13:30, Dr. David Alan Gilbert wrote:
I don't know that bit of qemu well enough to know whether the cpu part
of qemu should be splitting the unaligned accesses or not.
All I/O accesses
On 6/12/22 15:38, Gerd Hoffmann wrote:
Hi,
So on x86 we can have 16-bit I/O accesses unaligned to 8-bit boundary?
Yes.
So I _think_ today we should be good with removing the x86 line:
-# ifdef TARGET_I386
-{ 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
-#
On Tue, Dec 06, 2022 at 02:16:32PM +0100, Eric Auger wrote:
> Hi Peter,
> On 12/6/22 00:28, Peter Xu wrote:
> > On Mon, Dec 05, 2022 at 12:23:20PM +0800, Jason Wang wrote:
> >> On Fri, Dec 2, 2022 at 12:25 AM Peter Xu wrote:
> >>> It seems not super clear on when iova_tree is used, and why. Add a
On Tue, 6 Dec 2022 at 15:56, Philippe Mathieu-Daudé wrote:
>
> On 6/12/22 13:30, Dr. David Alan Gilbert wrote:
> > I don't know that bit of qemu well enough to know whether the cpu part
> > of qemu should be splitting the unaligned accesses or not.
> All I/O accesses are gated thru access_with_adj
On Tue, Dec 06, 2022 at 02:06:54PM +0100, Eric Auger wrote:
> >>> + * current VTD address space, because all UNMAP (including iotlb or
> >>> + * dev-iotlb) events can be transparently delivered to !MAP iommu
> >>> + * notifiers.
> >> because all UNMAP notifications (iotlb or dev-iotlb)
Hi, Shivam,
On Tue, Dec 06, 2022 at 11:18:52AM +0530, Shivam Kumar wrote:
[...]
> > Note
> > --
> > --
> >
> > We understand that there is a good scope of improvement in the current
> > implementation. Here is a list of things we are working on:
> > 1) Adding dirty quota as a mi
On Tue, 2022-12-06 at 09:49 -0600, Richard Henderson wrote:
> On 12/6/22 09:28, Ilya Leoshkevich wrote:
> > > + switch (TCG_TARGET_CALL_ARG_I64) {
> > > + case TCG_CALL_ARG_EVEN:
> >
> > On a s390x host with gcc-11.0.1-0.3.1.ibm.fc34.s390x I get:
> >
> > FAILED: libqemu-aarc
On 6/12/22 13:30, Dr. David Alan Gilbert wrote:
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
Hi,
I'm trying to understand the x86 architecture-specific code in
hw/display/vga.c:
const MemoryRegionPortio vbe_portio_list[] = {
{ 0, 1, 2, .read = vbe_ioport_read_index,
On 12/6/22 09:28, Ilya Leoshkevich wrote:
+switch (TCG_TARGET_CALL_ARG_I64) {
+case TCG_CALL_ARG_EVEN:
On a s390x host with gcc-11.0.1-0.3.1.ibm.fc34.s390x I get:
FAILED: libqemu-aarch64-softmmu.fa.p/tcg_tcg.c.o
../tcg/tcg.c: In function ‘init_call_layout’:
../tcg/tcg.c
On Thu, Dec 01, 2022 at 10:51:48PM -0800, Richard Henderson wrote:
> Previously we hard-coded R2 and R3.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target-con-set.h | 4 ++--
> tcg/s390x/tcg-target-con-str.h | 8 +--
> tcg/s390x/tcg-target.c.inc | 43 +++
Hi,
On Tue, Dec 6, 2022 at 12:01 PM Chao Peng wrote:
>
> On Mon, Dec 05, 2022 at 09:23:49AM +, Fuad Tabba wrote:
> > Hi Chao,
> >
> > On Fri, Dec 2, 2022 at 6:19 AM Chao Peng
> > wrote:
> > >
> > > Currently in mmu_notifier invalidate path, hva range is recorded and
> > > then checked again
Hi,
On Fri, Dec 2, 2022 at 6:19 AM Chao Peng wrote:
>
> This new KVM exit allows userspace to handle memory-related errors. It
> indicates an error happens in KVM at guest memory range [gpa, gpa+size).
> The flags includes additional information for userspace to handle the
> error. Currently bit
On Mon, 21 Mar 2022 at 11:59, Alex Bennée wrote:
>
> At a couple of hundred bytes per notifier allocating one for every
> potential queue is very wasteful as most devices only have a few
> queues. Instead of having this handled statically dynamically assign
> them and track in a GPtrArray.
>
> [AJ
On 12/6/22 01:48, Philippe Mathieu-Daudé wrote:
On 6/12/22 05:17, Richard Henderson wrote:
Now that tcg can handle direct and indirect goto_tb simultaneously,
we can optimistically leave space for a direct branch and fall back
to loading the pointer from the TB for an indirect branch.
Signed-of
On 12/6/22 01:44, Philippe Mathieu-Daudé wrote:
On 6/12/22 05:17, Richard Henderson wrote:
This is always true for sparc64, so this is dead since 3a5f6805c7ca.
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 57 ++--
1 file changed, 22 ins
On 12/6/22 15:53, Claudio Fontana wrote:
> On 5/17/21 13:11, Philippe Mathieu-Daudé wrote:
>> Guard declarations within hwaddr.h against inclusion
>> from user-mode emulation.
>>
>> To make it clearer this header is sysemu specific,
>> move it to the sysemu/ directory.
>
> Hi Philippe,
>
> do we
On Thu, Dec 01, 2022 at 09:39:53PM -0800, Richard Henderson wrote:
> Pre-compute the function call layout for each helper at startup.
> Drop TCG_CALL_DUMMY_ARG, as we no longer need to leave gaps
> in the op->args[] array. This allows several places to stop
> checking for NULL TCGTemp, to which TC
Hi,
On Fri, Dec 2, 2022 at 6:18 AM Chao Peng wrote:
>
> In confidential computing usages, whether a page is private or shared is
> necessary information for KVM to perform operations like page fault
> handling, page zapping etc. There are other potential use cases for
> per-page memory attributes
On Mon, 17 May 2021 at 12:16, Philippe Mathieu-Daudé wrote:
>
> Guard declarations within hwaddr.h against inclusion
> from user-mode emulation.
They're all safe, though; none of them are target-dependent.
I wonder if we should move MemMapEntry somewhere else -- it's used
in less than 20 files a
Hi,
On Fri, Dec 2, 2022 at 6:18 AM Chao Peng wrote:
>
> From: "Kirill A. Shutemov"
>
> Introduce 'memfd_restricted' system call with the ability to create
> memory areas that are restricted from userspace access through ordinary
> MMU operations (e.g. read/write/mmap). The memory content is expe
On 5/17/21 13:11, Philippe Mathieu-Daudé wrote:
> Guard declarations within hwaddr.h against inclusion
> from user-mode emulation.
>
> To make it clearer this header is sysemu specific,
> move it to the sysemu/ directory.
Hi Philippe,
do we need include/exec/sysemu/... .h
as opposed to just use
From: Tianren Zhang
The pci option rom is a RAMBlock mapped from a rom file,
but in some cases of migration, the src and dest machine
may have rom files with different size, which causes the
migration to fail due to mismatch of RAMBlock size.
In those cases, we could make the migration more comp
On 11/29/22 18:42, Pierre Morel wrote:
The guest uses the STSI instruction to get information on the
CPU topology.
Let us implement the STSI instruction for the basis CPU topology
level, level 2.
Signed-off-by: Pierre Morel
---
target/s390x/cpu.h | 77 +++
hw/s390x/
On 6/12/22 15:32, Philippe Mathieu-Daudé wrote:
On 26/5/21 20:15, Richard Henderson wrote:
On 5/17/21 4:11 AM, Philippe Mathieu-Daudé wrote:
--- a/include/exec/hwaddr.h
+++ b/include/exec/sysemu/hwaddr.h
@@ -1,8 +1,9 @@
/* Define hwaddr if it exists. */
-#ifndef HWADDR_H
-#define HWADDR_H
+#
Hi,
> So on x86 we can have 16-bit I/O accesses unaligned to 8-bit boundary?
Yes.
> So I _think_ today we should be good with removing the x86 line:
>
> -# ifdef TARGET_I386
> -{ 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data
> },
> -# endif
Nope. Breaks vgabios.
On 12/6/22 14:35, Janis Schoetterl-Glausch wrote:
On Tue, 2022-12-06 at 11:32 +0100, Pierre Morel wrote:
On 12/6/22 10:31, Janis Schoetterl-Glausch wrote:
On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
We will need a Topology device to transfer the topology
during migration and to
On 26/5/21 20:15, Richard Henderson wrote:
On 5/17/21 4:11 AM, Philippe Mathieu-Daudé wrote:
--- a/include/exec/hwaddr.h
+++ b/include/exec/sysemu/hwaddr.h
@@ -1,8 +1,9 @@
/* Define hwaddr if it exists. */
-#ifndef HWADDR_H
-#define HWADDR_H
+#ifndef EXEC_SYSEMU_HWADDR_H
+#define EXEC_SYSEMU_
On Tue, Dec 06, 2022 at 11:18:03AM +0800, Jason Wang wrote:
> On Tue, Dec 6, 2022 at 7:19 AM Peter Xu wrote:
> >
> > Jason,
> >
> > On Mon, Dec 05, 2022 at 12:12:04PM +0800, Jason Wang wrote:
> > > I'm fine to go without iova-tree. Would you mind to post patches for
> > > fix? I can test and inclu
On Tue, 2022-12-06 at 11:32 +0100, Pierre Morel wrote:
>
> On 12/6/22 10:31, Janis Schoetterl-Glausch wrote:
> > On Tue, 2022-11-29 at 18:42 +0100, Pierre Morel wrote:
> > > We will need a Topology device to transfer the topology
> > > during migration and to implement machine reset.
> > >
> > >
Chao Peng writes:
> In confidential computing usages, whether a page is private or shared is
> necessary information for KVM to perform operations like page fault
> handling, page zapping etc. There are other potential use cases for
> per-page memory attributes, e.g. to make memory read-only (or
Hi jason,
On 11/29/22 09:10, Jason Wang wrote:
> Without dt mode, device IOTLB notifier won't work since guest won't
> send device IOTLB invalidation descriptor in this case. Let's fail
> early instead of misbehaving silently.
>
> Signed-off-by: Jason Wang
> ---
> hw/i386/intel_iommu.c | 8 +
Hi Jason,
On 11/29/22 09:10, Jason Wang wrote:
> Without caching mode, MAP notifier won't work correctly since guest
> won't send IOTLB update event when it establishes new mappings in the
> I/O page tables. Let's fail the IOMMU notifiers early instead of
> misbehaving silently.
>
> Signed-off-by:
Hi Peter,
On 12/6/22 00:28, Peter Xu wrote:
> On Mon, Dec 05, 2022 at 12:23:20PM +0800, Jason Wang wrote:
>> On Fri, Dec 2, 2022 at 12:25 AM Peter Xu wrote:
>>> It seems not super clear on when iova_tree is used, and why. Add a rich
>>> comment above iova_tree to track why we needed the iova_tree
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