On 6/12/22 01:18, David Woodhouse wrote:
On Mon, 2022-12-05 at 22:58 +0100, Philippe Mathieu-Daudé wrote:
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 22b681ca37..45aa9e40a5 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7069,6 +7069,8 @@ static Property x86_cpu_properti
On 6/12/22 05:17, Richard Henderson wrote:
Now that tcg can handle direct and indirect goto_tb simultaneously,
we can optimistically leave space for a direct branch and fall back
to loading the pointer from the TB for an indirect branch.
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-targ
On 6/12/22 05:17, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 6/12/22 05:17, Richard Henderson wrote:
This is always true for sparc64, so this is dead since 3a5f6805c7ca.
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 57 ++--
1 file changed, 22 insertions(+), 35 deletions(-)
@@ -1897,7 +1884,7
On 6/12/22 05:17, Richard Henderson wrote:
Install empty versions for !TCG_TARGET_HAS_direct_jump hosts.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 6 ++
tcg/mips/tcg-target.c.inc | 6 ++
tcg/riscv/tcg-target.c.inc | 6 ++
tcg/tci/tcg-target.c.inc | 6
On 6/12/22 05:17, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h| 3 +++
tcg/aarch64/tcg-target.h | 4
tcg/arm/tcg-target.h | 5 -
tcg/i386/tcg-target.h| 3 ---
tcg/loongarch64/tcg-target.h | 3 ---
tcg/mips/tcg-tar
On 6/12/22 05:17, Richard Henderson wrote:
The INDEX_op_goto_tb opcode needs no register allocation.
Split out a dedicated helper function for it.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4 ++
tcg/aarch64/tcg-target.c.inc | 40 +-
tcg/arm
On 6/12/22 05:17, Richard Henderson wrote:
This will shortly be used for more than reset.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 2 +-
accel/tcg/translate-all.c | 8
tcg/tcg.c | 4 ++--
3 files changed, 7 insertions(+), 7 deletions(-)
Re
On 6/12/22 05:40, Richard Henderson wrote:
Take the w^x split into account when computing the
pc-relative distance to an absolute pointer.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/loongarch64
On Mon, Dec 5, 2022 at 9:07 PM Eugenio Perez Martin wrote:
>
> On Mon, Dec 5, 2022 at 5:27 AM Jason Wang wrote:
> >
> > On Thu, Dec 1, 2022 at 5:29 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Thu, Dec 1, 2022 at 9:39 AM Jason Wang wrote:
> > > >
> > > > On Wed, Nov 30, 2022 at 3:07 PM Eu
On 6/12/22 05:17, Richard Henderson wrote:
Similar to the existing set_jmp_reset_offset. Include the
rw->rx address space coversion done by arm and s390x, and
Typo "conversion".
forgotten by mips and riscv.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 9 +
t
On 6/12/22 05:16, Richard Henderson wrote:
Test TCG_TARGET_HAS_direct_jump instead of testing an
implementation pointer.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc | 2 +-
tcg/loongarch64/tcg-target.c.inc | 2 +-
tcg/mips/
On 6/12/22 05:16, Richard Henderson wrote:
The INDEX_op_exit_tb opcode needs no register allocation.
Split out a dedicated helper function for it.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4
tcg/aarch64/tcg-target.c.inc | 22 ++
tcg/a
On 6/12/22 05:40, Richard Henderson wrote:
Take the w^x split into account when computing the
pc-relative distance to an absolute pointer.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathi
On Tue, Dec 6, 2022 at 1:04 AM Eugenio Pérez wrote:
>
> The state of the descriptors (avail or used) may not be recoverable just
> looking at the guest memory. Out of order used descriptor may override
> previous avail ones in the descriptor table or avail vring.
>
> Currently we're not migrating
On Mon, Dec 5, 2022 at 4:54 PM Bin Meng wrote:
>
> The priv spec v1.12 says:
>
> If no PMP entry matches an M-mode access, the access succeeds. If
> no PMP entry matches an S-mode or U-mode access, but at least one
> PMP entry is implemented, the access fails. Failed accesses generate
> an
On Tue, Dec 6, 2022 at 7:28 AM Peter Xu wrote:
>
> On Mon, Dec 05, 2022 at 12:23:20PM +0800, Jason Wang wrote:
> > On Fri, Dec 2, 2022 at 12:25 AM Peter Xu wrote:
> > >
> > > It seems not super clear on when iova_tree is used, and why. Add a rich
> > > comment above iova_tree to track why we nee
On Wed, Nov 30, 2022 at 11:56 AM Tommy Wu wrote:
>
> Create the AON device when we realize the sifive_e machine.
> This patch only implemented the functionality of the watchdog timer,
> not all the functionality of the AON device.
>
> Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
Alist
On Fri, Nov 18, 2022 at 8:57 AM Conor Dooley wrote:
>
> From: Conor Dooley
>
> Hey all,
> Apart from DDR (see [1]), these should be the last bits needed to get
> recent Linux kernels booting again for Icicle/PolarFire SoC. Previously,
> I had been disabling the hwrng and PCI but I keep forgetting
On Tue, Dec 06, 2022 at 06:57:39AM +0100, Alexandre Ghiti wrote:
>
> I can't find the sve* properties you're talking about, can you point them
> to me?
>
target/arm/cpu64.c: cpu_arm_get/set_vq() and arm_cpu_sve_finalize() and
aarch64_add_sve_properties().
Thanks,
drew
Hi Andrew,
On Thu, Dec 1, 2022 at 3:47 PM Andrew Jones wrote:
> On Thu, Dec 01, 2022 at 10:36:23AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes
> for
> > the machine's support at startup via the satp CSR register (done in
> > csr.c:val
On 21/11/22 4:24 am, Shivam Kumar wrote:
This patchset is the QEMU-side implementation of a (new) dirty "quota"
based throttling algorithm that selectively throttles vCPUs based on their
individual contribution to overall memory dirtying and also dynamically
adapts the throttle based on the av
Adjust the constraints to allow any int32_t for immediate
addition. Split immediate adds into addu16i + addi, which
covers quite a lot of the immediate space. For the hole in
the middle, load the constant into TMP0 instead.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-se
Regenerate with ADDU16I included.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-insn-defs.c.inc | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc
b/tcg/loongarch64/tcg-insn-defs.c.inc
index d162571856..c3c8669b4b 100644
From: Rui Wang
diff:
Imm Before After
addi.w rd, zero, 0 addi.w rd, zero, 0
lu52i.d rd, zero, 0
f800lu12i.w rd, -1 addi.w rd, zero, -2048
ori rd, rd, 2048
Based-on: 20221206041715.314209-1-richard.hender...@linaro.org
("[PATCH 00/22] tcg: exit_tb tidy, goto_tb reorg")
Includes:
* Disassembler from target/loongarch/.
* Improvements to movi by Rui Wang, with minor tweaks.
* Improvements to setcond.
* Implement movcond.
* Fix the same goto_tb
Reuse the decodetree based disassembler from
target/loongarch/ for tcg/loongarch64/.
The generation of decode-insns.c.inc into ./libcommon.fa.p/ could
eventually result in conflict, if any other host requires the same
trick, but this is good enough for now.
Signed-off-by: Richard Henderson
---
The old implementation replaces two insns, swapping between
b
nop
and
pcaddu18i tmp,
jirl zero, tmp, & 0x
There is a race condition in which a thread could be stopped at
the jirl, i.e. with the top of the address loaded, and when
restarted we have
Split out a helper function, tcg_out_setcond_int, which
does not always produce the complete boolean result, but
returns a set of flags to do so.
Accept all int32_t as constant input, so that LE/GT can
adjust the constant to LT.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.
Take the w^x split into account when computing the
pc-relative distance to an absolute pointer.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.h | 4 ++--
tcg/loongarch64/tcg-target.c.inc | 33
3 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/tcg/loongarch64/tcg-target-con-
The old ppc64 implementation replaces 2 or 4 insns, which leaves a race
condition in which a thread could be stopped at a PC in the middle of
the sequence, and when restarted does not see the complete address
computation and branches to nowhere.
The new implemetation replaces only one insn, swappi
The old sparc64 implementation may replace two insns, which leaves
a race condition in which a thread could be stopped at a PC in the
middle of the sequence, and when restarted does not see the complete
address computation and branches to nowhere.
The new implemetation replaces only one insn, swap
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h| 3 +++
tcg/aarch64/tcg-target.h | 4
tcg/arm/tcg-target.h | 5 -
tcg/i386/tcg-target.h| 3 ---
tcg/loongarch64/tcg-target.h | 3 ---
tcg/mips/tcg-target.h| 5 -
tcg/ppc/tcg-target.h
This is always true for sparc64, so this is dead since 3a5f6805c7ca.
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 57 ++--
1 file changed, 22 insertions(+), 35 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 41 +++-
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 1e3351a4e8..f035bf7dd2 100644
--- a/tcg/sparc64/tcg-target
This can replace four other variables that are references
into the TranslationBlock structure.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 11 +++
accel/tcg/translate-all.c | 2 +-
tcg/tcg-op.c | 14 +++---
tcg/tcg.c | 14 +++
We now have the option to generate direct or indirect
goto_tb depending on the dynamic displacement, thus
the define is no longer necessary or completely accurate.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target.h | 1 -
tcg/i386/tcg-target.h
Install empty versions for !TCG_TARGET_HAS_direct_jump hosts.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 6 ++
tcg/mips/tcg-target.c.inc | 6 ++
tcg/riscv/tcg-target.c.inc | 6 ++
tcg/tci/tcg-target.c.inc | 6 ++
4 files changed, 24 insertions(+)
diff -
Now that tcg can handle direct and indirect goto_tb
simultaneously, we can optimistically leave space for
a direct branch and fall back to loading the pointer
from the TB for an indirect branch.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 52 --
Stop overloading jmp_target_arg for both offset and address,
depending on TCG_TARGET_HAS_direct_jump. Instead, add a new
field to hold the jump insn offset and always set the target
address in jmp_target_addr[]. This will allow a tcg backend
to use either direct or indirect depending on displacem
The INDEX_op_exit_tb opcode needs no register allocation.
Split out a dedicated helper function for it.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4
tcg/aarch64/tcg-target.c.inc | 22 ++
tcg/arm/tcg-target.c.inc | 11 +
tcg/
The old implementation replaces two insns, swapping between
b
nop
br x30
and
adrpx30,
addix30, x30, lo12:
br x30
There is a race condition in which a thread could be stopped at
the PC of the second insn, and when restarted
Test TCG_TARGET_HAS_direct_jump instead of testing an
implementation pointer.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc | 2 +-
tcg/loongarch64/tcg-target.c.inc | 2 +-
tcg/mips/tcg-target.c.inc| 2 +-
tcg/riscv/tcg-tar
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 5c20bedd20..f3a40fc428 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.i
This will shortly be used for more than reset.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 2 +-
accel/tcg/translate-all.c | 8
tcg/tcg.c | 4 ++--
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/
Replace 'tc_ptr' and 'addr' with 'tb' and 'n'.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 3 ++-
tcg/arm/tcg-target.h | 3 ++-
tcg/i386/tcg-target.h| 9 ++---
tcg/loongarch64/tcg-target.h | 3 ++-
tcg/mips/tcg-target.h|
Now that tcg can handle direct and indirect goto_tb simultaneously,
we can optimistically leave space for a direct branch and fall back
to loading the pointer from the TB for an indirect branch.
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 5 +
tcg/riscv/tcg-target.c.in
Similar to the existing set_jmp_reset_offset. Include the
rw->rx address space coversion done by arm and s390x, and
forgotten by mips and riscv.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 9 +
tcg/arm/tcg-target.c.inc | 2 +-
tcg/mips/tcg-target.c.inc | 2 +-
t
Small patch for exit_tb. Large reorg for goto_tb, primarily aimed at
fixing a race condition in which a host thread gets suspended in the
middle of executing a two insn sequence, and the sequence is updated.
The updated second insn does not match the previous first insn, so
when the thread restart
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 37baae9cda..de029d62b4 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -2
Similar to the existing set_jmp_reset_offset. Move any assert for
TCG_TARGET_HAS_direct_jump into the new function (which now cannot
be build-time). Will be unused if TCG_TARGET_HAS_direct_jump is
constant 0, but we can't test for constant in the preprocessor,
so just mark it G_GNUC_UNUSED.
Sign
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 32 +---
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 186599dae0..3f9ee4b39a 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc
The INDEX_op_goto_tb opcode needs no register allocation.
Split out a dedicated helper function for it.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4 ++
tcg/aarch64/tcg-target.c.inc | 40 +-
tcg/arm/tcg-target.c.inc | 49 +++--
On Tue, Dec 6, 2022 at 1:05 AM Eugenio Pérez wrote:
>
> There is currently no data to be migrated, since nothing populates or
> read the fields on virtio-net.
>
> The migration of in-flight descriptors is modelled after the migration
> of requests in virtio-blk. With some differences:
> * virtio-b
On Tue, Dec 6, 2022 at 7:19 AM Peter Xu wrote:
>
> Jason,
>
> On Mon, Dec 05, 2022 at 12:12:04PM +0800, Jason Wang wrote:
> > I'm fine to go without iova-tree. Would you mind to post patches for
> > fix? I can test and include it in this series then.
>
> One sample patch attached, only compile tes
On Mon, 2022-12-05 at 23:17 +0100, Philippe Mathieu-Daudé wrote:
> On 5/12/22 18:31, David Woodhouse wrote:
> > From: Joao Martins
> >
> > This is done by implementing HYPERVISOR_memory_op specifically
> > XENMEM_add_to_physmap with space XENMAPSPACE_shared_info. While
> > Xen removes the page wi
On Mon, 2022-12-05 at 23:25 +0100, Philippe Mathieu-Daudé wrote:
> On 5/12/22 18:31, David Woodhouse wrote:
> > From: Ankur Arora <
> > ankur.a.ar...@oracle.com
> > >
> >
> > GSI-2/IOAPIC pin-2 is treated specially while initing
> > IRQ routing: PIC does not use it at all while the IOAPIC
> > maps
On Mon, 2022-12-05 at 23:13 +0100, Philippe Mathieu-Daudé wrote:
> > +static int kvm_xen_hcall_hvm_op(struct kvm_xen_exit *exit,
> > +int cmd, uint64_t arg)
> > +{
> > +switch (cmd) {
> > +case HVMOP_pagetable_dying: {
> > +exit->u.hcall.result =
On Mon, 2022-12-05 at 23:11 +0100, Philippe Mathieu-Daudé wrote:
> On 5/12/22 18:31, David Woodhouse wrote:
> > From: Joao Martins
> >
> > This means handling the new exit reason for Xen but still
> > crashing on purpose. As we implement each of the hypercalls
> > we will then return the right re
On Mon, 2022-12-05 at 23:06 +0100, Philippe Mathieu-Daudé wrote:
> On 5/12/22 18:31, David Woodhouse wrote:
> > From: Joao Martins
> >
> > This allows -machine xenfv to work with Xen emulated guests.
> >
> > Signed-off-by: Joao Martins
> > Signed-off-by: David Woodhouse
> > ---
> > hw/i386/p
On Mon, 2022-12-05 at 22:58 +0100, Philippe Mathieu-Daudé wrote:
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 22b681ca37..45aa9e40a5 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -7069,6 +7069,8 @@ static Property x86_cpu_properties[] = {
> >
On Mon, Dec 05, 2022 at 12:23:20PM +0800, Jason Wang wrote:
> On Fri, Dec 2, 2022 at 12:25 AM Peter Xu wrote:
> >
> > It seems not super clear on when iova_tree is used, and why. Add a rich
> > comment above iova_tree to track why we needed the iova_tree, and when we
> > need it.
> >
> > Suggeste
Jason,
On Mon, Dec 05, 2022 at 12:12:04PM +0800, Jason Wang wrote:
> I'm fine to go without iova-tree. Would you mind to post patches for
> fix? I can test and include it in this series then.
One sample patch attached, only compile tested.
I can also work on this but I'll be slow in making progr
On Mon, 2022-12-05 at 14:53 +0800, Bin Meng wrote:
> The priv spec v1.12 says:
>
> If no PMP entry matches an M-mode access, the access succeeds. If
> no PMP entry matches an S-mode or U-mode access, but at least one
> PMP entry is implemented, the access fails. Failed accesses
> generate
>
On Fri, Nov 18, 2022 at 8:57 AM Conor Dooley wrote:
>
> From: Conor Dooley
>
> The system controller on PolarFire SoC is access via a mailbox. The
> control registers for this mailbox lie in the "IOSCB" region & the
> interrupt is cleared via write to the "SYSREG" region. It also has a
> QSPI con
On Fri, Dec 02, 2022 at 02:13:45PM +0800,
Chao Peng wrote:
> A large page with mixed private/shared subpages can't be mapped as large
> page since its sub private/shared pages are from different memory
> backends and may also treated by architecture differently. When
> private/shared memory are m
On 5/12/22 18:31, David Woodhouse wrote:
From: Ankur Arora
GSI-2/IOAPIC pin-2 is treated specially while initing
IRQ routing: PIC does not use it at all while the IOAPIC
maps virq=0 to pin-2 and does not use GSI-2.
(all other GSIs are identity mapped to pins.)
This results in any later code wh
On 5/12/22 18:31, David Woodhouse wrote:
From: Joao Martins
This is simply when guest tries to register a vcpu_info
and since vcpu_info placement is optional in the minimum ABI
therefore we can just fail with -ENOSYS
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
target/i38
On 5/12/22 18:31, David Woodhouse wrote:
From: Joao Martins
This is done by implementing HYPERVISOR_memory_op specifically
XENMEM_add_to_physmap with space XENMAPSPACE_shared_info. While
Xen removes the page with its own, we instead use the gfn passed
by the guest.
Signed-off-by: Joao Martins
On 5/12/22 18:31, David Woodhouse wrote:
From: Joao Martins
This is when guest queries for support for HVMOP_pagetable_dying.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
target/i386/xen.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target/i38
On 5/12/22 18:31, David Woodhouse wrote:
From: Joao Martins
This means handling the new exit reason for Xen but still
crashing on purpose. As we implement each of the hypercalls
we will then return the right return code.
Signed-off-by: Joao Martins
[dwmw2: Add CPL to hypercall tracing, disall
On 5/12/22 18:31, David Woodhouse wrote:
From: Joao Martins
This allows -machine xenfv to work with Xen emulated guests.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
hw/i386/pc_piix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc_piix
On Mon, 2022-12-05 at 16:21 +0800, Bin Meng wrote:
> On Fri, Dec 2, 2022 at 8:28 AM Wilfred Mallawa
> wrote:
> >
> > On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> > > The pending register upper limit is currently set to
> > > plic->num_sources >> 3, which is wrong, e.g.: considering
> > >
On 5/12/22 18:31, David Woodhouse wrote:
From: Joao Martins
Such that PCI passthrough devices work for Xen emulated guests.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
hw/i386/xen/xen_platform.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
Hi David,
On 5/12/22 18:31, David Woodhouse wrote:
From: Joao Martins
Introduce support for emulating CPUID for Xen HVM guests via
xen, xen_vapic as changeable params.
Signed-off-by: Joao Martins
[dwmw2: Obtain xen_version from machine property]
Signed-off-by: David Woodhouse
---
target/i
Hi Philippe,
On Sun, Dec 4, 2022 at 10:39 PM Philippe Mathieu-Daudé
wrote:
>
> Hi Strahinja,
>
> On 4/12/22 00:19, Strahinja Jankovic wrote:
> > This patch adds minimal support for AXP-209 PMU.
> > Most important is chip ID since U-Boot SPL expects version 0x1. Besides
> > the chip ID register, r
> From: Eugenio Pérez
> Sent: Monday, December 5, 2022 12:05 PM
>
> There is currently no data to be migrated, since nothing populates or read
> the fields on virtio-net.
>
> The migration of in-flight descriptors is modelled after the migration of
> requests in virtio-blk. With some difference
Hi Simon,
Thanks for your interest in the calendar! I am not a regular QEMU
contributor, but I am a longtime user, and ran the calendar in 2020. I
also put out a submission request for the calendar this past year, but
there wasn't much response. The cost to host the calendar is trivial, we
just ne
On 12/5/22 10:50, Peter Maydell wrote:
@@ -2639,6 +2640,14 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
return ret;
}
+/*
+ * Use the maximum of the S1 & S2 page size, so that invalidation
+ * of pages > TARGET_PAGE_SIZE works correctly.
On Mon, 2022-12-05 at 15:20 +0100, Thomas Huth wrote:
> The PSW key mask is a 16 bit field, and the psw_key variable is
> in the range from 0 to 15, so it does not make sense to use
> "0x80 >> psw_key" for testing the bits here. We should use 0x8000
> instead.
>
> Signed-off-by: Thomas Huth
Revi
From: Joao Martins
This allows -machine xenfv to work with Xen emulated guests.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
hw/i386/pc_piix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 3dcac2f4b6..d112
From: Joao Martins
This is done by implementing HYPERVISOR_memory_op specifically
XENMEM_add_to_physmap with space XENMAPSPACE_shared_info. While
Xen removes the page with its own, we instead use the gfn passed
by the guest.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
accel
From: Joao Martins
Such that PCI passthrough devices work for Xen emulated guests.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
hw/i386/xen/xen_platform.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/hw/i386/xen/xen_platform.c b/hw/
From: David Woodhouse
The original Oracle version of this made it a CPU property, but it isn't
really a per-CPU thing. I then tried making it a KVM accelerator
property but moved to a machine property for two reasons. One is that it
allows us to set it in default_machine_opts for the xenfv platfo
From: Joao Martins
This is when guest queries for support for HVMOP_pagetable_dying.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
target/i386/xen.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target/i386/xen.c b/target/i386/xen.c
index 5d2d8a7e00.
From: Joao Martins
In order to support Linux vdso in Xen.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
target/i386/xen.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/target/i386/xen.c b/target/i386/xen.c
index 59ac
From: Ankur Arora
GSI-2/IOAPIC pin-2 is treated specially while initing
IRQ routing: PIC does not use it at all while the IOAPIC
maps virq=0 to pin-2 and does not use GSI-2.
(all other GSIs are identity mapped to pins.)
This results in any later code which allocates a virq
to be assigned GSI-2.
In 2019, Joao Martins posted a set of Linux KVM patches¹ which added
support for hosting Xen HVM guests directly under KVM. Referenced from
that post was a qemu git tree² which made use of it.
Now that the core of the kernel support has been merged upstream, I'm
looking at updating the qemu suppor
From: Ankur Arora
Handle both HVMOP_set_param(.index = HVM_PARAM_CALLBACK_IRQ) and
HVMOP_set_evtchn_upcall_vector which set the system-wide and per-vCPU
upcall vectors respectively.
The former injects the vector directly to the vCPU, which KVM handles
for us when entering the vCPU with vcpu_info
From: Joao Martins
This is a workaround while we find the most elegant solution
in grant table frames mapping.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
hw/i386/xen/xen_platform.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i386/xen/xen_
From: Joao Martins
Handle the hypercall to set a per vcpu info, as opposed to using
shared_info equivalent. Also, Guests may not call
VCPUOP_register_vcpu_info and will fail in event channel operations if a
proper one isn't set in Qemu.
So derive the hva from shared_info which is where these are
From: Joao Martins
Additionally set XEN_INTERFACE_VERSION to most recent in order to
exercise both event_channel_op and event_channel_op_compat.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
target/i386/xen.c | 46 ++
1 file changed
From: Joao Martins
This is just meant to serve as an example on how we can implement
hypercalls. xen_version specifically since Qemu does all kind of
feature controllability. So handling that here seems appropriate.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
target/i386/xe
From: Joao Martins
This is simply when guest tries to register a vcpu_info
and since vcpu_info placement is optional in the minimum ABI
therefore we can just fail with -ENOSYS
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
target/i386/xen.c | 19 +++
1 file cha
From: Joao Martins
It allows to shutdown itself via hypercall with any of the 3 reasons:
1) self-reboot
2) shutdown
3) crash
Implementing SCHEDOP_shutdown sub op let us handle crashes gracefully rather
than leading to triple faults if it remains unimplemented.
Signed-off-by: Joao Martins
From: Joao Martins
Introduce support for emulating CPUID for Xen HVM guests via
xen, xen_vapic as changeable params.
Signed-off-by: Joao Martins
[dwmw2: Obtain xen_version from machine property]
Signed-off-by: David Woodhouse
---
target/i386/cpu.c | 2 ++
target/i386/cpu.h | 3 ++
t
From: Joao Martins
And use newly added xen_emulated_machine_init() to iniitalize
the xenstore and the sysdev bus for future emulated devices.
Signed-off-by: Joao Martins
[dwmw2: Move it to xen-legacy-backend.c]
Signed-off-by: David Woodhouse
---
hw/i386/pc_piix.c | 5 +
From: Joao Martins
Allow guest to setup the vcpu runstates which is used as
steal clock.
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
target/i386/xen.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/target/i386/xen.c b/target/i386/xen.c
index
From: Joao Martins
Signed-off-by: Joao Martins
Signed-off-by: David Woodhouse
---
hw/xen/xen-legacy-backend.c | 40 +
include/hw/xen/xen-legacy-backend.h | 3 +++
2 files changed, 32 insertions(+), 11 deletions(-)
diff --git a/hw/xen/xen-legacy-backend.c b
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