On Nov 18 08:56, Philippe Mathieu-Daudé wrote:
> On 16/11/22 09:43, Klaus Jensen wrote:
> > From: Klaus Jensen
> >
> > Add the 'nmi-i2c' device that emulates an NVMe Management Interface
> > controller.
> >
> > Initial support is very basic (Read NMI DS, Configuration Get).
> >
> > This is base
On 17/11/22 18:25, Alex Bennée wrote:
It is important that contributors take the review process seriously
and we collaborate in a respectful way while avoiding personal
attacks. Try and make this clear in the language.
Signed-off-by: Alex Bennée
Reviewed-by: Markus Armbruster
Reviewed-by: Stef
On 16/11/22 09:43, Klaus Jensen wrote:
From: Klaus Jensen
Add the 'nmi-i2c' device that emulates an NVMe Management Interface
controller.
Initial support is very basic (Read NMI DS, Configuration Get).
This is based on previously posted code by Padmakar Kalghatgi, Arun
Kumar Agasar and Saurav
On 17/11/22 18:25, Alex Bennée wrote:
The bullet points are quite long and contain process tips. Move those
bits of the bullet to the relevant sections and link to them. Use a
table for nicer formatting of the checklist.
Signed-off-by: Alex Bennée
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Paol
On 17/11/22 18:25, Alex Bennée wrote:
We welcome all sorts of patches.
Signed-off-by: Alex Bennée
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Paolo Bonzini
Message-Id: <2022145529.4020801-7-alex.ben...@linaro.org>
---
docs/devel/submitting-a-patch.rst | 10 +-
1 file changed, 5 i
On 17/11/22 18:25, Alex Bennée wrote:
We don't currently have a clear place in the documentation to describe
the roles and responsibilities of a maintainer. Lets create one so we
can. I've moved a few small bits out of other files to try and keep
everything in one place.
Signed-off-by: Alex Benn
On 18/11/22 08:32, Philippe Mathieu-Daudé wrote:
On 11/11/22 16:47, Emanuele Giuseppe Esposito wrote:
This API allows the accelerators to prevent vcpus from issuing
new ioctls while execting a critical section marked with the
Typo "executing".
accel_ioctl_inhibit_begin/end functions.
Note t
On 11/11/22 16:47, Emanuele Giuseppe Esposito wrote:
This API allows the accelerators to prevent vcpus from issuing
new ioctls while execting a critical section marked with the
accel_ioctl_inhibit_begin/end functions.
Note that all functions submitting ioctls must mark where the
ioctl is being c
Add encode, trans* functions and helper functions support for Zcmt
instrutions
Add support for jvt csr
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.h| 4 ++
target/riscv/cpu_bits.h | 7 +++
target/riscv/csr.c
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn16.decode | 8
target/riscv/insn_trans/trans_rvf.c.inc | 18 ++
2 files changed, 22
On 17/11/22 17:55, Stefan Hajnoczi wrote:
v3:
- Add Patch 1 to avoid clobbering tx descriptor bits
- Add Patch 2 to avoid confusing tx command modes
- Exclude IP and TCP headers from large send MSS value
Stefan Hajnoczi (3):
rtl8139: avoid clobbering tx descriptor bits
rtl8139: keep Tx c
On 17/11/22 17:55, Stefan Hajnoczi wrote:
There are two Tx Descriptor formats called mode 0 and mode 1. The mode
is determined by the Large Send bit.
CP_TX_IPCS (bit 18) is defined in mode 1 but the code checks the bit
unconditionally. In mode 0 bit 18 is part of the Large Send MSS value.
Expli
On 17/11/22 17:55, Stefan Hajnoczi wrote:
The Large-Send Task Offload Tx Descriptor (9.2.1 Transmit) has a
Large-Send MSS value where the driver specifies the MSS. See the
datasheet here:
http://realtek.info/pdf/rtl8139cp.pdf
The code ignores this value and uses a hardcoded MSS of 1500 bytes
ins
This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions.
Specification:
https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v4
To test Zc* implementation, spe
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension
Add check for these properties
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Cc: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 43 +++
target/riscv/cpu.h | 6
Add encode, trans* functions for Zcmp instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn16.decode| 18 +++
target/riscv/insn_trans/trans_rvzce.c.inc | 189 +-
target/riscv/translate.c | 5 +
3 files ch
On 17/11/22 17:55, Stefan Hajnoczi wrote:
The device turns the Tx Descriptor into a Tx Status descriptor after
fully reading the descriptor. This involves clearing Tx Own (bit 31) to
indicate that the driver has ownership of the descriptor again as well
as several other bits.
The code keeps the
Separate c_fld/c_fsd from fld/fsd to add additional check for
c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse
their encodings
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn16.decode | 8
target/riscv/
Add encode and trans* functions support for Zcb instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn16.decode| 24 ++
target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++
target/riscv/tra
Modify the check for C extension to Zca (C implies Zca)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/translate.c| 8 ++--
2 files changed, 8 insertions(+), 4 deletions
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1ab04ab246..b9e41df96c 100644
Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd*
instructions currently
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 287 +-
1 file changed, 286 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/d
在 2022/11/17 19:26, Tobias Fiebig 写道:
Heho,
Ok, that explains a lot. I was also thinking that the vlan bit seem to overlap
with the MTU field, and wanted to look at that later today.
Re the 12b: IIRC, the standard 1500 MTU for ethernet is already without the
ethernet header; That can have up
On 18/11/22 02:37, Vivek Kasireddy wrote:
While filling out the display info such as width, height to
be provided to the Guest, make sure that the position information
(x, y) is also included. This position info corresponds with the
x and y fields mentioned in the spec:
https://github.com/oasis-t
Hi Klaus,
> I had to reverse the target mode functionality in QEMU from the linux
> driver, so I am really not too sure if having START and STOP set in
> the interrupt register is allowed behavior or not
>From my interpretation of things, there's nothing explicitly preventing
both a pending start
On 17/11/22 18:00, Conor Dooley wrote:
On Sat, Nov 12, 2022 at 01:34:15PM +, Conor Dooley wrote:
From: Conor Dooley
The system controller on PolarFire SoC is access via a mailbox. The
control registers for this mailbox lie in the "IOSCB" region & the
interrupt is cleared via write to the "
On Nov 18 14:15, Jeremy Kerr wrote:
> Hi Klaus,
>
> > With those changes, I can get control protocol going, and multi-
> > packet messages work.
>
> Ah, I also needed a change to the aspeed I2C driver, as I'm seeing
> the interrupt handler being invoked with both a stop and a start event
> pendin
On Nov 18 13:56, Jeremy Kerr wrote:
> Hi Klaus,
>
> > Add an abstract MCTP over I2C endpoint model. This implements MCTP
> > control message handling as well as handling the actual I2C transport
> > (packetization).
> >
> > Devices are intended to derive from this and implement the class
> > meth
On Nov 17 14:40, Cédric Le Goater wrote:
> On 11/17/22 12:58, Klaus Jensen wrote:
> > On Nov 17 09:01, Cédric Le Goater wrote:
> > > On 11/17/22 08:37, Klaus Jensen wrote:
> > > > On Nov 17 07:56, Cédric Le Goater wrote:
> > > > > On 11/17/22 07:40, Klaus Jensen wrote:
> > > > > > On Nov 16 16:58,
Hi Klaus,
> With those changes, I can get control protocol going, and multi-
> packet messages work.
Ah, I also needed a change to the aspeed I2C driver, as I'm seeing
the interrupt handler being invoked with both a stop and a start event
pending.
Patch below; if this seems sensible I will propo
Hi Klaus,
> Add an abstract MCTP over I2C endpoint model. This implements MCTP
> control message handling as well as handling the actual I2C transport
> (packetization).
>
> Devices are intended to derive from this and implement the class
> methods.
Looks good, nice to see how it's used by the n
On 11/15/22 20:03, Xiaojuan Yang wrote:
Fix setprop_sized method in fdt rtc node.
Signed-off-by: Xiaojuan Yang
---
hw/loongarch/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On Wed, Nov 16, 2022 at 8:54 AM Ani Sinha wrote:
>
> On Wed, Nov 16, 2022 at 2:58 AM John Snow wrote:
> >
> > Instead of using a hardcoded timeout, just rely on Avocado's built-in
> > test case timeout. This helps avoid timeout issues on machines where 60
> > seconds is not sufficient.
> >
> > Si
On 2022/11/18 10:51, Richard Henderson wrote:
I don't think any processor will support overlapping, mutual exclusive
extensions. The decode within the processor would be wildly
complicated by that.
While you might be able to get away with returning false in this
particular case right now,
On 11/17/22 17:46, weiwei wrote:
However, to some extent, JVT and FCSR in statenen CSR are used to
enable/disable
Zfinx and Zcmt extensions. When they are disabled, It seems reasonable to look
for
another insn, just like the processor doesn't support them at all.
From the other aspect, is it
QE tries to test the parameter "event_idx=on". In both environments
"virtio-vdpa + vp_vdpa" and "vhost_vdpa + vp_vdpa", there is no
network connectivity issue after the guest boot up.
Tested-by: Lei Yang
> From: Jason Wang
> Date: Tue, Nov 1, 2022 at 10:42 AM
> Subject: Re: [PATCH 0/4] Endiane
在 2022/11/15 下午8:10, Philippe Mathieu-Daudé 写道:
On 15/11/22 12:56, Xiaojuan Yang wrote:
Add cfi01 pflash device for LoongArch virt machine
So the subject prefix should be "hw/loongarch/virt:".
Signed-off-by: Xiaojuan Yang
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/acpi-build.
Pull the code that creates a new window associated with a notebook
tab into a separate function. This new function can be useful not
just when user wants to detach a tab but also in the future when
a new window creation is needed in other scenarios.
Cc: Gerd Hoffmann
Cc: Dongwon Kim
Signed-off-b
There is a need (expressed by several customers/users) to assign
ownership of one or more physical monitors/connectors to individual
Guests such that there is a clear notion of which Guest's contents
are being displayed on any given monitor. Given that there is always
a Display Server/Compositor ru
Just like it is done in gtk-egl.c, we need to ensure that the scaling
factors are correctly calculated in draw callback. Otherwise, they
would just be set to 1.0. And, use gtk_widget_get_allocated_width/height
variants to determine width and height in the Wayland case similar to
how it is done in d
gdk_device_warp() is a no-op when running in a Host environment that is
Wayland based as the Wayland protocol does not allow clients to move
the cursor to a specific location. This presents a problem when Qemu is
running with GTK UI + relative mouse mode, as we would no longer be able
to warp the c
When a detached tab window is closed, the underlying (EGL) context
is destroyed; therefore, disable the scanout which also destroys the
underlying framebuffer (id) and other objects. Also add calls to
make the context current in disable scanout and other missing places.
Cc: Gerd Hoffmann
Cc: Dong
The new parameter named "connector" can be used to assign physical
monitors/connectors to individual GFX VCs such that when the monitor
is connected or hotplugged, the associated GTK window would be
moved to it. If the monitor is disconnected or unplugged, the
associated GTK window would be destroy
Since gdk_window_get_root_coords() expects a position within the window,
we need to translate Guest's cooridinates to window local coordinates
by multiplying them with the scaling factor.
Cc: Gerd Hoffmann
Cc: Dongwon Kim
Signed-off-by: Vivek Kasireddy
---
ui/gtk.c | 3 ++-
1 file changed, 2 i
Currently, the range of the absolute pointer device (usb-tablet) is
restricted to any one monitor. This presents a problem when there are
multiple VCs (Guest GTK windows) located on different monitors.
Therefore, it makes sense to extend the range of the absolute pointer
device to span all monitors
While filling out the display info such as width, height to
be provided to the Guest, make sure that the position information
(x, y) is also included. This position info corresponds with the
x and y fields mentioned in the spec:
https://github.com/oasis-tcs/virtio-spec/blob/master/virtio-gpu.tex#L3
While filling out the display info such as width, height to
be provided to the Guest, make sure that the position information
(x, y) is also included. This position info corresponds with the
x and y fields mentioned in the spec:
https://github.com/oasis-tcs/virtio-spec/blob/master/virtio-gpu.tex#L3
In situtations where the Guest uses multiple displays/outputs, this
position info is useful for aligning the Guest's outputs with that of
the Host's.
Cc: Dongwon Kim
Cc: Gerd Hoffmann
Signed-off-by: Vivek Kasireddy
---
ui/gtk.c | 20
1 file changed, 20 insertions(+)
diff
On 2022/11/18 04:57, Richard Henderson wrote:
On 11/17/22 03:44, weiwei wrote:
Missing a smstateen_check. Not mentioned in the instruction
description itself, but it is within the State Enable section of JVT.
smstateen_check have been added in REQUIRE_ZCMT.
Oh. I see. That's wrong, I th
Sam Li 于2022年11月18日周五 08:33写道：
>
> Stefan Hajnoczi 于2022年11月18日周五 03:12写道：
> >
> > Hi Sam,
> > Please send a git repo URL so Thomas can fetch the commit without
> > email/file size limitations.
>
> I'll push it to the zbd branch after fixing the bellowing.
> https://github.com/sgzerolc/qemu-web/z
On Thu, Nov 17, 2022 at 03:08:17PM +, Alex Bennée wrote:
>
> Chao Peng writes:
>
> > On Wed, Nov 16, 2022 at 07:03:49PM +, Alex Bennée wrote:
> >>
> >> Chao Peng writes:
> >>
> >> > On Tue, Nov 15, 2022 at 04:56:12PM +, Alex Bennée wrote:
> >> >>
> >> >> Chao Peng writes:
> >> >
On 11/17/22 08:11, Pavel Dovgalyuk wrote:
AVR ELPMX instruction (and some others) use three registers to
form long 24-bit address from RAMPZ and two 8-bit registers.
RAMPZ stores shifted 8 bits like ff to simplify address calculation.
This patch fixes full address calculation in function gen_
Stefan Hajnoczi 于2022年11月18日周五 03:12写道：
>
> Hi Sam,
> Please send a git repo URL so Thomas can fetch the commit without
> email/file size limitations.
I'll push it to the zbd branch after fixing the bellowing.
https://github.com/sgzerolc/qemu-web/zbd
>
> > diff --git a/_posts/2022-11-17-zoned-em
On Thu, Nov 17, 2022 at 06:06:33PM +0100, Greg Kurz wrote:
> On Thu, 17 Nov 2022 12:32:18 -0300
> Daniel Henrique Barboza wrote:
>
> > The maintainer is no longer being paid to maintain these components. All
> > maintainership work is being done in his personal time since the middle
> > of the 7.
On Wed, Nov 16, 2022 at 11:29 PM Alexandre Ghiti wrote:
>
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in turn mu
From: Conor Dooley
The system controller on PolarFire SoC is access via a mailbox. The
control registers for this mailbox lie in the "IOSCB" region & the
interrupt is cleared via write to the "SYSREG" region. It also has a
QSPI controller, usually connected to a flash chip, that is used for
stori
From: Conor Dooley
The Fabric Interconnect Controllers provide interfaces between the FPGA
fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered
0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and
does not show up on the MSS memory map. FIC4 is dedicated to th
From: Conor Dooley
Hey all,
Apart from DDR (see [1]), these should be the last bits needed to get
recent Linux kernels booting again for Icicle/PolarFire SoC. Previously,
I had been disabling the hwrng and PCI but I keep forgetting that is
required and decided to fix that.
I'm not entirely sure
From: Conor Dooley
On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by
"Clock Conditioning Circuitry" in the FPGA. The specific clock depends
on the FPGA bitstream & can be locked to one particular {D,P}LL - in the
Icicle Kit Reference Design v2022.09 or later this is/will be
On Thu, Nov 17, 2022, 15:42 Tobias Fiebig wrote:
> Heho,
> I gave v3 a shot and it performs as expected; For a requested MSS of 1320,
> TSO consistently uses a 1308 MSS. So for me, this patch works. Thanks for
> fixing this. :-)
>
> Sadly, I do not have boxes to test with .1q around; If none of y
From: Igor Mammedov
PCI-ISA bridges that are built in PIIX/Q35 are building its own AML
using AcpiDevAmlIf interface. Now build_append_pci_bus_devices()
gained AcpiDevAmlIf interface support to get AML of devices atached
to PCI slots.
So drop ad-hoc build_q35_isa_bridge()/build_piix4_isa_bridge()
On 11/17/22 03:44, weiwei wrote:
Missing a smstateen_check. Not mentioned in the instruction description itself, but it
is within the State Enable section of JVT.
smstateen_check have been added in REQUIRE_ZCMT.
Oh. I see. That's wrong, I think.
Returning false from trans_* means "no matc
Heho,
I gave v3 a shot and it performs as expected; For a requested MSS of 1320, TSO
consistently uses a 1308 MSS. So for me, this patch works. Thanks for fixing
this. :-)
Sadly, I do not have boxes to test with .1q around; If none of you has either,
and that should be tested as well, I can giv
On 11/9/22 00:16, John Snow wrote:
On Thu, Nov 3, 2022 at 6:29 AM Maksim Davydov
wrote:
This script run QEMU to obtain compat_props of machines and default
values of different types and produce appropriate table. This table
can be used to compare machine types to choose the most suitable
mach
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
second release candidate for the QEMU 7.2 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-7.2.0-rc1.tar.xz
http://downl
On 11.11.22 16:47, Emanuele Giuseppe Esposito wrote:
Using the new accel-blocker API, mark where ioctls are being called
in KVM. Next, we will implement the critical section that will take
care of performing memslots modifications atomically, therefore
preventing any new ioctl from running and al
Hi Sam,
Please send a git repo URL so Thomas can fetch the commit without
email/file size limitations.
> diff --git a/_posts/2022-11-17-zoned-emulation.md
> b/_posts/2022-11-17-zoned-emulation.md
> new file mode 100644
> index 000..69ce4d7
> --- /dev/null
> +++ b/_posts/2022-11-17-zoned-emula
On Thu, 17 Nov 2022 19:11:47 +0200
Avihai Horon wrote:
> On 16/11/2022 20:36, Alex Williamson wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Thu, 3 Nov 2022 18:16:17 +0200
> > Avihai Horon wrote:
> >
> >> If vfio_migration_set_state() fails to set the device
On Thu, 17 Nov 2022 at 12:53, Russell King (Oracle)
wrote:
> Your subject says "for-7.2" - that's a while off yet! I guess you need
> to update it to "for-6.2" for the next posting of this series.
Sorry if this looked like a Linux patch series. This is a QEMU series
and the next release is 7.2.
Well...
On Thu, 2022-11-17 at 16:27 +0100, Dario Faggioli wrote:
> Keep the old limit of 288 for machine versions 7.2 and earlier.
>
...At least, this was the idea...
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -386,6 +386,7 @@ static void
> pc_q35_7_1_machine_options(MachineClass *m)
Hi Stefan,
Your subject says "for-7.2" - that's a while off yet! I guess you need
to update it to "for-6.2" for the next posting of this series.
Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
On Thu, 17 Nov 2022 19:07:10 +0200
Avihai Horon wrote:
> On 16/11/2022 20:29, Alex Williamson wrote:
> > On Thu, 3 Nov 2022 18:16:15 +0200
> > Avihai Horon wrote:
> >> diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c
> >> index e784374453..62afc23a8c 100644
> >> --- a/hw/vfio/migration.c
>
On Wed, Nov 16, 2022 at 10:34 PM Marek Marczykowski-Górecki
wrote:
>
> On Wed, Nov 16, 2022 at 10:40:02PM +0100, Marek Marczykowski-Górecki wrote:
> > On Wed, Nov 16, 2022 at 02:15:22PM -0500, Jason Andryuk wrote:
> > > On Mon, Nov 14, 2022 at 2:21 PM Marek Marczykowski-Górecki
> > > wrote:
> > >
Hi,
This contains my last set of fixes which didn't make it in the last
pull request I sent. I've dropped the console peek patch which
unearthed a number of additional tests which can't handle even the
smallest delay in avocado draining the console chardev. As a result we
still occasionally miss l
It is important that contributors take the review process seriously
and we collaborate in a respectful way while avoiding personal
attacks. Try and make this clear in the language.
Signed-off-by: Alex Bennée
Reviewed-by: Markus Armbruster
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Paolo Bonzini
On Thu, Nov 17, 2022 at 07:07:10PM +0200, Avihai Horon wrote:
> > > +}
> > > +
> > > +if (mig_state->data_fd != -1) {
> > > +if (migration->data_fd != -1) {
> > > +/*
> > > + * This can happen if the device is asynchronously reset and
> > > + * te
The boot_linux tests download and run a full cloud image boot and
start a full distro. While the ability to test the full boot chain is
worthwhile it is perhaps a little too heavy weight and causes issues
in CI. Fix this by introducing a new alpine linux ISO boot in
machine_aarch64_virt.
This boot
We don't currently have a clear place in the documentation to describe
the roles and responsibilities of a maintainer. Lets create one so we
can. I've moved a few small bits out of other files to try and keep
everything in one place.
Signed-off-by: Alex Bennée
Reviewed-by: Stefan Hajnoczi
Review
From: Stefan Weil
The docker probe uses "sudo -n" which can cause an e-mail with a security
warning
each time when configure is run. Therefore run docker probe only if either
docker
or podman are available.
That avoids the problematic "sudo -n" on build environments which have neither
docker n
From: Peter Maydell
The two tests
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv2
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv3
take quite a long time to run, and the current timeout of 240s
is not enough for the tests to complete on slow machines:
we've seen
The bullet points are quite long and contain process tips. Move those
bits of the bullet to the relevant sections and link to them. Use a
table for nicer formatting of the checklist.
Signed-off-by: Alex Bennée
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Paolo Bonzini
Message-Id: <2022145529.4
From: Daniel P. Berrangé
The Cirrus CI service has announced the intent to discontinue
support for x86_64 macOS CI runners. They already have aarch64
runners available and require all projects to switch to these
images before Jan 1st 2023. The different architecture is
merely determined by the im
This should hopefully give is nice coverage information about what our
tests (or at least the subset we are running) have hit. Ideally we
would want a way to trigger coverage on tests likely to be affected by
the current commit.
Signed-off-by: Alex Bennée
Acked-by: Stefan Hajnoczi
Message-Id: <2
We welcome all sorts of patches.
Signed-off-by: Alex Bennée
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Paolo Bonzini
Message-Id: <2022145529.4020801-7-alex.ben...@linaro.org>
---
docs/devel/submitting-a-patch.rst | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a
We now have a much lighter weight test in machine_aarch64_virt which
tests the full boot chain in less time. Rename the tests while we are
at it to make it clear it is a Fedora cloud image.
Signed-off-by: Alex Bennée
---
tests/avocado/boot_linux.py | 9 +++--
1 file changed, 7 insertions(+),
From: Cédric Le Goater
The Aspeed SDK images are based on OpenBMC which starts a lot of
services. The output noise on the console can break from time to time
the test waiting for the logging prompt.
Change the U-Boot bootargs variable to add "quiet" to the kernel
command line and reduce the outp
From: Peter Maydell
On my machine, a debug build of QEMU takes about 260 seconds to
complete this test, so with the current timeout value of 180 seconds
it always times out. Double the timeout value to 360 so the test
definitely has enough time to complete.
Signed-off-by: Peter Maydell
Signed-
This is useful when trying to bisect a particular failing test behind
a docker run. For example:
make docker-test-clang@fedora \
TARGET_LIST=arm-softmmu \
TEST_COMMAND="meson test qtest-arm/qos-test" \
J=9 V=1
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-
Thomas Huth writes:
> On 16/11/2022 18.50, Daniel P. Berrangé wrote:
>> The Cirrus CI service has announced the intent to discontinue
>> support for x86_64 macOS CI runners. They already have aarch64
>> runners available and require all projects to switch to these
>> images before Jan 1st 2023.
On 11/17/22 15:04, Alex Bennée wrote:
Cédric Le Goater writes:
Hello Alex,
On 11/11/22 15:55, Alex Bennée wrote:
This attempts to deal with the problem of login prompts not being
guaranteed to be terminated with a newline. The solution to this is to
peek at the incoming data looking to see
On 16/11/2022 20:36, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Thu, 3 Nov 2022 18:16:17 +0200
Avihai Horon wrote:
If vfio_migration_set_state() fails to set the device in the requested
state it tries to put it in a recover state. If setting the devi
On 16/11/2022 20:29, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Thu, 3 Nov 2022 18:16:15 +0200
Avihai Horon wrote:
Add implementation of VFIO migration protocol v2. The two protocols, v1
and v2, will co-exist and in next patch v1 protocol will be rem
On Thu, 17 Nov 2022 12:32:18 -0300
Daniel Henrique Barboza wrote:
> The maintainer is no longer being paid to maintain these components. All
> maintainership work is being done in his personal time since the middle
> of the 7.2 development cycle.
>
Great thanks Daniel for all your contributions
On Sat, Nov 12, 2022 at 01:34:15PM +, Conor Dooley wrote:
> From: Conor Dooley
>
> The system controller on PolarFire SoC is access via a mailbox. The
> control registers for this mailbox lie in the "IOSCB" region & the
> interrupt is cleared via write to the "SYSREG" region. It also has a
>
Heho,
Thanks, will test the three patches later.
With best regards,
Tobias
-Original Message-
From: Stefan Hajnoczi
Sent: Thursday, 17 November 2022 17:57
To: Tobias Fiebig
Cc: Jason Wang ; Stefan Hajnoczi ;
qemu-devel@nongnu.org; qemu-sta...@nongnu.org; Russell King - ARM Linux
Sub
Peter Maydell writes:
> The two tests
> tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv2
> tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv3
>
> take quite a long time to run, and the current timeout of 240s
> is not enough for the tests to complete on slow machin
The Large-Send Task Offload Tx Descriptor (9.2.1 Transmit) has a
Large-Send MSS value where the driver specifies the MSS. See the
datasheet here:
http://realtek.info/pdf/rtl8139cp.pdf
The code ignores this value and uses a hardcoded MSS of 1500 bytes
instead. When the MTU is less than 1500 bytes t
Hi Tobias,
My initial patch was broken. I did some cleanup and sent a v3.
Stefan
The device turns the Tx Descriptor into a Tx Status descriptor after
fully reading the descriptor. This involves clearing Tx Own (bit 31) to
indicate that the driver has ownership of the descriptor again as well
as several other bits.
The code keeps the first dword of the Tx Descriptor in the txdw
v3:
- Add Patch 1 to avoid clobbering tx descriptor bits
- Add Patch 2 to avoid confusing tx command modes
- Exclude IP and TCP headers from large send MSS value
The rtl8139 large send offload currently does not honor the MSS value provided
by the driver. This is a problem especially when the MTU
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