Debugging bits issue often involves running the QEMU command line manually
outside of the avocado environment with the generated ISO. Hence, its
inconvenient if the iso gets cleaned up after the test has finished. This change
makes sure that the work directory is kept after the test finishes if the
On Thu, Nov 17, 2022 at 7:52 AM Jason Wang wrote:
>
>
> 在 2022/11/16 23:05, Eugenio Pérez 写道:
> > Isolate control virtqueue in its own group, allowing to intercept control
> > commands but letting dataplane run totally passthrough to the guest.
> >
> > Signed-off-by: Eugenio Pérez
> > ---
> > v7:
On Thu, Nov 17, 2022 at 5:24 AM Ani Sinha wrote:
>
>
>
> On Wed, Nov 16, 2022 at 11:31 PM John Snow wrote:
>>
>>
>>
>> On Tue, Nov 15, 2022, 10:24 PM Ani Sinha wrote:
>>>
>>> On Wed, Nov 16, 2022 at 2:58 AM John Snow wrote:
>>> >
>>> > Instead of using a hardcoded timeout, just rely on Avocado'
On Nov 17 07:56, Cédric Le Goater wrote:
> On 11/17/22 07:40, Klaus Jensen wrote:
> > On Nov 16 16:58, Cédric Le Goater wrote:
> > > On 11/16/22 09:43, Klaus Jensen wrote:
> > > > From: Klaus Jensen
> > > >
> > > > It is not given that the current master will release the bus after a
> > > > trans
On Nov 16 18:14, Joel Granados wrote:
> In order to evaluate write amplification factor (WAF) within the storage
> stack it is important to know the number of bytes written to the
> controller. The existing SMART log value of Data Units Written is too
> coarse (given in units of 500 Kb) and so we a
Separate c_fld/c_fsd from fld/fsd to add additional check for
c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse
their encodings
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn16.decode | 8
target/riscv/
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1ab04ab246..b9e41df96c 100644
This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version
instructions.
Specification:
https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v3
To test Zc* implementation, s
Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd*
instructions currently
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 287 +-
1 file changed, 286 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/d
Add encode, trans* functions and helper functions support for Zcmt
instrutions
Add support for jvt csr
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.h| 2 +
target/riscv/cpu_bits.h | 7 +++
target/riscv/csr.c
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension
Add check for these properties
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Cc: Alistair Francis
---
target/riscv/cpu.c | 43 +++
target/riscv/cpu.h | 6 ++
2 files changed, 49 insertio
Modify the check for C extension to Zca (C implies Zca)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/translate.c| 8 ++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/riscv/i
Add encode, trans* functions for Zcmp instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn16.decode| 18 ++
target/riscv/insn_trans/trans_rvzce.c.inc | 242 +-
target/riscv/translate.c | 5 +
3 files cha
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn16.decode | 8
target/riscv/insn_trans/trans_rvf.c.inc | 18 ++
2 files changed, 22 insertions(+), 4 deletions(-)
d
Add encode and trans* functions support for Zcb instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn16.decode| 24 ++
target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++
target/riscv/translate.c | 2
On 11/17/22 07:40, Klaus Jensen wrote:
On Nov 16 16:58, Cédric Le Goater wrote:
On 11/16/22 09:43, Klaus Jensen wrote:
From: Klaus Jensen
It is not given that the current master will release the bus after a
transfer ends. Only schedule a pending master if the bus is idle.
Fixes: 37fa5ca42623
在 2022/11/16 23:05, Eugenio Pérez 写道:
Isolate control virtqueue in its own group, allowing to intercept control
commands but letting dataplane run totally passthrough to the guest.
Signed-off-by: Eugenio Pérez
---
v7:
* Never ask for number of address spaces, just react if isolation is not
On Nov 16 08:27, Corey Minyard wrote:
> On Wed, Nov 16, 2022 at 09:43:11AM +0100, Klaus Jensen wrote:
> > From: Klaus Jensen
> >
> > Add an abstract MCTP over I2C endpoint model. This implements MCTP
> > control message handling as well as handling the actual I2C transport
> > (packetization).
>
On 11/17/22 03:13, Vaibhav Jain wrote:
Greg Kurz writes:
Hi Vaibhav,
Hey Greg,
Good to see you,
Nice to see some people are still building QEMU at IBM ;-)
Yeah, and will hopefully continue to do this in future :-)
Reported-by: Kowshik Jois B S
Signed-off-by: Vaibhav Jain
---
Revie
On Nov 16 16:58, Cédric Le Goater wrote:
> On 11/16/22 09:43, Klaus Jensen wrote:
> > From: Klaus Jensen
> >
> > It is not given that the current master will release the bus after a
> > transfer ends. Only schedule a pending master if the bus is idle.
> >
> > Fixes: 37fa5ca42623 ("hw/i2c: suppor
On Nov 16 17:19, Joel Granados wrote:
> On Tue, Nov 15, 2022 at 12:26:17PM +0100, Klaus Jensen wrote:
> > On Nov 14 14:50, Joel Granados wrote:
> > >
> > > +static uint16_t nvme_vendor_specific_log(uint8_t lid, NvmeCtrl *n,
> > > uint8_t rae,
> > > + uint3
在 2022/11/16 23:05, Eugenio Pérez 写道:
The memory listener that thells the device how to convert GPA to qemu's
va is registered against CVQ vhost_vdpa. memory listener translations
are always ASID 0, CVQ ones are ASID 1 if supported.
Let's tell the listener if it needs to register them on iova
在 2022/11/16 23:05, Eugenio Pérez 写道:
CVQ can be shadowed two ways:
- Device has x-svq=on parameter (current way)
- The device can isolate CVQ in its own vq group
QEMU needs to check for the second condition dynamically, because CVQ
index is not known at initialization time. Since this is dyna
On Wed, Nov 16, 2022 at 11:06 PM Eugenio Pérez wrote:
>
> So the caller can choose which ASID is destined.
>
> No need to update the batch functions as they will always be called from
> memory listener updates at the moment. Memory listener updates will
> always update ASID 0, as it's the passthro
On Wed, Nov 16, 2022 at 11:06 PM Eugenio Pérez wrote:
>
> SVQ may run or not in a device depending on runtime conditions (for
> example, if the device can move CVQ to its own group or not).
>
> Allocate the SVQ array unconditionally at startup, since its hard to
> move this allocation elsewhere.
>
On Wed, Nov 16, 2022 at 11:06 PM Eugenio Pérez wrote:
>
> The next patches will start control SVQ if possible. However, we don't
> know if that will be possible at qemu boot anymore.
>
> Since the moved checks will be already evaluated at net/ to know if it
> is ok to shadow CVQ, move them.
>
> Si
On Wed, Nov 16, 2022 at 11:06 PM Eugenio Pérez wrote:
>
> This function used to trust in v->shadow_vqs != NULL to know if it must
> start svq or not.
>
> This is not going to be valid anymore, as qemu is going to allocate svq
> unconditionally (but it will only start them conditionally).
>
> Signe
Most of the changes are trivial. The bits test timeout has now been increased
to 200 seconds in order to accommodate slower systems and fewer unnecessary
failures. Removed of the reference to non-existent README file in docs. Some
minor corrections in the doc file.
CC: Thomas Huth
CC: Michael S.
On Wed, Nov 16, 2022 at 10:40:02PM +0100, Marek Marczykowski-Górecki wrote:
> On Wed, Nov 16, 2022 at 02:15:22PM -0500, Jason Andryuk wrote:
> > On Mon, Nov 14, 2022 at 2:21 PM Marek Marczykowski-Górecki
> > wrote:
> > >
> > > The /dev/mem is used for two purposes:
> > > - reading PCI_MSIX_ENTRY_
On 11/16/22 09:03, Ard Biesheuvel wrote:
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 3745ac9723474332..9a6277d862fac229 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1222,6 +1222,14 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
ps = MIN(ps,
Heho,
Ok, I just learned more C than I ever wanted to. There is a bit more amiss here
(ll from 7d7238c72b983cff5064734349d2d45be9c6282c):
In line 1916 of rtl8139.c we set txdw0; If we calculate the MSS at this point,
it is consistently 12 below requested, but generally accurate. The bits that
f
I think you missed the Based-on tag.
r~
On Wed, 16 Nov 2022, 05:38 Daniel Henrique Barboza,
wrote:
> Richard,
>
> I believe the ppc64-linux-user target didn't like what you did in this
> patch. Here's the error:
>
> $ ../configure
> --target-list=ppc64-softmmu,ppc64-linux-user,ppc-softmmu,ppc-l
Hi Philippe,
Philippe Mathieu-Daudé writes:
>
> Oops sorry.
>
> Fixes: 61bd1d2942 ("target/ppc: Convert to tcg_ops restore_state_to_opc")
Thanks for figuring and pointing this out
>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index a05a2ed595..94adcb766b 100644
>> --
Greg Kurz writes:
> Hi Vaibhav,
>
Hey Greg,
Good to see you,
> Nice to see some people are still building QEMU at IBM ;-)
Yeah, and will hopefully continue to do this in future :-)
>> Reported-by: Kowshik Jois B S
>> Signed-off-by: Vaibhav Jain
>> ---
>
> Reviewed-by: Greg Kurz
>
Thanks
>
On Wed, Nov 16, 2022 at 11:31 PM John Snow wrote:
>
>
> On Tue, Nov 15, 2022, 10:24 PM Ani Sinha wrote:
>
>> On Wed, Nov 16, 2022 at 2:58 AM John Snow wrote:
>> >
>> > Instead of using a hardcoded timeout, just rely on Avocado's built-in
>> > test case timeout. This helps avoid timeout issues o
On Tue, Oct 25, 2022, Chao Peng wrote:
> +static int kvm_vm_ioctl_set_mem_attr(struct kvm *kvm, gpa_t gpa, gpa_t size,
> + bool is_private)
> +{
> + gfn_t start, end;
> + unsigned long i;
> + void *entry;
> + int idx;
> + int r = 0;
> +
> + i
On Wed, Nov 16, 2022, Ackerley Tng wrote:
> >@@ -4173,6 +4203,22 @@ static int kvm_faultin_pfn(struct kvm_vcpu *vcpu,
> >struct kvm_page_fault *fault)
> > return RET_PF_EMULATE;
> > }
> >
> >+if (kvm_slot_can_be_private(slot) &&
> >+fault->is_private != kvm_mem_
Pressing attention button has special meaning when power indicator is
blinking. Better just not do it.
For example, trying to remove device immediately after hotplug leads to
both commands succeded but device not actually unrealized.
Same thing for PCIE hotplug was done in
81124b3c7a5dae "pcie:
On Wed, Nov 16, 2022 at 02:15:22PM -0500, Jason Andryuk wrote:
> On Mon, Nov 14, 2022 at 2:21 PM Marek Marczykowski-Górecki
> wrote:
> >
> > The /dev/mem is used for two purposes:
> > - reading PCI_MSIX_ENTRY_CTRL_MASKBIT
> > - reading Pending Bit Array (PBA)
> >
> > The first one was originally
> A memslot with KVM_MEM_PRIVATE being set can include both fd-based
> private memory and hva-based shared memory. Architecture code (like TDX
> code) can tell whether the on-going fault is private or not. This patch
> adds a 'is_private' field to kvm_page_fault to indicate this and
> architecture
On 11/16/22 19:26, Michael S. Tsirkin wrote:
On Wed, Nov 16, 2022 at 07:12:34PM +0300, Vladimir Sementsov-Ogievskiy wrote:
Hi all! That's an RFC patch.
The problem is that SHPC protocol says that power-led is blinking for 5
seconds before actual turning-on the device. If we call device-del
duri
On Wed, 16 Nov 2022, Igor Mammedov wrote:
Code has not been used practically since its inception (2004)
f2aa58c6f4a20 UniNorth PCI bridge support
or maybe even earlier, but it was consuming contributors time
as QEMU was being rewritten.
Drop it for now. Whomever would like to actually
use th
On 16/11/2022 18:20, Alex Bennée wrote:
Stefan Hajnoczi writes:
This pull request causes the following CI failure:
https://gitlab.com/qemu-project/qemu/-/jobs/3328449477
I haven't figured out the root cause of the failure. Maybe the pull
request just exposes a latent failure. Please take a
On Mon, Nov 14, 2022 at 2:21 PM Marek Marczykowski-Górecki
wrote:
>
> The /dev/mem is used for two purposes:
> - reading PCI_MSIX_ENTRY_CTRL_MASKBIT
> - reading Pending Bit Array (PBA)
>
> The first one was originally done because when Xen did not send all
> vector ctrl writes to the device mode
Chao Peng writes:
> On Tue, Nov 15, 2022 at 04:56:12PM +, Alex Bennée wrote:
>>
>> Chao Peng writes:
>>
>> > This new KVM exit allows userspace to handle memory-related errors. It
>> > indicates an error happens in KVM at guest memory range [gpa, gpa+size).
>> > The flags includes additi
Both VIA south bridges allow system software to configure the routing of
PCI interrupts to ISA interrupts. Implement this to model the real
hardware more closely.
The implementation is based on hw/isa/piix4.c.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 46 ++
pci_map_irq_fn's in general seem to be board-specific, and PIIX4's
pci_slot_get_pirq() in particular seems very Malta-specific. So move the
latter to malta.c to 1/ keep the board logic in one place and 2/ avoid
PIIX4 to make assumptions about its board.
Signed-off-by: Bernhard Beschow
---
hw/isa
pci_map_irq_fn's in general seem to be board-specific. So move PIIX3's
pci_slot_get_pirq() to board code to not have PIIX3 make assuptions
about its board.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_piix.c | 17 +
hw/isa/piix3.c| 16 +++-
2 files changed, 20 i
During my PIIX consolidation work [1] I've noticed that both PIIX models have
quite different pci_slot_get_pirq() implementations. These functions seem to
map PCI INTx pins to input pins of a programmable interrupt router which is
AFAIU board-specific. IOW, board-specific assumptions are baked into
On Wed, Nov 16, 2022, Andy Lutomirski wrote:
>
>
> On Tue, Oct 25, 2022, at 8:13 AM, Chao Peng wrote:
> > diff --git a/Documentation/virt/kvm/api.rst
> > b/Documentation/virt/kvm/api.rst
> > index f3fa75649a78..975688912b8c 100644
> > --- a/Documentation/virt/kvm/api.rst
> > +++ b/Documentation/
On Thu, 3 Nov 2022 18:16:17 +0200
Avihai Horon wrote:
> If vfio_migration_set_state() fails to set the device in the requested
> state it tries to put it in a recover state. If setting the device in
> the recover state fails as well, hw_error is triggered and the VM is
> aborted.
>
> To improve
Stefan Hajnoczi writes:
> This pull request causes the following CI failure:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/3328449477
>
> I haven't figured out the root cause of the failure. Maybe the pull
> request just exposes a latent failure. Please take a look and we can
> try again for
On Thu, 3 Nov 2022 18:16:15 +0200
Avihai Horon wrote:
> Add implementation of VFIO migration protocol v2. The two protocols, v1
> and v2, will co-exist and in next patch v1 protocol will be removed.
>
> There are several main differences between v1 and v2 protocols:
> - VFIO device state is now
On Tue, Oct 25, 2022, at 8:13 AM, Chao Peng wrote:
> This new KVM exit allows userspace to handle memory-related errors. It
> indicates an error happens in KVM at guest memory range [gpa, gpa+size).
> The flags includes additional information for userspace to handle the
> error. Currently bit 0
On Tue, Nov 15, 2022, 10:24 PM Ani Sinha wrote:
> On Wed, Nov 16, 2022 at 2:58 AM John Snow wrote:
> >
> > Instead of using a hardcoded timeout, just rely on Avocado's built-in
> > test case timeout. This helps avoid timeout issues on machines where 60
> > seconds is not sufficient.
> >
> > Sign
The Cirrus CI service has announced the intent to discontinue
support for x86_64 macOS CI runners. They already have aarch64
runners available and require all projects to switch to these
images before Jan 1st 2023. The different architecture is
merely determined by the image name requested.
For aa
From: Francesco Cagnin
These helpers will be also used for HVF. Aside from reformatting a
couple of comments for 'checkpatch.pl' and updating meson to compile
'hyp_gdbstub.c', this is just code motion.
Signed-off-by: Francesco Cagnin
---
target/arm/hyp_gdbstub.c | 242 +
From: Francesco Cagnin
Support is added for single-stepping, software breakpoints, hardware
breakpoints and watchpoints. The code has been structured like the KVM
counterpart (and many parts are basically identical).
Guests can be debugged through the gdbstub.
Signed-off-by: Francesco Cagnin
-
From: Francesco Cagnin
This patch series aims to add gdbstub support to HVF (the 'QEMU
accelerator on macOS that employs Hypervisor.framework') on Apple
Silicon hosts.
The proposed implementation, structured like the KVM counterpart,
handles single-stepping, software breakpoints, hardware breakp
From: Francesco Cagnin
This proved to be required when debugging the Linux kernel's initial
code, as the Hypervisor framework was triggering 'EC_SYSTEMREGISTERTRAP'
VM exits after enabling trap exceptions with
'hv_vcpu_set_trap_debug_exceptions()'.
Signed-off-by: Francesco Cagnin
---
target/ar
The motivation and description are contained in the last patch in this set.
Will copy paste it here for convenience:
In order to evaluate write amplification factor (WAF) within the storage
stack it is important to know the number of bytes written to the
controller. The existing SMART
In order to evaluate write amplification factor (WAF) within the storage
stack it is important to know the number of bytes written to the
controller. The existing SMART log value of Data Units Written is too
coarse (given in units of 500 Kb) and so we add the SMART health
information extended from
In order to return the units_{read/written} required by the SMART log we
need to shift the number of bytes value by BDRV_SECTORS_BITS and multiply
by 1000. This is a prep patch that moves this adjustment to where the SMART
log is calculated in order to use the stats struct for calculating OCP
exten
On Wed, Nov 16, 2022 at 12:15 PM Daniel P. Berrangé wrote:
>
> On Wed, Nov 16, 2022 at 10:23:52AM +, Daniel P. Berrangé wrote:
> > On Wed, Nov 16, 2022 at 09:03:31AM +, Or Ozeri wrote:
> > > > -Original Message-
> > > > From: Daniel P. Berrangé
> > > > Sent: 15 November 2022 19:47
With LPA2, the effective output address size is at most 48 bits when
TCR.DS == 0. This case is currently unhandled in the page table walker,
where we happily assume LVA/64k granule when outputsize > 48 and
param.ds == 0, resulting in the wrong conversion to be used from a
page table descriptor to a
Am 02.09.22 um 09:55 schrieb Pierre Morel:
Hi,
The implementation of the CPU Topology in QEMU has been drastically
modified since the last patch series and the number of LOCs has been
greatly reduced.
Unnecessary objects have been removed, only a single S390Topology object
is created to support
On 11/15/22 16:41, Emanuele Giuseppe Esposito wrote:
To sum up on what was discussed in this serie, I don't really see any
strong objection against these patches, so I will soon send v3 which is
pretty much the same except for patch 1, which will be removed.
I think these patches are useful and
On 11/16/22 19:23, Michael S. Tsirkin wrote:
On Wed, Nov 16, 2022 at 07:12:32PM +0300, Vladimir Sementsov-Ogievskiy wrote:
Hi all! Please look at 02 for the details.
In the future, pls use --subject-prefix='PATCH RFC' with git-format-patch to
add same prefix to all patches.
If you are resendin
On Wed, Nov 16, 2022 at 07:12:34PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> Hi all! That's an RFC patch.
>
> The problem is that SHPC protocol says that power-led is blinking for 5
> seconds before actual turning-on the device. If we call device-del
> during this time the attention button pres
On Wed, Nov 16, 2022 at 07:12:32PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> Hi all! Please look at 02 for the details.
In the future, pls use --subject-prefix='PATCH RFC' with git-format-patch to
add same prefix to all patches.
If you are resending, add 'resend' in the subject, or increase th
On Wed, Nov 16, 2022 at 07:12:32PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> Hi all! Please look at 02 for the details.
I got 2 copies donnu which to reply to.
> Vladimir Sementsov-Ogievskiy (2):
> hw/pci/shpc: introduce FOR_EACH_DEVICE_IN_SLOT
> qapi: introduce DEVICE_POWER_ON for SHPC h
On Tue, Nov 15, 2022 at 12:26:17PM +0100, Klaus Jensen wrote:
> On Nov 14 14:50, Joel Granados wrote:
> > In order to evaluate write amplification factor (WAF) within the storage
> > stack it is important to know the number of bytes written to the
> > controller. The existing SMART log value of Dat
Hi all! Please look at 02 for the details.
Vladimir Sementsov-Ogievskiy (2):
hw/pci/shpc: introduce FOR_EACH_DEVICE_IN_SLOT
qapi: introduce DEVICE_POWER_ON for SHPC hotplug
hw/pci/shpc.c | 53 +-
qapi/qdev.json | 23 ++
2 f
Introduce a macro to loop through devices like in
shpc_free_devices_in_slot(), as we are going to add one more similar
function.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/pci/shpc.c | 37 -
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git
Hi all! That's an RFC patch.
The problem is that SHPC protocol says that power-led is blinking for 5
seconds before actual turning-on the device. If we call device-del
during this time the attention button press is ignored and we never get
DEVICE_DELETED event, which is unexpected for the user.
I
On 11/16/22 09:43, Klaus Jensen wrote:
From: Klaus Jensen
It is not given that the current master will release the bus after a
transfer ends. Only schedule a pending master if the bus is idle.
Fixes: 37fa5ca42623 ("hw/i2c: support multiple masters")
Signed-off-by: Klaus Jensen
---
hw/i2c/as
On Wed, 16 Nov 2022 16:35:10 +0100
Philippe Mathieu-Daudé wrote:
> On 16/11/22 16:27, Igor Mammedov wrote:
> > and use cast to TYPE_PCI_BRIDGE instead.
> >
> > Signed-off-by: Igor Mammedov
> > ---
> > include/hw/pci/pci.h | 11 +--
> > include/hw/pci/pci_bridge.h
I have sent a v2 with a fixed MSS mask constant but haven't tested it.
Thanks,
Stefan
The Large-Send Task Offload Tx Descriptor (9.2.1 Transmit) has a
Large-Send MSS value where the driver specifies the MSS. See the
datasheet here:
http://realtek.info/pdf/rtl8139cp.pdf
The code ignores this value and uses a hardcoded MSS of 1500 bytes
instead. When the MTU is less than 1500 bytes t
Hi, All,
Very appreciated for your time on reviewing our patch.
The second CI failure caused by our patch has been addressed. One simple
way is moving "#endif" in qemu/tests/bench/xbzrle-bench.c from line 46 to line
450.
We have submitted patch v7 to update this modification. Thanks f
On 16/11/22 16:27, Igor Mammedov wrote:
and use cast to TYPE_PCI_BRIDGE instead.
Signed-off-by: Igor Mammedov
---
include/hw/pci/pci.h | 11 +--
include/hw/pci/pci_bridge.h| 1 +
hw/acpi/pcihp.c| 3 +--
hw/i386/acpi-build.c
On 16/11/22 16:20, Greg Kurz wrote:
Hi Vaibhav,
Nice to see some people are still building QEMU at IBM ;-)
On Wed, 16 Nov 2022 18:47:43 +0530
Vaibhav Jain wrote:
Kowshik reported that building qemu with GCC 12.2.1 for 'ppc64-softmmu'
target is failing due to following build warnings:
../
This patch updates code of avx512 support for xbzrle_encode_buffer function.
We mainly modified code in xbzrle-bench.c for addressing CI failure.
Signed-off-by: ling xu
Co-authored-by: Zhou Zhao
Co-authored-by: Jun Jin
ling xu (2):
Update AVX512 support for xbzrle_encode_buffer
Unit test
Unit test code is in test-xbzrle.c, and benchmark code is in xbzrle-bench.c
for performance benchmarking. we have modified xbzrle-bench.c to address
CI problem.
Signed-off-by: ling xu
Co-authored-by: Zhou Zhao
Co-authored-by: Jun Jin
---
tests/bench/meson.build| 4 +
tests/bench/xbzrle-b
This commit is the same with [PATCH v6 1/2], and provides avx512 support for
xbzrle_encode_buffer
function to accelerate xbzrle encoding speed. Runtime check of avx512
support and benchmark for this feature are added. Compared with C
version of xbzrle_encode_buffer function, avx512 version can ach
Code has not been used practically since its inception (2004)
f2aa58c6f4a20 UniNorth PCI bridge support
or maybe even earlier, but it was consuming contributors time
as QEMU was being rewritten.
Drop it for now. Whomever would like to actually
use the thing, can make sure it actually works/reintr
and use cast to TYPE_PCI_BRIDGE instead.
Signed-off-by: Igor Mammedov
---
include/hw/pci/pci.h | 11 +--
include/hw/pci/pci_bridge.h| 1 +
hw/acpi/pcihp.c| 3 +--
hw/i386/acpi-build.c | 5 ++---
hw/pci-bridge/cxl_downstream.c
On 16/11/22 14:17, Vaibhav Jain wrote:
Kowshik reported that building qemu with GCC 12.2.1 for 'ppc64-softmmu'
target is failing due to following build warnings:
../target/ppc/cpu_init.c:7018:13: error: 'ppc_restore_state_to_opc' defined
but not used [-Werror=unused-function]
7018 | static
Igor Mammedov (2):
remove DEC 21154 PCI bridge
pci: drop redundant PCIDeviceClass::is_bridge field
hw/pci-bridge/dec.h| 9 --
include/hw/pci/pci.h | 11 +-
include/hw/pci/pci_bridge.h| 1 +
include/hw/pci/pci_ids.h | 1 -
hw/acpi/pcihp.
Hi Vaibhav,
Nice to see some people are still building QEMU at IBM ;-)
On Wed, 16 Nov 2022 18:47:43 +0530
Vaibhav Jain wrote:
> Kowshik reported that building qemu with GCC 12.2.1 for 'ppc64-softmmu'
> target is failing due to following build warnings:
>
>
> ../target/ppc/cpu_init.c:7018:13:
The next patches will start control SVQ if possible. However, we don't
know if that will be possible at qemu boot anymore.
Since the moved checks will be already evaluated at net/ to know if it
is ok to shadow CVQ, move them.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 33 ++--
SVQ may run or not in a device depending on runtime conditions (for
example, if the device can move CVQ to its own group or not).
Allocate the SVQ array unconditionally at startup, since its hard to
move this allocation elsewhere.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 4
It will be reused at vdpa device start so let's extract in its own function
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
net/vhost-vdpa.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 6811089231
So the caller can choose which ASID is destined.
No need to update the batch functions as they will always be called from
memory listener updates at the moment. Memory listener updates will
always update ASID 0, as it's the passthrough ASID.
All vhost devices's ASID are 0 at this moment.
Signed-
By the end of this series CVQ is shadowed as long as the features
support it.
Since we don't know at the beginning of qemu running if this is
supported, move the event notifier handler setting to the start of the
SVQ, instead of the start of qemu run.
Signed-off-by: Eugenio Pérez
Acked-by: Jason
Control VQ is the way net devices use to send changes to the device state, like
the number of active queues or its mac address.
QEMU needs to intercept this queue so it can track these changes and is able to
migrate the device. It can do it from 1576dbb5bbc4 ("vdpa: Add x-svq to
NetdevVhostVDPAOpt
CVQ can be shadowed two ways:
- Device has x-svq=on parameter (current way)
- The device can isolate CVQ in its own vq group
QEMU needs to check for the second condition dynamically, because CVQ
index is not known at initialization time. Since this is dynamic, the
CVQ isolation could vary with dif
Isolate control virtqueue in its own group, allowing to intercept control
commands but letting dataplane run totally passthrough to the guest.
Signed-off-by: Eugenio Pérez
---
v7:
* Never ask for number of address spaces, just react if isolation is not
possible.
* Return ASID ioctl errors inste
The memory listener that thells the device how to convert GPA to qemu's
va is registered against CVQ vhost_vdpa. memory listener translations
are always ASID 0, CVQ ones are ASID 1 if supported.
Let's tell the listener if it needs to register them on iova tree or
not.
Signed-off-by: Eugenio Pérez
This function used to trust in v->shadow_vqs != NULL to know if it must
start svq or not.
This is not going to be valid anymore, as qemu is going to allocate svq
unconditionally (but it will only start them conditionally).
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 4 ++--
1 file
1 - 100 of 217 matches
Mail list logo
