We're about to start validating PAGE_EXEC, which means
that we've got to mark the commpage executable. We had
been placing the commpage outside of reserved_va, which
was incorrect and lead to an abort.
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
The function is not used outside of cpu-exec.c. Move it and
its subroutines up in the file, before the first use.
Reviewed-by: Alistair Francis
Acked-by: Ilya Leoshkevich
Tested-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 3 -
accel/tcg/cpu-exec.c
While there are no target-specific nonfaulting probes,
generic code may grow some uses at some point.
Note that the attrs argument was incorrect -- it should have
been MEMTXATTRS_UNSPECIFIED. Just use the simpler interface.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
--
The following changes since commit e93ded1bf6c94ab95015b33e188bc8b0b0c32670:
Merge tag 'testing-pull-request-2022-08-30' of https://gitlab.com/thuth/qemu
into staging (2022-08-31 18:19:03 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-202209
Dongli Zhang writes:
> Hi Markus,
>
> On 8/30/22 4:04 AM, Markus Armbruster wrote:
>> Dongli Zhang writes:
>>
>>> The below is printed when printing help information in qemu-system-x86_64
>>> command line, and when CONFIG_TRACE_LOG is enabled:
>>>
>>> $ qemu-system-x86_64 -d help
>>> ... ...
>>
Hi Marc-André,
On Wed, Aug 31, 2022 at 8:54 PM Marc-André Lureau
wrote:
>
> Hi Bin
>
> On Wed, Aug 24, 2022 at 1:42 PM Bin Meng wrote:
>>
>> From: Bin Meng
>>
>> At present get_tmp_filename() has platform specific implementations
>> to get the directory to use for temporary files. Switch over t
Hi,
On Tue, Aug 2, 2022 at 3:52 PM Bin Meng wrote:
>
> Support for the unix socket has existed both in BSD and Linux for the
> longest time, but not on Windows. Since Windows 10 build 17063 [1],
> the native support for the unix socket has come to Windows. Starting
> this build, two Win32 process
On 8/31/2022 8:50 PM, Gerd Hoffmann wrote:
When the guest (firmware specifically) knows how big
the address space actually is it can be used better.
Some more background:
https://bugzilla.redhat.com/show_bug.cgi?id=2084533
QEMU enables host-phys-bits for "-cpu host/max" in
host_cpu_max_ins
On 8/31/22 00:17, Ilya Leoshkevich wrote:
page_set_flags(start, start + len, page_flags);
+ tb_invalidate_phys_range(start, start + len);
+
+ CPU_FOREACH(cpu) {
+ cpu_tb_jmp_cache_clear(cpu);
+ }
+
mmap_unlock();
return 0;
error:
I think adding tb_invalidate_
This bit is not saved across interrupts, so we must
delay delivering the interrupt until the skip has
been processed.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1118
Reviewed-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/avr/hel
We cannot deliver two interrupts simultaneously;
the first interrupt handler must execute first.
Reviewed-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a
There is no need to go through cc->tcg_ops when
we know what value that must have.
Reviewed-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/avr/helper
While there are no target-specific nonfaulting probes,
generic code may grow some uses at some point.
Note that the attrs argument was incorrect -- it should have
been MEMTXATTRS_UNSPECIFIED. Just use the simpler interface.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
--
The following changes since commit e93ded1bf6c94ab95015b33e188bc8b0b0c32670:
Merge tag 'testing-pull-request-2022-08-30' of https://gitlab.com/thuth/qemu
into staging (2022-08-31 18:19:03 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-avr-202209
On Tue, Aug 30, 2022 at 12:43:23PM +0200, Markus Armbruster wrote:
> David Gibson writes:
>
> > On Mon, Aug 29, 2022 at 07:00:55PM -0300, Daniel Henrique Barboza wrote:
> >>
> >>
> >> On 8/29/22 00:34, David Gibson wrote:
> >> > On Fri, Aug 26, 2022 at 11:11:44AM -0300, Daniel Henrique Barboza
On 9/1/22 02:02, Wilfred Mallawa wrote:
From: Wilfred Mallawa
Adds a helper macro that implements the `rw1c`
behaviour.
Ex:
uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
if the specified `FIELD` is set (single/multi bit all fields)
then the respective field is cleared and returned to `d
On 8/31/22 19:11, Tom Clark wrote:
I've done a lot of digging in the source and found the code_gen_buffer and determined
that's where the IR generation is being written to
That's not IR generation, but the JIT compiler output.
There's no sequential "byte" format. There's struct TCGOp, which i
Hi Markus and Richard,
Thank you very much for the feedback. I agree this is not a good solution. I
will look for alternatives to add timestamp.
Thank you very much!
Dongli Zhang
On 8/30/22 8:31 AM, Richard Henderson wrote:
> On 8/30/22 04:09, Markus Armbruster wrote:
>> Dongli Zhang writes:
>
And empty bios-tables-test-allowed-diff.h.
Diff of ASL form, cited from qtest testlog.txt:
--- /tmp/asl-0WHMR1.dsl 2022-08-30 11:38:09.406635934 +0800
+++ /tmp/asl-APDMR1.dsl 2022-08-30 11:38:09.403635663 +0800
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler
Since it will be heavily used in next patch, define macro
NVDIMM_DEVICE_DSM_UUID for "4309AC30-0D11-11E4-9191-0800200C9A66", which is
NVDIMM device specific method uuid defined in NVDIMM _DSM interface spec,
Section 3. [1]
No functional changes in this patch.
[1] https://pmem.io/documents/IntelOp
Recent ACPI spec [1] has defined NVDIMM Label Methods _LS{I,R,W}, which
deprecates corresponding _DSM Functions defined by PMEM _DSM Interface spec
[2].
Since the semantics of the new Label Methods are same as old _DSM
methods, the implementations here simply wrapper old ones.
ASL form diff can b
In If condition, using bitwise and/or, rather than logical and/or.
The result change in AML code:
If (((Local6 == Zero) | (Arg0 != Local0)))
==>
If (((Local6 == Zero) || (Arg0 != Local0)))
If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One)))
==>
If (((ObjectType (Arg3) == 0x04) && (SizeOf
Signed-off-by: Robert Hoo
Reviewed-by: Jingqi Liu
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..eb8bae1407 100644
--- a/tests/qtest
Originally NVDIMM Label methods was defined in Intel PMEM _DSM Interface
Spec [1], of function index 4, 5 and 6.
Recent ACPI spec [2] has deprecated those _DSM methods with ACPI NVDIMM
Label Methods _LS{I,R,W}. The essence of these functions has no changes.
This patch set is to update QEMU emulati
These topics are interesting. I have two questions.
1. Can we join it on online? If so, could you share the meeting link before the
meeting.
2. If it is only offline, could you share the meeting content to the public?
Thanks,
Zhiwei
On Mon, Aug 22, 2022 at 07:30:36AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 8/22/22 00:29, Alexey Kardashevskiy wrote:
> >
> >
> > On 22/08/2022 13:05, David Gibson wrote:
> > > On Fri, Aug 19, 2022 at 06:42:34AM -0300, Daniel Henrique Barboza wrote:
> > > >
> > > >
> > > > On 8/18/22 2
On 8/31/2022 6:39 PM, Daniel P. Berrangé wrote:
On Wed, Aug 31, 2022 at 05:18:34PM +0800, Wang, Lei wrote:
On 8/31/2022 4:49 PM, Daniel P. Berrangé wrote:
On Wed, Aug 31, 2022 at 02:23:51PM +0800, Wang, Lei wrote:
On 10/2/2015 1:30 AM, marcandre.lur...@redhat.com wrote:
From: Marc-André Lu
From: Wilfred Mallawa
Adds a helper macro that implements the `rw1c`
behaviour.
Ex:
uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
if the specified `FIELD` is set (single/multi bit all fields)
then the respective field is cleared and returned to `data`.
If ALL bits of the bitfield are not
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
The below is printed when printing help information in qemu-system-x86_64
command line, and when CONFIG_TRACE_LOG is enabled:
$ qemu-system-x86_64 -d help
... ...
trace:PATTERN enable trace events
Use "-d trace:help" to get a list of trace events.
--
The following changes since commit 93fac696d241dccb04ebb9d23da55fc1e9d8ee36:
Open 7.2 development tree (2022-08-30 09:40:41 -0700)
are available in the Git repository at:
https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20220831
for you to fetch changes up to
/danielhb/qemu.git tags/pull-ppc-20220831
for you to fetch changes up to 2d9c27ac5c035823315f68c227ca1cc6313e9842:
ppc4xx: Fix code style problems reported by checkpatch (2022-08-31 14:08:06
-0300)
ppc patch queue for 2022-08-31:
In
Am 31. August 2022 16:30:10 UTC schrieb BALATON Zoltan :
>On Wed, 31 Aug 2022, Bernhard Beschow wrote:
>> According to good QOM practice, an object should only deal with objects
>> of its own sub tree. Having devices create an alias on the machine
>> object doesn't respect this good practice. To re
On Wed, 31 Aug 2022, Daniel Henrique Barboza wrote:
The following changes since commit 93fac696d241dccb04ebb9d23da55fc1e9d8ee36:
Open 7.2 development tree (2022-08-30 09:40:41 -0700)
are available in the Git repository at:
https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20220831
for you
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
Message-Id:
<0a3e454eb7fd5f2b807a9c752c28693f27829f1d.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc4xx_devs.c | 2 +-
1 file c
Hello,
Thanks so much for reading this and I appreciate any and all time you put
into this.
I'm a dev working on a project that's using QEMU as its basis. I'm
interested in extracting the IR representation of translation blocks,
preferably at the instruction level, to do some analysis on it. In v
Hi Markus,
On 8/30/22 4:04 AM, Markus Armbruster wrote:
> Dongli Zhang writes:
>
>> The below is printed when printing help information in qemu-system-x86_64
>> command line, and when CONFIG_TRACE_LOG is enabled:
>>
>> $ qemu-system-x86_64 -d help
>> ... ...
>> trace:PATTERN enable trace event
From: BALATON Zoltan
In pegasos2 section move imply before select to match other sections.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Message-Id:
<4d46dde64c2e5df6db3f92426fb3ae885939c2b0.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/K
From: Cédric Le Goater
Having an explicit I2C model object will help if one day we want to
add I2C devices on the bus from the machine init routine.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: Symplify sysbus device casts for readibility]
Signed-off-by: BALAT
From: BALATON Zoltan
These are only used by the board code so move out from the shared SoC
model and put it in the boards file.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Message-Id:
<2b23bcaaf191f96b217cbd06a6038694024862c3.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: D
From: BALATON Zoltan
This device is shared between different 4xx socs.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: BALATON Zoltan
Message-Id:
<5b13ebfd12a71a28035bed5a915cbeee81cf21d1.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h
From: BALATON Zoltan
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Message-Id:
<62798fbe9c200da3e0c870601ed9162b1c3a50a5.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405_uc.c | 5 +++--
hw/ppc/ppc440_bamboo.c | 27 ++--
From: BALATON Zoltan
The PLB is shared between 405 and 440 so move it to the shared file.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: BALATON Zoltan
Message-Id:
<2498384bf3e18959ee8cb984d72fb66b8a6ecadc.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw
From: BALATON Zoltan
Now that shared PPC4xx devices are separated from PPC405 ones we can
drop this depencency.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/Kconfig| 1 -
hw/ppc/sam460ex.c | 1 -
2 files chang
From: BALATON Zoltan
Make ppc-uic a subclass of ppc4xx-dcr-device which will handle the cpu
link and make it uniform with the other PPC4xx devices.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/intc/ppc-uic.c |
From: Cédric Le Goater
The DMA controller is currently modeled as a DCR device with a couple
of IRQs.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
<4738b3c7cf18c328f05aaaddc555a4621943133
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405_boards.c | 56 +-
1 file changed, 39 insertions(+), 17 dele
From: BALATON Zoltan
This device is shared between different 4xx socs.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: BALATON Zoltan
Message-Id:
<63d9b14c8ff5f73e35bffca1036394b5235735ee.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h
From: Cédric Le Goater
The OCM controller is currently modeled as a simple DCR device with
a couple of memory regions.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
Signed-off-by: Daniel
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: Simplify sysbus device casts for readability]
Signed-off-by: BALATON Zoltan
Message-Id:
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405.h| 3 ++-
hw/ppc/ppc405_uc.c | 28
From: Cédric Le Goater
The OPB arbitrer is currently modeled as a simple SysBus device with a
unique memory region.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
<38476bc43d2332db2f09dbede
From: Cédric Le Goater
The GPT controller is currently modeled as a SysBus device with a
unique memory region, a couple of IRQs and a timer.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes, add finalize method]
Signed-off-by: BALATON Z
On Tue, Aug 23, 2022 at 08:31:03PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On 8/23/22 01:23, Stefan Hajnoczi wrote:
> > The remainder of the patch series reworks the existing QEMU
> > bdrv_register_buf()
> > API so virtio-blk emulation efficiently map guest RAM for libblkio - some
> > libblki
From: BALATON Zoltan
The EBC is shared between 405 and 440 so move it to shared file.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: BALATON Zoltan
Message-Id:
<10eae70509ca4bd74858fc2c0a0f0e4eb9330199.1660746880.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc
From: Cédric Le Goater
Drop the use of ppc4xx_init() and duplicate a bit of code related to
clocks in the SoC realize routine. We will clean that up in the
following patches.
ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe
this could be done in model initializer of the CP
From: Cédric Le Goater
The Device Control Registers (DCR) of on-SoC devices are accessed by
software through the use of the mtdcr and mfdcr instructions. These
are converted in transactions on a side band bus, the DCR bus, which
connects the on-SoC devices to the CPU.
Ideally, we should model th
From: Cédric Le Goater
The Memory Access Layer (MAL) controller is currently modeled as a DCR
device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt
the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes, a
From: Cédric Le Goater
The CPC controller is currently modeled as a DCR device.
Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
From: Cédric Le Goater
It has been deprecated since 7.0.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20220809153904.485018-2-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
MAINTAINERS | 2 +-
docs/about/deprecated.rst
From: Cédric Le Goater
It is an initial model to start QOMification of the PPC405 board.
QOM'ified devices will be reintroduced one by one. Start with the
memory regions, which name prefix is changed to "ppc405".
Also, initialize only one RAM bank. The second bank is a dummy one
(zero size) whic
From: Cédric Le Goater
PLB is currently modeled as a simple DCR device. Also drop the
ppc4xx_plb_init() helper and adapt the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: BALATON Zoltan
Signed-off-by: Cédric Le Goater
Message-Id: <20220809153904.485018-4-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405_boards.c | 31 +++
1 file changed, 1
Given that powernv9 and powernv10 uses the same pnv-phb backend, the
logic to allow user created pnv-phbs for powernv10 is already in place.
Let's flip the switch.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.57892
From: Cédric Le Goater
It doesn't belong to the generic machine nor the SoC. Fix a typo in
the name while we are at it.
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
Message-Id: <20220809153904.485018-5-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405_boar
From: Cédric Le Goater
POB is currently modeled as a simple DCR device.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
<2bb1a89182523059ecb0e8d20c22a293534dec17.1660746880.git.bala...@eik.b
Enable pnv-phb user created devices for powernv9 now that we have
everything in place.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.578927-9-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 2 +-
hw/pci-hos
From: Cédric Le Goater
EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init()
helper and adapt the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
Message-Id:
<51a07
User creatable root ports are being parented by the 'peripheral' or the
'peripheral-anon' container. This happens because this is the regular
QOM schema for sysbus devices that are added via the command line.
Let's make this QOM hierarchy similar to what we have with default root
ports, i.e. the r
We have 2 helpers that amends the QOM and parent bus of a given object,
repectively. These 2 helpers are called together, and not by accident.
Due to QOM internals, doing an object_unparent() will result in the
device being removed from its parent bus. This means that changing the
QOM parent requir
When enabling user created PHBs (a change reverted by commit 9c10d86fee)
we were handling PHBs created by default versus by the user in different
manners. The only difference between these PHBs is that one will have a
valid phb3->chip that is assigned during pnv_chip_power8_realize(),
while the use
From: Cédric Le Goater
The GPIO controller is currently modeled as a simple SysBus device
with a unique memory region.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
[balaton: Simplify sysbus device casts for readability]
Signed-off-by: BALATON Zoltan
Message-Id:
Signe
The same rationale provided in the PHB3 bus case applies here.
Note: we could have merged both buses in a single object, like we did
with the root ports, and spare some boilerplate. The reason we opted to
preserve both buses objects is twofold:
- there's not user side advantage in doing so. Unify
The PHB4 backend relies on a link with the corresponding PEC element.
This is trivial to do during machine_init() time for default devices,
but not so much for user created ones.
pnv_phb4_get_pec() is a small variation of the function that was
reverted by commit 9c10d86fee "ppc/pnv: Remove user-cr
For default root ports we have a way of accessing chassis and slot,
before root_port_realize(), via pnv_phb_attach_root_port(). For the
future user created root ports this won't be the case: we can't use
this helper because we don't have access to the PHB phb-id/chip-id
values.
In earlier patches
From: Cédric Le Goater
This moves all the code previously done in the ppc405ep_init() routine
under ppc405_soc_realize(). We can also adjust the number of banks now
that we have control on ppc4xx_sdram_init().
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
Message-Id: <20220809153
The helper is only used in this file.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-13-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 24
hw/ppc/pnv.c | 25 -
include/hw/ppc/pn
We rely on the phb-id and chip-id, which are PHB properties, to assign
chassis and slot to the root port. For default devices this is no big
deal: the root port is being created under pnv_phb_realize() and the
values are being passed on via the 'index' and 'chip-id' of the
pnv_phb_attach_root_port(
The bulk of the work was already done by previous patches.
Use defaults_enabled() to determine whether we need to create the
default devices or not.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220811163950.578927-7-danielhb..
From: Cédric Le Goater
We will use this machine as a base to define the ref405ep and possibly
the PPC405 hotfoot board as found in the Linux kernel.
Reviewed-by: BALATON Zoltan
Signed-off-by: Cédric Le Goater
Message-Id: <20220809153904.485018-3-...@kaod.org>
Signed-off-by: Daniel Henrique Bar
We need a handful of changes that needs to be done in a single swoop to
turn PnvPHB3 into a PnvPHB backend.
In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and
will hold the PCI bus, change PnvPHB3 parent to TYPE_DEVICE. There are a
couple of instances in pnv_phb3.c that needs to
pnv_parent_qom_fixup() and pnv_parent_bus_fixup() are versions of the
helpers that were reverted by commit 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices". They are needed to amend the QOM and
bus hierarchies of user created pnv-phbs, matching them with default
pnv-phbs.
A new helper
It's unused.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-12-danielhb...@gmail.com>
---
include/hw/pci-host/pnv_phb4.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
i
The PnvPHB3 bus init consists of initializing the pci_io and pci_mmio
regions, registering it via pci_register_root_bus() and then setup the
iommu.
We'll want to init the bus from outside pnv_phb3.c when the bus is
removed from the PnvPHB3 device and put into a new parent PnvPHB device.
The new pn
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Cédric Le Goater
The unified pnv-phb-root-port can be used instead. The phb4-root-port
device isn't exposed to the user in any official QEMU release so there's
no ABI breakage in removing it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-9-danielhb...@gmai
We support only a single root port, PNV_PHB_ROOT_PORT.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-10-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb.c | 7 +--
hw/ppc/pnv.c | 9 +
include/hw/ppc/pnv.h | 3 +--
3 fi
From: "Lucas Mateus Castro (alqotel)"
When an overflow exception occurs and OE is set the intermediate result
should be adjusted (by subtracting from the exponent) to avoid rounding
to inf. The same applies to an underflow exceptionion and UE (but adding
to the exponent). To do this set the fp_st
The attribute is unused.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-11-danielhb...@gmail.com>
---
hw/pci-host/pnv_phb4_pec.c | 2 --
include/hw/pci-host/pnv_phb4.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/hw/pci-host/pn
The unified pnv-phb-root-port can be used in its place. There is no ABI
breakage in doing so because no official QEMU release introduced user
creatable pnv-phb3-root-port devices.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-8-danielhb...
Similar to what we already did for the PnvPHB3 device, let's add a
helper to init the bus when using a PnvPHB4. This helper will be used by
PnvPHb when PnvPHB4 turns into a backend.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Message-Id: <20220624084921.399219-5-danielhb.
Change the parent type of the PnvPHB4 device to TYPE_PARENT since the
PCI bus is going to be initialized by the PnvPHB parent. Functions that
needs to access the bus via a PnvPHB4 object can do so via the
phb4->phb_base pointer.
pnv_phb4_pec now creates a PnvPHB object.
The powernv9 machine class
From: Nicholas Piggin
The SBE (Self Boot Engine) are on-chip microcontrollers that perform
early boot steps, as well as provide some runtime facilities (e.g.,
timer, secure register access, MPIPL). The latter facilities are
accessed mostly via a message system called SBEFIFO.
This driver provide
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until now, has no additional attributes.
The main difference between the PHB3 and PHB4 root ports is that
pnv-phb4-root-port has the pnv_phb4_root_port_
From: Nicholas Piggin
ppc_cpu_compare_class_pvr_mask() should match the best CPU class in the
family, because it is used by the KVM subsystem to find the host CPU
class. Since commit 03ae4133ab8 ("target-ppc: Add pvr_match()
callback"), it matches any class in the family (the first one in the
com
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has the same user API as the other
PHB, namely being a PCIHostBridge and having chip-id and index
properties. It also has a 'backend' pointer that will be initialized
with the PHB implementatio
From: "Lucas Mateus Castro (alqotel)"
Added the possibility of recalculating a result if it overflows or
underflows, if the result overflow and the rebias bool is true then the
intermediate result should have 3/4 of the total range subtracted from
the exponent. The same for underflow but it shoul
The following changes since commit 93fac696d241dccb04ebb9d23da55fc1e9d8ee36:
Open 7.2 development tree (2022-08-30 09:40:41 -0700)
are available in the Git repository at:
https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20220831
for you to fetch changes up to
Thomas Huth writes:
> On 26/08/2022 19.21, Alex Bennée wrote:
>> We should be aiming to keep our tests under 2 minutes so lets reduce
>> the default timeout to that. Tests that we know take longer should
>> explicitly set a longer timeout.
>> Signed-off-by: Alex Bennée
>> ---
>> tests/avocad
On 8/30/22 14:12, Stefan Hajnoczi wrote:
Please check the proposed release schedule and let me know if they fall
on inconvenient dates:
- 2022-08-30: Beginning of development phase
- 2022-11-1: Soft feature freeze. Only bug fixes after this point. All feature
changes must be already in a sub mai
1 - 100 of 205 matches
Mail list logo
