[RFC] hw/nvme: Use irqfd to send interrupts

Use irqfd to directly notify KVM to inject interrupts. This is done by registering a virtual IRQ(virq) in KVM and associate the virq with an irqfd, so that KVM can directly inject the interrupt when it receives notification from the irqfd. This approach is supposed to improve performance because i

Re: [PATCH 0/2] Hexagon (target/hexagon) bug fixes for mem_noshuf

On 7/8/22 02:35, Taylor Simpson wrote: Recall that the semantics of a Hexagon mem_noshuf packet are that the store effectively happens before the load. There are two bug fixes in this series. Taylor Simpson (2): Hexagon (target/hexagon) fix store w/mem_noshuf & predicated load Hexagon (t

Re: [PATCH v4] hw/nvme: Use ioeventfd to handle doorbell updates

at 10:24 PM, Jinhao Fan wrote: > @@ -5793,6 +5891,7 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const > NvmeRequest *req) > uint64_t dbs_addr = le64_to_cpu(req->cmd.dptr.prp1); > uint64_t eis_addr = le64_to_cpu(req->cmd.dptr.prp2); > int i; > +int ret; > I just noticed th

Re: [PATCH RFC v2 0/2] arm: enable MTE for QEMU + kvm

On 7/7/22 21:46, Cornelia Huck wrote: If I'm not misunderstanding things, we need a way to fault in a page together with the tag; doing that in one go is probably the only way that we can be sure that this is race-free on the QEMU side. That's my understanding as well. r~

Re: [PATCH] scsi/lsi53c895a: fix use-after-free in lsi_do_msgout (CVE-2022-0216)

On 220705 2205, Mauro Matteo Cascella wrote: > Set current_req->req to NULL to prevent reusing a free'd buffer in case of > repeated SCSI cancel requests. Thanks to Thomas Huth for suggesting the patch. > > Fixes: CVE-2022-0216 > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/972 > Signed

Re: What to do with the nanomips disassembler (was: [PATCH] disas: Remove libvixl disassembler)

On 04/07/2022 14.22, Milica Lazarevic wrote: On 09/06/2022 18.31, Vince Del Vecchio wrote: ... Regardless, I think we can look at converting the existing disassembler from C++ to C.  That would address the current concern, right? > Right - if it's not too much of a hassle that would b

Re: [PATCH v9 05/21] job.c: add job_lock/unlock while keeping job.h intact

On 7/6/22 23:15, Emanuele Giuseppe Esposito wrote: With "intact" we mean that all job.h functions implicitly take the lock. Therefore API callers are unmodified. This means that: - many static functions that will be always called with job lock held become _locked, and call _locked functions -

Re: Intermittent meson failures on msys2

On 08/07/2022 15.13, Daniel P. Berrangé wrote: On Fri, Jul 08, 2022 at 04:41:48PM +0400, Marc-André Lureau wrote: Hi On Mon, Jun 27, 2022 at 6:41 AM Richard Henderson < richard.hender...@linaro.org> wrote: Hi guys, There's an occasional failure on msys2, where meson fails to capture the outp

Re: [PATCH v3] hw: m25p80: Add Block Protect and Top Bottom bits for write protect

On [2022 Jul 08] Fri 09:45:52, Iris Chen wrote: > Signed-off-by: Iris Chen Reviewed-by: Francisco Iglesias > --- > Cosmetic suggestions addressed. > > hw/block/m25p80.c | 102 -- > 1 file changed, 90 insertions(+), 12 deletions(-) > > diff --git a

[PATCH v3] hw: m25p80: Add Block Protect and Top Bottom bits for write protect

Signed-off-by: Iris Chen --- Cosmetic suggestions addressed. hw/block/m25p80.c | 102 -- 1 file changed, 90 insertions(+), 12 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 50b523e5b1..f3b401cf90 100644 --- a/hw/block/m25p80.c

Re: [RFC 0/8] Introduce an extensible static analyzer

On Wed, Jul 6, 2022 at 11:15 AM Daniel P. Berrangé wrote: > For clang-tidy, I've been trying it out integrated into emacs > via eglot and clangd. This means I get clang-tidy errors reported > interactively as I write code, so wouldn't need to run a full > tree analysis. Unfortunately, unless I'm m

[RISU PATCH v4 29/29] aarch64: Trivial SME test

Signed-off-by: Richard Henderson --- test_sme_aarch64.s | 55 ++ 1 file changed, 55 insertions(+) create mode 100644 test_sme_aarch64.s diff --git a/test_sme_aarch64.s b/test_sme_aarch64.s new file mode 100644 index 000..a5ef909 --- /dev/null +++

[RISU PATCH v4 28/29] aarch64: Add support for ZA storage

Require NVL == SVL on startup, to make it easier to manage reginfo. Most of the time PSTATE.SM would be active with PSTATE.ZA anyway, for any non-trivial SME testing. Extend saved storage only when PSTATE.ZA is active. Use a carefully reserved uint16_t for saving SVCR. Signed-off-by: Richard Hend

[RISU PATCH v4 25/29] Remove return value from reginfo_dump

No uses actually checked the error indication. Even if we wanted to check ferror on the stream, we should do that generically rather than per arch. Signed-off-by: Richard Henderson --- risu.h | 4 ++-- risu_reginfo_aarch64.c | 8 +++- risu_reginfo_arm.c | 6 ++ risu_

[RISU PATCH v4 27/29] aarch64: Tidy reginfo dumping ahead of ZA state

A misalignment for sve_vl, plus add a bit more space on the left for the ZA[n] field name. Signed-off-by: Richard Henderson --- risu_reginfo_aarch64.c | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64

[RISU PATCH v4 23/29] Standardize reginfo_dump_mismatch printing

Hoist the "master vs apprentice" label to apprentice(), since we will want different labels for dumping. Remove all of the "mismatch" text from reginfo_dump_mismatch -- just print "vs". Signed-off-by: Richard Henderson --- risu.h | 4 ++-- risu.c | 1 + risu_re

[RISU PATCH v4 21/29] aarch64: Use arch_init to configure sve

Adjust some of the aarch64 code to look at the reginfo struct instead of looking at test_sve, so that we do not need to pass the --test-sve option in order to dump sve trace files. Diagnose EINVAL as either cpu or kernel does not support SVE. Signed-off-by: Richard Henderson --- risu.h

[RISU PATCH v4 24/29] Add --fulldump and --diffdup options

These allow the inspection of the trace files. Signed-off-by: Richard Henderson --- risu.c | 117 + 1 file changed, 102 insertions(+), 15 deletions(-) diff --git a/risu.c b/risu.c index f613fa9..8d907d9 100644 --- a/risu.c +++ b/risu.c @@

[RISU PATCH v4 18/29] Compute reginfo_size based on the reginfo

This will allow dumping of SVE frames without having to know the SVE vector length beforehand. Signed-off-by: Richard Henderson --- risu.h | 2 +- risu.c | 9 +++-- risu_reginfo_aarch64.c | 4 ++-- risu_reginfo_arm.c | 4 ++-- risu_reginfo_i386.c| 4 ++

[RISU PATCH v4 22/29] ppc64: Use uint64_t to represent double

We want to do exact bitwise comparisons of the data, not be held hostage to IEEE comparisons and NaNs. Signed-off-by: Richard Henderson --- risu_reginfo_ppc64.h | 3 ++- risu_reginfo_ppc64.c | 29 + 2 files changed, 11 insertions(+), 21 deletions(-) diff --git a/ris

Re: [Qemu-devel] [PATCH v1] virtio-scsi: Send "REPORTED LUNS CHANGED" sense data upon a disk hotplug.

Ping? On 2022-05-31 15:22:37 -0500, Venu Busireddy wrote: > When a disk is hotplugged, QEMU reports a VIRTIO_SCSI_EVT_RESET_RESCAN > event, but does not send the "REPORTED LUNS CHANGED" sense data. This > does not conform to Section 5.6.6.3 of the VirtIO specification, which > states "Events wil

[RISU PATCH v4 19/29] aarch64: Assume system support for SVE

SVE support is no longer new, assume it's present. Signed-off-by: Richard Henderson --- risu_reginfo_aarch64.h | 4 risu_reginfo_aarch64.c | 24 2 files changed, 28 deletions(-) diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index c33b86f..efbca56 10

[RISU PATCH v4 17/29] Add magic and size to the trace header

Sanity check that we're not getting out of sync with the trace stream. This will be especially bad with the change in size of the sve save data. Signed-off-by: Richard Henderson --- risu.h | 10 +++- risu.c | 162 - 2 files changed, 136 i

[RISU PATCH v4 20/29] aarch64: Reorg sve reginfo to save space

Mirror the signal frame by storing all of the registers as a lump. Use the signal macros to pull out the values. Signed-off-by: Richard Henderson --- risu_reginfo_aarch64.h | 45 ++- risu_reginfo_aarch64.c | 171 - 2 files changed, 108 insertions

[RISU PATCH v4 11/29] Always write for --master

For trace, master of course must write to the file we create. For sockets, we can report mismatches from either end. At present, we are reporting mismatches from master. Reverse that so that we report mismatches from the apprentice, just as we do for trace. Reviewed-by: Alex Bennée Signed-off-

[RISU PATCH v4 16/29] Split out recv_register_info

We will want to share this code when dumping. Signed-off-by: Richard Henderson --- risu.c | 50 ++ 1 file changed, 34 insertions(+), 16 deletions(-) diff --git a/risu.c b/risu.c index b91ad38..80bc3b1 100644 --- a/risu.c +++ b/risu.c @@ -166,6 +16

[RISU PATCH v4 12/29] Simplify syncing with master

Do not pass status like RES_BAD_IO from apprentice to master. This means that when master reports i/o error that we know it came from master; the apprentice will report its own i/o error. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- reginfo.c | 11 +-- 1 file changed, 5

[RISU PATCH v4 13/29] Split RES_MISMATCH for registers and memory

By remembering the specific comparison that failed, we do not have to try again when it comes time to report. This makes the mem_used flag redundant. Also, packet_mismatch is now redundant with RES_BAD_IO. This means that the only thing that report_match_status does is to report on register stat

[RISU PATCH v4 09/29] Unify i/o functions and use RisuResult

Push the trace check down from the function calling the reginfo function down into the i/o function. This means we don't have to pass a function pointer. Return a RisuResult from the i/o functions. This fixes a minor bug in send_register_info (even before the conversion to RisuResult), which ret

[RISU PATCH v4 07/29] Add enum RisuOp

Formalize the set of defines, plus -1, into an enum. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- risu.h | 23 +++ reginfo.c | 32 +++- risu_aarch64.c | 6 +++--- risu_arm.c | 6 +++--- risu_i386.c| 4 ++--

[RISU PATCH v4 10/29] Pass non-OK result back through siglongjmp

Rather than doing some work in the signal handler and some work outside, move all of the non-resume work outside. This works because we arranged for RES_OK to be 0, which is the normal return from sigsetjmp. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- risu.c | 50 +

[RISU PATCH v4 02/29] Unify master_fd and apprentice_fd to comm_fd

Any one invocation cannot be both master and apprentice. Let's use only one variable for the file descriptor. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- risu.c | 40 1 file changed, 20 insertions(+), 20 dele

[RISU PATCH v4 04/29] Adjust tracefile open for write

Truncate the new output file. Rely on umask to remove group+other file permissions, if desired. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- risu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/risu.c b/risu.c index 2f6a677..81

[RISU PATCH v4 08/29] Add enum RisuResult

Formalize the random set of numbers into an enum. Doing this makes it easy to see that one of the responses in recv_and_compare_register_info was inconsistent. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- risu.h| 25 + reginfo.c | 32 +++

[RISU PATCH v4 06/29] Make some risu.c symbols static

These are unused in other translation units. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- risu.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/risu.c b/risu.c index 26dc116..ab17c71 100644 --- a/risu.c +++ b/risu.c @@ -31,18 +31,

[PATCH v4 11/12] tests/qemu-iotests: skip 108 when FUSE is not loaded

Do not merge: Staged in Hanna's branch. Signed-off-by: John Snow --- tests/qemu-iotests/108 | 5 + 1 file changed, 5 insertions(+) diff --git a/tests/qemu-iotests/108 b/tests/qemu-iotests/108 index 9e923d6a59f..54e935acf28 100755 --- a/tests/qemu-iotests/108 +++ b/tests/qemu-iotests/108 @@

[RISU PATCH v4 03/29] Hoist trace file and socket opening

We will want to share this code with --dump. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Hoist socket connecting as well as trace file opening. --- risu.c | 49 +++-- 1 file changed, 23 insertions(+),

[PATCH v4 03/12] tests/vm: switch CentOS 8 to CentOS 8 Stream

The old CentOS image didn't work anymore because it was already EOL at the beginning of 2022. Signed-off-by: John Snow Reviewed-by: Thomas Huth Reviewed-by: Daniel P. Berrangé --- tests/vm/centos | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/vm/centos b/tests/

[PATCH v4 06/12] tests/vm: remove ubuntu.i386 VM test

Ubuntu 18.04 is out of our support window, and Ubuntu 20.04 does not support i386 anymore. The debian project does, but they do not provide any cloud images for it, a new expect-style script would have to be written. Since we have i386 cross-compiler tests hosted on GitLab CI, we don't need to sup

[PATCH v4 01/12] qga: treat get-guest-fsinfo as "best effort"

In some container environments, there may be references to block devices witnessable from a container through /proc/self/mountinfo that reference devices we simply don't have access to in the container, and cannot provide information about. Instead of failing the entire fsinfo command, return stub

[PATCH v6 45/45] linux-user/aarch64: Add SME related hwcap entries

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/elfload.c | 20 1 file changed, 20 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 1de77c7959..ce902dbd56 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@

[PATCH v4 02/12] tests/vm: use 'cp' instead of 'ln' for temporary vm images

If the initial setup fails, you've permanently altered the state of the downloaded image in an unknowable way. Use 'cp' like our other test setup scripts do. Signed-off-by: John Snow Reviewed-by: Thomas Huth Reviewed-by: Daniel P. Berrangé --- tests/vm/centos | 2 +- 1 file changed, 1 insertio

[RISU PATCH v4 26/29] ppc64: Clean up reginfo handling

Several of the gp_reg[] elements are not relevant -- e.g. orig r3, which is related to system calls. Omit those from the original reginfo_init(), so that any differences are automatically hidden. Do not only compare bit 4 of CCR -- this register is 32 bits wide with 8 cr subfields. We should com

[PATCH v4 05/12] tests/vm: upgrade Ubuntu 18.04 VM to 20.04

18.04 has fallen out of our support window, so move ubuntu.aarch64 forward to ubuntu 20.04, which is now our oldest supported Ubuntu release. Notes: This checksum changes periodically; use a fixed point image with a known checksum so that the image isn't re-downloaded on every single invocation.

[PATCH v4 12/12] iotests: fix copy-before-write for macOS and FreeBSD

From: Vladimir Sementsov-Ogievskiy Do not merge: this is a copy of Vladimir's fix that will be taken in through the iotests tree. Signed-off-by: Vladimir Sementsov-Ogievskiy Signed-off-by: John Snow --- tests/qemu-iotests/tests/copy-before-write | 5 + 1 file changed, 5 insertions(+) dif

[PATCH v6 41/45] linux-user: Rename sve prctls

Add "sve" to the sve prctl functions, to distinguish them from the coming "sme" prctls with similar names. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 8 linux-user/syscall.c | 12 ++-- 2 files changed, 10 in

[PATCH v4 09/12] tests/vm: Remove docker cross-compile test from CentOS VM

The fedora container has since been split apart, so there's no suitable nearby target that would support "test-mingw" as it requires both x32 and x64 support -- so either fedora-cross-win32 nor fedora-cross-win64 would be truly suitable. Just remove this test as superfluous with our current CI inf

[PATCH v6 44/45] target/arm: Enable SME for user-only

Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9b54443843..5de7e097e9 100644 --- a/target/arm/cp

[PATCH v6 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/target_cpu.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h index 97a477bd3e..f90359faf2 100644 --- a/linux-user/aarch64/t

[RISU PATCH v4 15/29] Rearrange reginfo and memblock buffers

For send_register_info from master_sigill, do not keep a reginfo buffer on the stack. At the moment, this struct is quite large for aarch64. Put the two reginfo buffers into an array, for the benefit of future dumping. For recv_and_compare_register_info, index this array with constants, so it's

[PATCH v4 07/12] tests/vm: remove duplicate 'centos' VM test

This is listed twice by accident; we require genisoimage to run the test, so remove the unconditional entry. Signed-off-by: John Snow Reviewed-by: Thomas Huth Reviewed-by: Daniel P. Berrangé --- tests/vm/Makefile.include | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests

[RISU PATCH v4 14/29] Merge reginfo.c into risu.c

The distinction between the two is artificial. Following patches will rearrange the functions involved to make it easier for dumping of the trace file. Signed-off-by: Richard Henderson --- Makefile | 2 +- risu.h| 28 +- reginfo.c | 151 --

[PATCH v6 43/45] target/arm: Only set ZEN in reset if SVE present

There's no reason to set CPACR_EL1.ZEN if SVE disabled. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9c58be8b14..9b54443843 100644 --- a/targe

[PATCH v6 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 9 + 1 file changed, 9 insertions(+) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index f7ef36cd9f..9875d609a9 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/l

[PATCH v4 08/12] tests/vm: add 1GB extra memory per core

If you try to run a 16 or 32 threaded test, you're going to run out of memory very quickly with qom-test and a few others. Bump the memory limit to try to scale with larger-core machines. Granted, this means that a 16 core processor is going to ask for 16GB, but you *probably* meet that requiremen

[PATCH v6 35/45] linux-user/aarch64: Add SM bit to SVE signal context

Make sure to zero the currently reserved fields. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 7da0e36c6d..3c

[PATCH v4 10/12] tests/qemu-iotests: hotfix for 307, 223 output

Do not merge; staged in Hanna's branch. Signed-off-by: John Snow --- tests/qemu-iotests/223.out | 4 ++-- tests/qemu-iotests/307.out | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/qemu-iotests/223.out b/tests/qemu-iotests/223.out index 06479415312..26fb347c5da 100

[RISU PATCH v4 05/29] Use EXIT_FAILURE, EXIT_SUCCESS

Some of the time we exit via the return value from main. This can make it easier to tell what it is we're returning. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- comms.c| 26 +- risu.c | 22

[PATCH v6 37/45] linux-user/aarch64: Do not allow duplicate or short sve records

In parse_user_sigframe, the kernel rejects duplicate sve records, or records that are smaller than the header. We were silently allowing these cases to pass, dropping the record. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 5 - 1 file chang

[PATCH v6 31/45] target/arm: Reset streaming sve state on exception boundaries

We can handle both exception entry and exception return by hooking into aarch64_sve_change_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/ar

[PATCH v6 40/45] linux-user/aarch64: Implement SME signal handling

Set the SM bit in the SVE record on signal delivery, create the ZA record. Restore SM and ZA state according to the records present on return. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 167 +--- 1 file changed,

[RISU PATCH v4 01/29] Use bool for tracing variables

Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- risu.h| 3 ++- reginfo.c | 2 +- risu.c| 8 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/risu.h b/risu.h index 8d2d646..e2b4508 100644 --- a/risu.h +++ b/risu.h @@ -17,6 +

[PATCH v6 29/45] target/arm: Implement REVD

This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 ++ target/arm/sve.decode | 1 + target/arm/sve_helper.c| 16

[PATCH v6 32/45] target/arm: Enable SME for -cpu max

Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 4 target/arm/cpu64.c| 1

[RISU PATCH v4 00/29] risu cleanups and improvements

If you can imagine, v3 was back in 2020: https://lore.kernel.org/qemu-devel/20200522023440.26261-1-richard.hender...@linaro.org/ I've refreshed that, not that risu has changed much in that time, and then also added support for SME to aarch64, i.e. SVCR and ZA storage are now present in the reginfo

[PATCH v6 30/45] target/arm: Implement SCLAMP, UCLAMP

This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 18 +++ target/arm/sve.decode | 5 ++ target/arm/translate-sve.c | 102

[PATCH v6 26/45] target/arm: Implement FMOPA, FMOPS (widening)

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 2 ++ target/arm/sme.decode | 1 + target/arm/sme_helper.c| 74 ++ target/arm/translate-sme.c | 1 + 4 files changed, 78 insertions(+) diff --git a/target/arm/helper-sme.h b/target/a

[PATCH v6 39/45] linux-user/aarch64: Move sve record checks into restore

Move the checks out of the parsing loop and into the restore function. This more closely mirrors the code structure in the kernel, and is slightly clearer. Reject rather than silently skip incorrect VL and SVE record sizes, bringing our checks in to line with those the kernel does. Reviewed-by:

[PATCH v6 23/45] target/arm: Implement SME ADDHA, ADDVA

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 5 +++ target/arm/sme.decode | 11 + target/arm/sme_helper.c| 90 ++ target/arm/translate-sme.c | 31 + 4 files changed, 137 insertions(+) d

[PATCH v6 21/45] target/arm: Export unpredicated ld/st from translate-sve.c

Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 3 +++ target/arm/translate-sve.c | 48 -- 2 fi

[PATCH v6 22/45] target/arm: Implement SME LDR, STR

We can reuse the SVE functions for LDR and STR, passing in the base of the ZA vector and a zero offset. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme.decode | 7 +++ target/arm/translate-sme.c | 24 2 files changed, 31 insertio

[PATCH v6 20/45] target/arm: Implement SME LD1, ST1

We cannot reuse the SVE functions for LD[1-4] and ST[1-4], because those functions accept only a Zreg register number. For SME, we want to pass a pointer into ZA storage. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 82 + target/arm/sme.decod

[PATCH v6 38/45] linux-user/aarch64: Verify extra record lock succeeded

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8fbe98d72f..9ff79da4be 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarc

[PATCH v4 00/12] Improve reliability of VM tests

Note: patches 10-12 are included for testing simplicity, they shouldn't be merged. They will be included in a forthcoming block PR. V4: - Addressed concern by Marc-Andre in patch 01. - Squashed Ubuntu patches (rth) This patch series attempts to improve the reliability of several of the VM test t

[PATCH v6 18/45] target/arm: Implement SME ZERO

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Fix ZA[] comment in helper_sme_zero. --- target/arm/helper-sme.h| 2 ++ target/arm/sme.decode | 4 target/arm/sme_helper.c| 25 + target/arm/translate-sme.c | 13 + 4 files

[PATCH v6 28/45] target/arm: Implement PSEL

This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve.decode | 20 + target/arm/translate-sve.c | 57

[PATCH v6 19/45] target/arm: Implement SME MOVA

We can reuse the SVE functions for implementing moves to/from horizontal tile slices, but we need new ones for moves to/from vertical tile slices. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 12 +++ target/arm/helper-sve.h| 2 + target/arm

[PATCH v6 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL

These prctl set the Streaming SVE vector length, which may be completely different from the Normal SVE vector length. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 54 +++ linux-user/syscall.c | 16 ++

[PATCH v6 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL

These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Add streaming_{vec,pred}_reg_size. --- target/arm/translate-a64.h | 12 target/arm/sve.decode

[PATCH v6 27/45] target/arm: Implement SME integer outer product

This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 16 target/arm/sme.decode | 10 + target/arm/sme_helper.c| 82 ++ target/arm/tr

[PATCH v6 15/45] target/arm: Add SME enablement checks

These functions will be used to verify that the cpu is in the correct state for a given instruction. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 21 + target/arm/translate-a64.c | 34 ++ 2 files

[PATCH v6 24/45] target/arm: Implement FMOPA, FMOPS (non-widening)

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 5 +++ target/arm/sme.decode | 9 + target/arm/sme_helper.c| 69 ++ target/arm/translate-sme.c | 32 ++ 4 files changed, 115 insertions(+) diff --git a/target/arm/

[PATCH v6 16/45] target/arm: Handle SME in sve_access_check

The pseudocode for CheckSVEEnabled gains a check for Streaming SVE mode, and for SME present but SVE absent. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 22 -- 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/tar

[PATCH v6 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return

Fold the return value setting into the goto, so each point of failure need not do both. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 26 +++--- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/linux-user/aarch64

[PATCH v6 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions

[PATCH v6 14/45] target/arm: Mark LD1RO as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletion

[PATCH v6 25/45] target/arm: Implement BFMOPA, BFMOPS

Signed-off-by: Richard Henderson --- target/arm/helper-sme.h| 2 ++ target/arm/sme.decode | 2 ++ target/arm/sme_helper.c| 56 ++ target/arm/translate-sme.c | 30 4 files changed, 90 insertions(+) diff --git a/target/arm/hel

[PATCH v6 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 15 +++ 2 files changed, 11 insertion

[PATCH v6 12/45] target/arm: Mark gather prefetch as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. In this case, introduce PRF_ns (prefetch non-streaming) to handle the checks. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 ---

[PATCH v6 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 12 ++-- 2 files changed, 6 insertions(+),

[PATCH v6 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 22 -- 2 files changed, 12 in

[PATCH v6 11/45] target/arm: Mark gather/scatter load/store as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 9 - target/arm/translate-sve.c | 6 ++ 2 files changed, 6 insertions(+),

[PATCH v6 04/45] target/arm: Mark ADR as non-streaming

Mark ADR as a non-streaming instruction, which should trap if full a64 support is not enabled in streaming mode. Removing entries from sme-fa64.decode is an easy way to see what remains to be done. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 7 +

[PATCH v6 10/45] target/arm: Mark string/histo/crypto as non-streaming

Mark these as non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 35 ++- 2 files chang

[PATCH v6 00/45] target/arm: Scalable Matrix Extension

Changes for v6: * Some sub-word big-endian addressing fixups (pmm). * Logic errors for BFMOPA/FMOPA (pmm). * Fix for PR_SME_SET_VL hflags rebuild. r~ Richard Henderson (45): target/arm: Handle SME in aarch64_cpu_dump_state target/arm: Add infrastructure for disas_sme target/arm: Trap

[PATCH v6 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 9 ++--- 2 files changed, 6 insertions(+), 5 de

[PATCH v6 07/45] target/arm: Mark PMULL, FMMLA as non-streaming

Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 24 +++- 2 files changed, 15 i

[PATCH v6 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active

This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought

[PATCH v6 01/45] target/arm: Handle SME in aarch64_cpu_dump_state

Dump SVCR, plus use the correct access check for Streaming Mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae6dca2f01..9c58be8b1

[PATCH v6 02/45] target/arm: Add infrastructure for disas_sme

This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 + target/arm/sme.decode | 20 target/arm/translate-a64.c |

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