The skiboot sources are licensed under the Apache license, so we don't
have to include them in our tarball as long as we continue to distribute
the skiboot license information in our release tarball.
Signed-off-by: Thomas Huth
---
scripts/make-release | 15 ++-
1 file changed, 14 ins
These files are of no use in a normal tarball and thus should not
be included here.
Signed-off-by: Thomas Huth
---
scripts/make-release | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/scripts/make-release b/scripts/make-release
index 176304f30b..61c0fd0bfb 100755
--- a/scr
The edk2 sources are bigger than the sources of QEMU - so they double the
size of our release tarballs if we include them. Fortunately, edk2 has a
permissive license, so there is no need for us to do this as long as we
continue to distribute the edk2 license information in our release tarball.
Sig
Our release tarballs are huge - qemu-7.0.0.tar.xz has a size of 119 MiB.
If you look at the contents, more than half of the size is used for the
edk2 sources that we ship along to provide the sources for the firmware
binaries, too. This feels very wrong, why do we urge users to download
such huge t
On Fri, Jul 1, 2022 at 10:05 PM Peter Maydell wrote:
>
> On Wed, 8 Jun 2022 at 09:17, Jason Wang wrote:
> >
> > On Tue, May 31, 2022 at 1:40 PM Zhang, Chen wrote:
> > >
> > >
> > >
> > > > -Original Message-
> > > > From: Qemu-devel > > > bounces+chen.zhang=intel@nongnu.org> On Beha
On Sat, Jul 02 2022, Thomas Huth wrote:
> On 28/06/2022 15.21, Cornelia Huck wrote:
>> On Tue, Jun 28 2022, Thomas Huth wrote:
>>
>>> Use VIRTIO_DASD_BLOCK_SIZE instead of the magic value 4096.
>>>
>>> Signed-off-by: Thomas Huth
>>> ---
>>> pc-bios/s390-ccw/virtio.h| 1 +
>>> pc-bio
Leonardo Bras writes:
> Signed-off-by: Leonardo Bras
> ---
> qapi/migration.json | 5 -
> migration/migration.c | 1 +
> monitor/hmp-cmds.c| 4
> 3 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/qapi/migration.json b/qapi/migration.json
> index 7102e474a6..925f009
On 2022/7/4 下午1:18, Richard Henderson wrote:
On 7/1/22 15:04, Xiaojuan Yang wrote:
By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.
Is it a typo in the manual that says "2VS", i.e. multiplication?
On 7/4/22 09:27, gaosong wrote:
Hi, Richard
On 2022/7/3 下午4:59, Richard Henderson wrote:
Hi. This is Song Gao's v20 [1], with patch 2 extensively rewritten
so that it handles lock_user properly. It compiles, but I need
to update the docker image we produced last year so that I can
properly te
On 7/1/22 15:03, Xiaojuan Yang wrote:
This series fix some bugs for LoongArch virt machine. Including
RTC device emulation, ECFG reg emulation, timer clear function,
and IPI device function, etc.
Xiaojuan Yang (11):
hw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch writing function
hw/rt
On 7/1/22 15:04, Xiaojuan Yang wrote:
By the document of ipi mailsend device, byte is written only when the mask bit
is 0. The original code discards mask bit and overwrite the data always, this
patch fixes the issue.
Signed-off-by: Xiaojuan Yang
---
hw/intc/loongarch_ipi.c | 45 +
On 7/1/22 15:04, Xiaojuan Yang wrote:
+static const MemoryRegionOps loongarch_ipi64_ops = {
+.write = loongarch_ipi_writeq,
+.impl.min_access_size = 8,
+.impl.max_access_size = 8,
+.valid.min_access_size = 4,
+.valid.max_access_size = 8,
+.endianness = DEVICE_LITTLE_ENDIAN
On 7/1/22 15:04, Xiaojuan Yang wrote:
By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.
Is it a typo in the manual that says "2VS", i.e. multiplication?
If so,
Reviewed-by: Richard Henderson
r~
On 7/1/22 08:37, Mao Bibo wrote:
Loongarch pch msi intc connects to extioi controller, the range of irq number
is 64-255. Here adds irqbase property for loongarch pch msi controller, we can
get irq offset from view of pch_msi controller with the method:
msi vector (from view of upper extioi in
On 7/1/22 15:04, Xiaojuan Yang wrote:
Fix 'calculate' spelling errors.
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
r~
On 7/1/22 15:04, Xiaojuan Yang wrote:
Use pointer as arguments in toy_time_to_val() instead of struct tm.
Signed-off-by: Xiaojuan Yang
---
hw/rtc/ls7a_rtc.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson
r~
On 7/1/22 15:04, Xiaojuan Yang wrote:
There is such error info when running linux kernel:
tcg_handle_interrupt: assertion failed: (qemu_mutex_iothread_locked()).
calling stack:
#0 in raise () at /lib64/libc.so.6
#1 in abort () at /lib64/libc.so.6
#2 in g_assertion_message
On 7/1/22 15:03, Xiaojuan Yang wrote:
Replace qemu_irq_pulse with qemu_irq_raise in ls7a_timer_cb function
to keep consistent with hardware behavior when raise irq.
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
r~
On 7/1/22 15:04, Xiaojuan Yang wrote:
Fix ls7a rtc enable and disable function. When rtc disabled, it do
not support to read or write, but the real time is still continue,
so we need not neither save the time nor update the rtc offset.
Signed-off-by: Xiaojuan Yang
---
hw/rtc/ls7a_rtc.c | 60 ++
On 7/1/22 15:03, Xiaojuan Yang wrote:
1. Initialize the tm struct in toymatch_write() and ls7a_toy_start() to
fix uninitialized bugs.
2. Fix toymatch_val_to_time function. By the document, when we calculate
the expiration year, we should first get current year, and replace the
0-5 bit
On 7/1/22 15:03, Xiaojuan Yang wrote:
Remove the unimplemented device when realized ls7a RTC, as it is not uesd.
Signed-off-by: Xiaojuan Yang
---
hw/rtc/ls7a_rtc.c | 1 -
1 file changed, 1 deletion(-)
Reviewed-by: Richard Henderson
r~
Laurent Vivier writes:
> On 30/06/2022 11:28, Dr. David Alan Gilbert wrote:
>> * Laurent Vivier (lviv...@redhat.com) wrote:
>>> Signed-off-by: Laurent Vivier
>>> Reviewed-by: Stefano Brivio
>>> ---
>>> net/stream.c| 106 +---
>>> qemu-options.h
Laurent Vivier writes:
> On 29/06/2022 13:26, Markus Armbruster wrote:
>> Laurent Vivier writes:
>>
>>> Format a string URI from a SocketAddress.
>>>
>>> Original code from hmp-cmds.c:SocketAddress_to_str()
>>>
>>> Replace 'tcp:' by 'inet:' (because 'inet' can be also 'udp').
>>
>> This one's
Peter Maydell writes:
> On Fri, 15 Oct 2021 at 16:01, Kevin Wolf wrote:
>> QDicts are both what QMP natively uses and what the keyval parser
>> produces. Going through QemuOpts isn't useful for either one, so switch
>> the main device creation function to QDicts. By sharing more code with
>> the
Hi, Richard
On 2022/7/3 下午4:59, Richard Henderson wrote:
Hi. This is Song Gao's v20 [1], with patch 2 extensively rewritten
so that it handles lock_user properly. It compiles, but I need
to update the docker image we produced last year so that I can
properly test this.
In the meantime, Song,
at 12:04 AM, Keith Busch wrote:
> On Thu, Jun 30, 2022 at 11:22:31AM +0800, Jinhao Fan wrote:
>> +static int nvme_init_sq_ioeventfd(NvmeSQueue *sq)
>> +{
>> +NvmeCtrl *n = sq->ctrl;
>> +uint16_t offset = sq->sqid << 3;
>> +int ret;
>> +
>> +ret = event_notifier_init(&sq->notifier,
Add property "ioeventfd" which is enabled by default. When this is
enabled, updates on the doorbell registers will cause KVM to signal
an event to the QEMU main loop to handle the doorbell updates.
Therefore, instead of letting the vcpu thread run both guest VM and
IO emulation, we now use the main
On Mon, Jul 4, 2022 at 2:59 AM Stafford Horne wrote:
>
> Add an endianness property to allow configuring the RTC as either
> native, little or big endian.
>
> Cc: Laurent Vivier
> Signed-off-by: Stafford Horne
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> hw/rtc/goldfish_
A vCPU thread always reaches 100% utilization when:
- guest uses idle=poll
- disable HLT vm-exit
- enable MWAIT
Add new guest agent command 'guest-get-cpustats' to get guest CPU
statistics, we can know the guest workload and how busy the CPU is.
Signed-off-by: zhenwei pi
---
qga/commands-posix.
v1 -> v2:
- Konstantin & Marc-André pointed out that the structure 'GuestCpuStats'
is too *linux style*, so re-define it to 'GuestLinuxCpuStats', and use
an union type of 'GuestCpuStats'.
- Modify comment info from 'man proc', also add linux version infomation.
- Test sscanf return value by '
On 7/4/22 10:17, Alistair Francis wrote:
> On Thu, Jun 30, 2022 at 4:13 PM Anup Patel wrote:
>> We should write transformed instruction encoding of the trapped
>> instruction in [m|h]tinst CSR at time of taking trap as defined
>> by the RISC-V privileged specification v1.12.
>>
>> Reviewed-by: Ali
On Thu, Jun 30, 2022 at 4:13 PM Anup Patel wrote:
>
> We should write transformed instruction encoding of the trapped
> instruction in [m|h]tinst CSR at time of taking trap as defined
> by the RISC-V privileged specification v1.12.
>
> Reviewed-by: Alistair Francis
> Signed-off-by: Anup Patel
@
On Thu, Jun 23, 2022 at 10:47 PM Eric Blake wrote:
> I did not get through all of the callers (you are right, there ARE a
> lot), but the ones I checked, particularly in block/qcow2-*.c, appear
> to handle -EIO just fine.
>
> I did notice, however, that qcow2-bitmap.c:free_bitmap_clusters()
> retu
On Sat, Jul 2, 2022 at 3:12 PM Paolo Bonzini wrote:
> Alberto, does this need a rebase?
This applies cleanly on "[PATCH v5 00/10] Implement
bdrv_{pread,pwrite,pwrite_sync,pwrite_zeroes}() using
generated_co_wrapper" [1], which applies cleanly to master.
Alberto
[1]
https://lore.kernel.org/qemu
On Sat, Jul 2, 2022 at 3:13 PM Paolo Bonzini wrote:
> These functions should be coroutine_fn (all coroutine entry points
> should be).
Thanks, I see now that you fixed this in [1].
Alberto
[1] https://patchew.org/QEMU/20220509103019.215041-1-pbonz...@redhat.com/
Signed-off-by: Stafford Horne
---
docs/system/openrisc/cpu-features.rst | 15 ++
docs/system/openrisc/emulation.rst| 17 +++
docs/system/openrisc/or1k-sim.rst | 43
docs/system/openrisc/virt.rst | 50 +++
docs/system/target-openrisc.rst
From: "Jason A. Donenfeld"
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.
Cc: Stafford Horne
Signed-off-by: Jason
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Signed-off-by: Stafford Horne
---
configs/targets/or1k-softmmu.mak | 1 +
hw/openrisc/cputimer.c | 17 +++
When running SMP systems we sometimes were seeing lockups where
IPI interrupts were being raised by never handled.
This looks to be caused by 2 issues in the openrisc interrupt handling
logic.
1. After clearing an interrupt the openrisc_cpu_set_irq handler will
always clear PICSR. This is n
This patch adds the OpenRISC virtual machine 'virt' for OpenRISC. This
platform allows for a convenient CI platform for toolchain, software
ports and the OpenRISC linux kernel port.
Much of this has been sourced from the m68k and riscv virt platforms.
The platform provides:
- OpenRISC SMP with
The last_clk time was initialized at zero, this means when we calculate
the first delta we will calculate 0 vs current time which could cause
unnecessary hops.
Initialize last_clk to the qemu clock on initialization.
Signed-off-by: Stafford Horne
---
hw/openrisc/cputimer.c | 1 +
1 file changed
When we are tracing it's helpful to know which CPU's are getting
interrupted, att that detail to the log line.
Signed-off-by: Stafford Horne
---
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interr
This is mostly borrowed from xtensa and riscv as examples. The
create_pcie_irq_map swizzle function is almost and exact copy
but here we use a single cell interrupt, possibly we can make
this generic.
Signed-off-by: Stafford Horne
---
hw/openrisc/Kconfig | 3 +
hw/openrisc/virt.c | 160 +
Add an endianness property to allow configuring the RTC as either
native, little or big endian.
Cc: Laurent Vivier
Signed-off-by: Stafford Horne
---
hw/rtc/goldfish_rtc.c | 46 ---
include/hw/rtc/goldfish_rtc.h | 2 ++
2 files changed, 39 insertions(+),
Hello,
This is the OpenRISC Virtual Machine plaform which we are now using for OpenRISC
CI such as the wireguard testing that Jason has been working on.
The first few patches help get OpenRISC QEMU ready for the virtual machine.
There is one bug fix for GDB debugging there too.
Next we have the
In commit f0655423ca ("target/openrisc: Reorg tlb lookup") data and
instruction TLB reads were combined. This, broke debugger reads where
we first tried to map using the data tlb then fall back to the
instruction tlb.
This patch replicates this logic by first requesting a PAGE_READ
protection map
These will be shared with the virt platform.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/openrisc/boot.c | 117 +
hw/openrisc/meson.build| 1 +
hw/openrisc/openrisc_sim.c | 106 ++---
include/h
Commit 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations")
changed core type of MPC8555 and MPC8560 from e500v1 to e500v2.
But both MPC8555 and MPC8560 have just e500v1 cores, there are no features
of e500v2 cores. It can be verified by reading NXP documentations:
https://www.nx
From: Song Gao
Some functions and member of the structure are different with softmmu-mode
So we need adjust them to support user-mode.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220624031049.1716097-12-gaos...@loongson.cn>
Signed-off-by:
From: Song Gao
We can use CSR_BADV to replace badaddr.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220624031049.1716097-8-gaos...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/cpu.h | 2 --
target/loongarch/gdbs
From: Song Gao
This includes:
- sockbits.h
- target_errno_defs.h
- target_fcntl.h
- termbits.h
- target_resource.h
- target_structs.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: WANG Xuerui
Message-Id:
On 7/3/22 14:27, Peter Maydell wrote:
On Sat, 2 Jul 2022 at 15:19, Richard Henderson
wrote:
On 7/1/22 01:11, Peter Maydell wrote:
+static inline bool isar_feature_any_doublelock(const ARMISARegisters *id)
+{
+/*
+ * We can't just OR together the aa32 and aa64 checks, because
+ * i
Hi. This is Song Gao's v20 [1], with patch 2 extensively rewritten
so that it handles lock_user properly. It compiles, but I need
to update the docker image we produced last year so that I can
properly test this.
In the meantime, Song, can you please test this?
r~
[1]
https://lore.kernel.org
From: Song Gao
Add linux-user emulation introduction
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220624031049.1716097-14-gaos...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/README | 39
From: Song Gao
loongarch_cpu_do_interrupt() should update CSR_BADV for some EXCCODE.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220624031049.1716097-9-gaos...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/cpu.c | 1
Perform the atomic update for hardware management of the
access flag and the dirty bit.
A limitation of the implementation so far is that the
page table must itself be writable. This is allowed because
it is CONSTRAINED UNPREDICTABLE whether any atomic update
happens at all. Any implementation i
From: Song Gao
This patch adds loongarch64 linux-user default configs file.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: WANG Xuerui
Message-Id: <20220624031049.1716097-13-gaos...@loongson.cn>
Signed-off-by: Richard Henderson
---
configs/
From: Song Gao
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220624031049.1716097-5-gaos...@loongson.cn>
Signed-off-by: Richard Henderson
---
linux-user/loongarch64/syscall_nr.h | 312 ++
Always overriding fi->type was incorrect, as we would not
properly propagate the fault type from S1_ptw_translate,
or arm_ldq_ptw. Simplify things by providing a new label
for reporting a translation fault. For other faults, store
into fi directly.
Signed-off-by: Richard Henderson
---
target/a
From: Song Gao
Raise EXCCODE_BCE instead of EXCCODE_ADEM for helper_asrtle_d/asrtgt_d.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220624031049.1716097-10-gaos...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/cpu.c
The unconditional loop was used both to iterate over levels
and to control parsing of attributes. Use an explicit goto
in both cases.
While this appears less clean for iterating over levels, we
will need to jump back into the middle of this loop for
atomic updates, which is even uglier.
Signed-o
From: Song Gao
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220624031049.1716097-4-gaos...@loongson.cn>
Signed-off-by: Richard Henderson
---
linux-user/loongarch64/target_elf.h | 12
linux-user/el
From: Song Gao
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220624031049.1716097-7-gaos...@loongson.cn>
Signed-off-by: Richard Henderson
---
scripts/qemu-binfmt-conf.sh | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --gi
From: Song Gao
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Message-Id: <20220624031049.1716097-3-gaos...@loongson.cn>
[rth: Rework extctx frame allocation and locking;
Properly read/write fcc from signal frame.]
Signed-off-by: Richard Henderson
---
linux-user/loongarch64/target
This fault type is to be used with FEAT_HAFDBS when
the guest enables hw updates, but places the tables
in memory where atomic updates are unsupported.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/internals.h b/tar
The return type of the functions is already bool, but in a few
instances we used an integer type with the return statement.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index
On Sat, 2 Jul 2022 at 15:19, Richard Henderson
wrote:
>
> On 7/1/22 01:11, Peter Maydell wrote:
> > +static inline bool isar_feature_any_doublelock(const ARMISARegisters *id)
> > +{
> > +/*
> > + * We can't just OR together the aa32 and aa64 checks, because
> > + * if there is no AArch
Both GP and DBM are in the upper attribute block.
Extend the computation of attrs to include them,
then simplify the setting of guarded.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/p
So far, limit the change to S1_ptw_translate, arm_ldl_ptw,
and arm_ldq_ptw. Use probe_access_extra to find the host
address, and if so use a host load. If the probe fails,
we've got our fault info already. On the off chance that
page tables are not in RAM, continue to use the
address_space_ld* f
On 7/1/22 15:41, Peter Maydell wrote:
On Tue, 28 Jun 2022 at 05:25, Richard Henderson
wrote:
Dump SVCR, plus use the correct access check for Streaming Mode.
Signed-off-by: Richard Henderson
---
Reviewed-by: Peter Maydell
Dumping the actual ZA storage seems like it would be more
annoying
We had been marking this ARM_MMU_IDX_NOTLB, move it to a real tlb.
Flush the tlb when invalidating stage 1+2 translations.
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 20 +++-
target/arm/helper.c| 4 +++-
3 files changed, 15
Separate S1 translation from the actual lookup.
Will enable lpae hardware updates.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 83 +---
1 file changed, 44 insertions(+), 39 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
inde
Hoist this test out of arm_ld[lq]_ptw into S1_ptw_translate.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 32937ec7db..b5105a2e92 100644
--- a/target/arm/ptw.c
+++
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 2 ++
target/arm/helper.c| 8 +++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1bbe4d950e..f2a421972e 100644
--- a/target/arm/internals.h
+++ b/target/arm/
Not yet used, but add mmu indexes for 1-1 mapping
to physical addresses.
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 4
target/arm/ptw.c | 9 +
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu-param.
From: Song Gao
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220624031049.1716097-11-gaos...@loongson.cn>
Signed-off-by: Richard Henderson
---
target/loongarch/cpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/loongarch/cpu.c
Hoist the computation of the mmu_idx for the ptw up to
get_phys_addr_with_secure and get_phys_addr_twostage.
This removes the duplicate check for stage2 disabled
from the middle of the walk, performing it only once.
Pass ptw_idx through get_phys_addr_{v5,v6,lpae} and
arm_{ldl,ldq}_ptw.
Signed-off
From: Song Gao
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Message-Id: <20220624031049.1716097-6-gaos...@loongson.cn>
Signed-off-by: Richard Henderson
---
linux-user/loongarch64/target_cpu.h | 34 ++
linux-user/loongarch64/cpu_loop.c | 96 +++
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 138 +--
1 file changed, 74 insertions(+), 64 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 43a82c3c7f..0f4b9b0166 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -22
Consolidate the results of S1_ptw_translate in one struct.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 60
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 6eb61849d3..32937ec7db
If stage2 is disabled, we do not need to adjust mmu_idx.
Below, we'll use get_phys_addr_lpae and not recurse.
Adjust regime_is_user so that it can be used for E10_0.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/
This has been broken since arm_hcr_el2_eff gained a check for
"el2 enabled" for Secure EL2.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index a760ab86c5..43a82c3c7f 100644
--
Use a switch. Do not apply memattr or shareability for Stage2
translations. Make sure to apply HCR_{DC,DCT} only to Regime_EL10,
per the pseudocode in AArch64.S1DisabledOutput.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 115 +++
1 file ch
On 6/15/2022 10:52 PM, Steve Sistare wrote:
> Enable vfio-pci devices to be saved and restored across an exec restart
> of qemu.
>
> At vfio creation time, save the value of vfio container, group, and device
> descriptors in cpr state.
>
> In the container pre_save handler, suspend the use of
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 182 +--
1 file changed, 96 insertions(+), 86 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 84d72ac249..993f015904 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -24
These subroutines did not need ENV for anything except
retrieving the effective value of HCR anyway.
We have computed the effective value of HCR in the callers,
and this will be especially important for interpreting HCR
in a non-current security state.
Signed-off-by: Richard Henderson
---
targe
Leave the upper and lower attributes in the place they originate
from in the descriptor. Shifting them around is confusing, since
one cannot read the bit numbers out of the manual. Also, new
attributes have been added which would alter the shifts.
Signed-off-by: Richard Henderson
---
target/ar
Rename the argument to is_secure_ptr, and introduce a
local variable is_secure with the value. We only write
back to the pointer toward the end of the function.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-
If stage2 translation is disabled, E1&0 translation is
just a single stage. Use the complete single stage path
rather than breaking out of the middle of the two stage path.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
di
Pass the correct stage2 mmu_idx to regime_translation_disabled,
which we computed afterward.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 12288ac365..12b6c2c98b 100644
---
Use a switch on mmu_idx for the a-profile indexes, instead of
three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/target/arm/p
The MMFR1 field may indicate support for hardware update of
access flag alone, or access flag and dirty bit.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e5e3084ec9..6484abcf1f 1006
This is the last use of regime_is_secure; remove it
entirely before changing the layout of ARMMMUIdx.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 42
target/arm/ptw.c | 44 --
2 files changed
Use get_phys_addr_with_secure directly. This is the one place
where the value of is_secure may not equal arm_is_secure(env).
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/ta
Remove the use of regime_is_secure from v7m_read_half_insn.
As it happens, both callers pass true, but that is a detail
of v7m_handle_execute_nsc we need not expose to the callee.
Signed-off-by: Richard Henderson
---
target/arm/m_helper.c | 9 -
1 file changed, 4 insertions(+), 5 deletio
Remove the use of regime_is_secure from arm_tr_init_disas_context.
Instead, provide the value of v8m_secure directly from tb_flags.
Rather than use regime_is_secure, use the env->v7m.secure directly,
as per arm_mmu_idx_el.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
targe
Remove the use of regime_is_secure from regime_translation_disabled.
This fixes a bug in S1_ptw_translate and get_phys_addr where we had
passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if
Stage2 is disabled, affecting FEAT_SEL2.
Signed-off-by: Richard Henderson
---
target/arm/pt
This value is unused.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 12b6c2c98b..93c533e60d 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2168,8 +2168,7 @@ static
Retain the existing get_phys_addr interface using
the security state derived from mmu_idx.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 6 ++
target/arm/ptw.c | 21 +++--
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/target/arm/intern
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 11 +--
target/arm/m_helper.c | 16 +++-
target/arm/ptw.c | 20 +---
3 files changed, 21 insertions(+), 26 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 7d08
1 - 100 of 132 matches
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