On 7/3/22 05:42, Alistair Francis wrote:
From: Alistair Francis
The following changes since commit d495e432c04a6394126c35cf96517749708b410f:
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into
staging (2022-06-30 22:04:12 +0530)
are available in the Git repository at
On 7/2/22 19:26, Warner Losh wrote:
The following changes since commit d495e432c04a6394126c35cf96517749708b410f:
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into
staging (2022-06-30 22:04:12 +0530)
are available in the Git repository at:
ssh://g...@github.com/qe
From: Anup Patel
Based on architecture review committee feedback, the [m|s|vs]seteienum,
[m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are
removed in the latest AIA draft v0.3.0 specification.
(Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31)
These CSRs w
From: Alistair Francis
We previously stored the device tree at a 16MB alignment from the end of
memory (or 3GB). This means we need at least 16MB of memory to be able
to do this. We don't actually need the FDT to be 16MB aligned, so let's
drop it down to 2MB so that we can support systems with le
From: Alistair Francis
The Ibex CPU supports version 1.11 of the priv spec [1], so let's
correct that in QEMU as well.
1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-Id: <20220629233102.275181-3-alistair.
From: Alistair Francis
There is nothing in the RISC-V spec that mandates version 1.12 is
required for ePMP and there is currently hardware [1] that implements
ePMP (a draft version though) with the 1.11 priv spec.
1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
Fixes:
From: Atish Patra
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
Message-Id: <20220620231603.2547260-6-ati...@rivosinc.com>
Signe
From: Atish Patra
mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.
Support mcycle/minstret
From: Anup Patel
The latest AIA draft v0.3.0 defines a relatively simpler scheme for
default priority assignments where:
1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use
and have implementation specific default priority.
2) remaining local interrupts 0 to 23 and 32 to 47 h
From: Atish Patra
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair Franc
From: Atish Patra
With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Atish Patra
Signed-off-
From: Atish Patra
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as wel
From: Nicolas Pitre
For a TOR entry to match, the stard address must be lower than the end
address. Normally this is always the case, but correct code might still
run into the following scenario:
Initial state:
pmpaddr3 = 0x2000 pmp3cfg = OFF
pmpaddr4 = 0x3000 pmp4cf
From: Atish Patra
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many programmable counters sho
From: Víctor Colombo
Commit 57c108b8646 introduced gen_set_gpri(), which already contains
a check for if the destination register is 'zero'. The check in auipc
and lui are then redundant. This patch removes those checks.
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Reviewed-by:
From: Atish Patra
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by:
From: Anup Patel
The minimum priv spec versino for mcountinhibit to v1.11 so that it
is not available for v1.10 (or lower).
Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Message-Id: <20220628101737.786681-3-a
From: Richard Henderson
The function doesn't set mtval, it sets badaddr. Move the set
of badaddr directly into gen_exception_inst_addr_mis and use
generate_exception.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220604231004.49990-3-richard.hender...@linaro.org
From: Anup Patel
The riscv_cpu_realize() sets priv spec version to v1.12 when it is
when "env->priv_ver == 0" (i.e. default v1.10) because the enum
value of priv spec v1.10 is zero.
Due to above issue, the sifive_u machine will see priv spec v1.12
instead of priv spec v1.10.
To fix this issue,
From: Atish Patra
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by:
From: Richard Henderson
While we set env->bins when unwinding for ILLEGAL_INST,
from e.g. csrrw, we weren't setting it for immediately
illegal instructions.
Add a testcase for mtval via both exception paths.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
Signed-off-by: Richard Hen
From: Richard Henderson
The set of instructions that require decode_save_opc for
unwinding is really fairly small -- only insns that can
raise ILLEGAL_INSN at runtime. This includes CSR, anything
that uses a *new* fp rounding mode, and many privileged insns.
Since unwind info is stored as the d
From: Richard Henderson
The function doesn't set mtval, it sets badaddr. Move the set
of badaddr directly into gen_exception_inst_addr_mis and use
generate_exception.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220604231004.49990-3-richard.hender...@linaro.org
From: Alistair Francis
The following changes since commit d495e432c04a6394126c35cf96517749708b410f:
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into
staging (2022-06-30 22:04:12 +0530)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tag
On Sun, Jul 3, 2022 at 10:09 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> The following changes since commit d495e432c04a6394126c35cf96517749708b410f:
>
> Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into
> staging (2022-06-30 22:04:12 +0530)
>
> are availa
From: Nicolas Pitre
For a TOR entry to match, the stard address must be lower than the end
address. Normally this is always the case, but correct code might still
run into the following scenario:
Initial state:
pmpaddr3 = 0x2000 pmp3cfg = OFF
pmpaddr4 = 0x3000 pmp4cf
From: Richard Henderson
The set of instructions that require decode_save_opc for
unwinding is really fairly small -- only insns that can
raise ILLEGAL_INSN at runtime. This includes CSR, anything
that uses a *new* fp rounding mode, and many privileged insns.
Since unwind info is stored as the d
From: Víctor Colombo
Commit 57c108b8646 introduced gen_set_gpri(), which already contains
a check for if the destination register is 'zero'. The check in auipc
and lui are then redundant. This patch removes those checks.
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Reviewed-by:
From: Richard Henderson
While we set env->bins when unwinding for ILLEGAL_INST,
from e.g. csrrw, we weren't setting it for immediately
illegal instructions.
Add a testcase for mtval via both exception paths.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
Signed-off-by: Richard Hen
From: Alistair Francis
The following changes since commit d495e432c04a6394126c35cf96517749708b410f:
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into
staging (2022-06-30 22:04:12 +0530)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tag
I like to build QEMU from the root source directory, rather than cd'ing
into the build directory. This code may as well include a search path
for that, so that you can run avocado tests individually without
specifying "-p qemu_bin=build/qemu-system-arm" manually.
Signed-off-by: Peter Delevoryas
-
From: Peter Delevoryas
To support multiple SoC's running simultaneously, we need a unique name for
each RAM region. DRAM is created by the machine, but SRAM is created by the
SoC, since in hardware it is part of the SoC's internals.
We need a way to uniquely identify each SRAM region though, for
On Sat, Jul 02, 2022 at 12:36:46AM -0700, Peter Delevoryas wrote:
> On Sat, Jul 02, 2022 at 12:01:48AM -0700, Peter Delevoryas wrote:
> > On Sat, Jul 02, 2022 at 08:01:14AM +0200, Cédric Le Goater wrote:
> > > On 7/1/22 20:06, Peter Delevoryas wrote:
> > > > To support multiple SoC's running simult
Reviewed-by: Akihiko Odaki
On 2022/07/02 13:43, Peter Delevoryas wrote:
I noticed this error while building QEMU on Mac OS X:
[1040/1660] Compiling Objective-C object libcommon.fa.p/ui_cocoa.m.o
../ui/cocoa.m:803:17: warning: variable 'switched_to_fullscreen' set but
not used [-Wunu
Retreieve the refresh rate of the display and reflect it with
dpy_set_ui_info() and update_displaychangelistener(), allowing the
guest and DisplayChangeListener to consume the information.
The information will be used as a hint how often the display should
be updated. For example, when we run 30 H
On 7/1/22 01:11, Peter Maydell wrote:
+static inline bool isar_feature_any_doublelock(const ARMISARegisters *id)
+{
+/*
+ * We can't just OR together the aa32 and aa64 checks, because
+ * if there is no AArch64 support the aa64 function will default
+ * to returning true for a zer
On 7/2/22 13:33, Alberto Faria wrote:
The current primary motivation for this work is enforcing rules around
block layer coroutines, which is why most of the series focuses on that.
However, the static analyzer is intended to be sufficiently generic to
satisfy other present and future QEMU static
On 7/2/22 13:33, Alberto Faria wrote:
@@ -1537,8 +1537,9 @@ static void blk_aio_read_entry(void *opaque)
QEMUIOVector *qiov = rwco->iobuf;
assert(qiov->size == acb->bytes);
-rwco->ret = blk_co_do_preadv(rwco->blk, rwco->offset, acb->bytes,
- qio
On 6/23/22 22:20, Alberto Faria wrote:
On Thu, Jun 9, 2022 at 4:27 PM Alberto Faria wrote:
Start by making the interfaces of analogous non-coroutine and coroutine
functions consistent with each other, then implement the non-coroutine
ones using generated_co_wrapper.
For the bdrv_pwrite_sync()
On 5/17/22 13:35, Alberto Faria wrote:
Adjust existing pairs of non-coroutine and coroutine functions to share
the same calling convention, and add non-coroutine/coroutine
counterparts where they don't exist.
Also make the non-coroutine versions generated_co_wrappers.
This series sits on top of
On 7/1/22 01:11, Peter Maydell wrote:
The target/arm/helper.c file is very long and is a grabbag of all
kinds of functionality. We have already a debug_helper.c which has
code for implementing architectural debug. Move the code which
defines the debug-related system registers out to this file a
In the last series, I inadvertantly didn't remove this inline, but did
all the others. Remove it for consistency.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bsd-user/bsd-file.h b/bsd-user/
On 7/1/22 01:11, Peter Maydell wrote:
The "OS Lock" in the Arm debug architecture is a way for software
to suppress debug exceptions while it is trying to power down
a CPU and save the state of the breakpoint and watchpoint
registers. In QEMU we implemented the support for writing
the OS Lock bit
On 7/1/22 01:11, Peter Maydell wrote:
Starting with v7 of the debug architecture, there are three extra
ID registers that add information on top of that provided in
DBGDIDR. These are DBGDEVID, DBGDEVID1 and DBGDEVID2. In the
v7 debug architecture, DBGDEVID is optional, present only of
s/of/if/
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 27 +++
bsd-user/freebsd/os-syscall.c | 8
2 files changed, 35 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
index c2
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 13 +
bsd-user/freebsd/os-syscall.c | 4
2 files changed, 17 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
index 065f576dfe8..108a506
These implement both the old-pre INO64 mknod variations, as well as the
now current INO64 variant. Make direct syscall calls for these older
syscalls to avloid too many dependencies.
Signed-off-by: Stacey Son
Signed-off-by: Michal Meloun
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 19 +++
bsd-user/freebsd/os-syscall.c | 8
2 files changed, 27 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
index a1c80428d9
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 32
bsd-user/freebsd/os-syscall.c | 12
2 files changed, 44 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
Signed-off-by: Stacey Son
Signed-off-by: Jung-uk Kim
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 74 +++
bsd-user/freebsd/os-syscall.c | 16
2 files changed, 90 insertions(+)
diff --git a/bsd-user/bsd-f
The following changes since commit d495e432c04a6394126c35cf96517749708b410f:
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into
staging (2022-06-30 22:04:12 +0530)
are available in the Git repository at:
ssh://g...@github.com/qemu-bsd-user/qemu-bsd-user.git
tags/bsd-
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 32
bsd-user/freebsd/os-syscall.c | 12
2 files changed, 44 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 48 +++
bsd-user/freebsd/os-syscall.c | 16
2 files changed, 64 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-fil
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 46 +++
bsd-user/freebsd/os-syscall.c | 16
2 files changed, 62 insertions(+)
diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-fil
Signed-off-by: Stacey Son
Signed-off-by: Jung-uk Kim
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-file.h | 52 +++
bsd-user/freebsd/os-syscall.c | 13 +
2 files changed, 65 insertions(+)
diff --git a/bsd-user/bsd-
On 7/1/22 01:11, Peter Maydell wrote:
Before moving debug system register helper functions to a
different file, fix the code style issues (mostly block
comment syntax) so checkpatch doesn't complain about the
code-motion patch.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 58
- improve the field extract progress
- add stand-alone check for mcuonteren when in less-privileged mode
- add check for scounteren when 'S' is enabled and current priv is PRV_U
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c | 76 ++-
On 7/2/22 03:24, Cédric Le Goater wrote:
On 6/30/22 21:42, Daniel Henrique Barboza wrote:
The function can't just return 0 whether an error happened and call it a
day. We must provide a way of letting callers know if the zero return is
legitimate or due to an error.
Add an Error pointer to k
On 6/28/22 17:55, Murilo Opsfelder Araujo wrote:
All ppc CPUs represent hardware that exists in the real world, i.e.: we
do not have a "max" CPU with all possible emulated features enabled.
Return the default CPU type for the machine because that has greater
chance of being useful as the "max"
On 6/29/22 13:28, Víctor Colombo wrote:
Hello everyone,
Set of patches containing implementations for some instructions that
were missing before. Also, moves some related instructions to
decodetree. Add mffsce test.
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
v3:
-
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 6/22/22 02:10, Alexey Kardashevskiy wrote:
The new PAPR 2.12 defines a watchdog facility managed via the new
H_WATCHDOG hypercall.
This adds H_WATCHDOG support which a proposed driver for pseries uses:
https://patchwork.ozlab
On 6/28/22 05:05, Alexey Kardashevskiy wrote:
It keeps repeating, move it to the header. This uses __builtin_ffsll() to
allow using the macros in #define.
This is not using the QEMU's FIELD macros as this would require changing
all such macros found in skiboot (the PPC PowerNV firmware).
Sig
At 2022-06-04 00:04:23, "Mayuresh Chitale" wrote:
>Accesses to henvcfg, henvcfgh and senvcfg are allowed
>only if corresponding bit in mstateen0/hstateen0 is
>enabled. Otherwise an illegal instruction trap is
>generated.
>
>Signed-off-by: Mayuresh Chitale
>---
> target/riscv/csr.c | 84 +
At 2022-06-04 00:04:22, "Mayuresh Chitale" wrote:
>Smstateen extension specifies a mechanism to close
>the potential covert channels that could cause security issues.
>
>This patch adds the CSRs defined in the specification and
>the corresponding predicates and read/write functions.
>
>Signed-off
I added this helper in the Aspeed machine file a while ago to help
initialize fuji-bmc i2c devices. This moves it to the official pca954x
file so that other files can use it.
This does something very similar to pca954x_i2c_get_bus, but I think
this is useful when you have a very complicated dts wi
These calls were found by static-analyzer.py.
Signed-off-by: Alberto Faria
---
block/block-backend.c | 2 +-
block/io.c | 10 +-
block/parallels.c | 4 ++--
block/qcow2-refcount.c | 2 +-
block/qed-table.c | 2 +-
block/qed.c| 2 +-
block/vmdk.c
When applied to a function, it advertises that it should not be called
from coroutine_fn functions.
Make generated_co_wrapper evaluate to no_coroutine_fn, as coroutine_fn
functions should instead directly call the coroutine_fn that backs the
generated_co_wrapper.
Extend static-analyzer.py's "coro
Add a static-analyzer.py check ensuring that non-coroutine_fn functions
don't perform direct calls to coroutine_fn functions.
For the few cases where this must happen, introduce an
__allow_coroutine_fn_call() macro that wraps offending calls and
overrides the static analyzer.
Signed-off-by: Alber
Extend static-analyzer.py to enforce coroutine_fn restrictions on
function pointer operations.
Invalid operations include assigning a coroutine_fn value to a
non-coroutine_fn function pointer, and invoking a coroutine_fn function
pointer from a non-coroutine_fn function.
Signed-off-by: Alberto Fa
These problems were found by static-analyzer.py. Only a few of the
reported cases were fixed.
Signed-off-by: Alberto Faria
---
include/block/block_int-common.h | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/include/block/block_int-common.h b/include/block/block_
Make some non-void static functions whose return values are ignored by
all callers return void instead.
These functions were found by the shiny new static-analyzer.py. Only a
few of the reported cases were fixed.
Signed-off-by: Alberto Faria
---
block/file-posix.c | 6 +-
block/io.c
These problems were found by static-analyzer.py. Only a few of the
reported cases were fixed.
Signed-off-by: Alberto Faria
---
block/block-backend.c | 13 -
block/copy-before-write.c | 3 ++-
block/dirty-bitmap.c | 6 --
block/iscsi.c | 3 ++-
block/qcow2.
Add a static-analyzer.py script that uses libclang's Python bindings to
provide a common framework on which arbitrary static analysis checks can
be developed and run against QEMU's code base.
As an example, a simple check is included that verifies that the return
value of static, non-void function
This series introduces a static analyzer for QEMU. It consists of a
single static-analyzer.py script that relies on libclang's Python
bindings, and provides a common framework on which arbitrary static
analysis checks can be developed and run against QEMU's code base.
Summary of the series:
- P
On Fri, Jul 01, 2022 at 12:51:06PM +0200, Gerd Hoffmann wrote:
> On Thu, Jun 23, 2022 at 11:16:39PM +0800, Hongren (Zenithal) Zheng wrote:
> > On Mon, Jun 13, 2022 at 08:12:38PM +0800, Hongren (Zenithal) Zheng wrote:
> >
> > > ---
> > > v2:
> > > * use usb_ep_get instead of recording ep_in_poi
When building tcg configure with --enable-tcg-interpreter and --enable-debug,
We may got an error:
In file included from ../tcg/tcg.c:432:
/root/code/github/soft-qemu/qemu/tcg/tci/tcg-target.c.inc: In function
'tcg_target_init':
/root/code/github/soft-qemu/qemu/tcg/tci/tcg-target.c.inc:829:9: err
Hi Richard,
Richard Henderson writes:
> Ok, version 1 didn't work, so once more with feeling.
> Can you give it a try, Sven?
This seems to work. Thanks a lot!
Regards
Sven
On Sat, Jul 02, 2022 at 12:01:48AM -0700, Peter Delevoryas wrote:
> On Sat, Jul 02, 2022 at 08:01:14AM +0200, Cédric Le Goater wrote:
> > On 7/1/22 20:06, Peter Delevoryas wrote:
> > > To support multiple SoC's running simultaneously, we need a unique name
> > > for
> > > each RAM region. DRAM is
On Sat, Jul 02, 2022 at 08:01:14AM +0200, Cédric Le Goater wrote:
> On 7/1/22 20:06, Peter Delevoryas wrote:
> > To support multiple SoC's running simultaneously, we need a unique name for
> > each RAM region. DRAM is created by the machine, but SRAM is created by the
> > SoC, since in hardware it
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