On Fri, Jul 1, 2022 at 10:32 PM Bin Meng wrote:
>
> On Thu, Jun 30, 2022 at 7:31 AM Alistair Francis
> wrote:
> >
> > From: Alistair Francis
> >
> > There is nothing in the RISC-V spec that mandates version 1.12 is
> > required for ePMP and there is currently hardware [1] that implements
> > ePM
On Sat, Jul 02, 2022 at 07:57:09AM +0200, Cédric Le Goater wrote:
> On 7/1/22 22:02, Peter Delevoryas wrote:
> > This change moves the code that connects the SoC UART's to serial_hd's
> > to the machine.
> >
> > It makes each UART a proper child member of the SoC, and then allows the
> > machine t
On 01/07/2022 17.36, Eric Farman wrote:
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
The logic of trying an final ISO or ECKD boot on virtio-block devices
is
very weird: Since the geometry hardly ever matches in
virtio_disk_is_scsi(),
virtio_blk_setup_device() always sets a "guessed" di
On 6/30/22 21:42, Daniel Henrique Barboza wrote:
The function can't just return 0 whether an error happened and call it a
day. We must provide a way of letting callers know if the zero return is
legitimate or due to an error.
Add an Error pointer to kvmppc_read_int_cpu_dt() that will be filled
w
On 28/06/2022 15.21, Cornelia Huck wrote:
On Tue, Jun 28 2022, Thomas Huth wrote:
Use VIRTIO_DASD_BLOCK_SIZE instead of the magic value 4096.
Signed-off-by: Thomas Huth
---
pc-bios/s390-ccw/virtio.h| 1 +
pc-bios/s390-ccw/virtio-blkdev.c | 2 +-
2 files changed, 2 insertions(+),
On 6/30/22 21:42, Daniel Henrique Barboza wrote:
From: jianchunfu
Add error reporting before return when opening file fails in
kvmppc_read_int_dt().
Signed-off-by: jianchunfu
[danielhb: use error_setg() instead of fprintf]
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Cédric Le Goat
On 6/30/22 21:42, Daniel Henrique Barboza wrote:
Let's put the default clock and timebase freq value in macros for better
readability. Use PPC440EP_CLOCK_FREQ as the default value of
'clock_freq' if kvmppc_get_clockfreq() throws an error.
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc
On 6/30/22 21:42, Daniel Henrique Barboza wrote:
Callers will then be able to handle any errors that might happen when
reading the clock frequency.
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/e500.c | 2 +-
hw/ppc/ppc440_bamboo.c | 2 +-
hw/ppc/sam460ex.c | 2 +-
hw/ppc
On 6/30/22 21:42, Daniel Henrique Barboza wrote:
This spares us a g_free() call. Let's also not use 'val' and return the
value of kvmppc_read_int_dt() directly.
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/kvm.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --g
When EXECUTE sets ex_value to interrupt the constructed instruction,
we implicitly disable interrupts so that the value is not corrupted.
Exit to the main loop after execution, so that we re-evaluate any
pending interrupts.
Reported-by: Sven Schnelle
Signed-off-by: Richard Henderson
---
target/
Replace this with a flag: exit_to_mainloop.
We can now control the exit for each of DISAS_TOO_MANY,
DISAS_PC_UPDATED, and DISAS_PC_CC_UPDATED, and fold in
the check for PER.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/translate.c | 21 +++--
1 file changed, 11 insertion
There is nothing to distinguish this from DISAS_TOO_MANY.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/translate.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index e38ae9ce09..a3422c0eb0 1
There is nothing to distinguish this from DISAS_NORETURN.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index fd2433d625..e38ae9ce09 100644
Ok, version 1 didn't work, so once more with feeling.
Can you give it a try, Sven?
r~
Richard Henderson (4):
target/s390x: Remove DISAS_GOTO_TB
target/s390x: Remove DISAS_PC_STALE
target/s390x: Remove DISAS_PC_STALE_NOCHAIN
target/s390x: Exit tb after executing ex_value
target/s390x/t
On 7/1/22 20:06, Peter Delevoryas wrote:
To support multiple SoC's running simultaneously, we need a unique name for
each RAM region. DRAM is created by the machine, but SRAM is created by the
SoC, since in hardware it is part of the SoC's internals.
We need a way to uniquely identify each SRAM
On 7/1/22 22:02, Peter Delevoryas wrote:
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should pres
I noticed this error while building QEMU on Mac OS X:
[1040/1660] Compiling Objective-C object libcommon.fa.p/ui_cocoa.m.o
../ui/cocoa.m:803:17: warning: variable 'switched_to_fullscreen' set but
not used [-Wunused-but-set-variable]
static bool switched_to_fullscreen = false;
I added this helper in the Aspeed machine file a while ago to help
initialize fuji-bmc i2c devices. This moves it to the official pca954x
file so that other files can use it.
This does something very similar to pca954x_i2c_get_bus, but I think
this is useful when you have a very complicated dts wi
Add to peter.mayd...@linaro.org
在 2022/7/1 11:07, Mao Bibo 写道:
> Loongarch pch msi intc connects to extioi controller, the range of irq number
> is 64-255. Here adds irqbase property for loongarch pch msi controller, we can
> get irq offset from view of pch_msi controller with the method:
> msi
On Fri, Jul 1, 2022 at 5:37 AM Thomas Huth wrote:
> On 29/06/2022 08.28, Ani Sinha wrote:
> > On Tue, Jun 28, 2022 at 11:30 PM Michael S. Tsirkin wrote:
> >> On Tue, Jun 28, 2022 at 05:15:05PM +0100, Daniel P. Berrangé wrote:
> >>> FYI, the reason much of this is intentionally NOT under the /qemu
On 7/1/22 10:34, Lucas Coutinho wrote:
Resent after rebasing and fixing conflicts with master.
Add Leandro Lupori as reviewer.
Based-on: <20220624191424.190471-1-leandro.lup...@eldorado.org.br>
Implement the following PowerISA v3.0 instuction:
slbiag: SLB Invalidate All Global X-form
Yeah,
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> The next patch is going to add more virtio-block specific code to
> virtio_blk_setup_device(), and if the virtio-scsi code is also in
> there, this is more cumbersome. And the calling function
> virtio_setup()
> in main.c looks at the device t
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should preserve backwards compatibility, but also allo
On Fri, Jul 01, 2022 at 12:56:19PM -0700, Peter Delevoryas wrote:
> This change moves the code that connects the SoC UART's to serial_hd's
> to the machine.
>
> It makes each UART a proper child member of the SoC, and then allows the
> machine to selectively initialize the chardev for each UART wi
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should preserve backwards compatibility, but also allo
Hi Mark,
On 6/29/22 14:39, Mark Cave-Ayland wrote:
> Here is the follow-on series from part 1 which completes the work to remove
> the legacy global device init functions for PS2 devices. Now that part 1 has
> been applied, the hard part to remove the PS2 function callback and argument
> has been
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> It looks nicer if we separate the run_ccw() from the IPL_assert()
> statement, and the error message should talk about "virtio device"
> instead of "block device", since this code is nowadays used for
> non-block (i.e. network) devices, too.
>
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> Feature negotiation should be done first, since some fields in the
> config area can depend on the negotiated features and thus should
> rather be read afterwards.
>
> While we're at it, also adjust the error message here a little bit
> (the
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> The virtio_assume_scsi() function is very questionable: First, it
> is only called for virtio-blk, and not for virtio-scsi, so the naming
> is already quite confusing. Second, it is called if we detected a
> "invalid" IPL disk, trying to fix i
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> The s390-ccw bios fails to boot if the boot disk is a virtio-blk
> disk with a sector size of 4096. For example:
>
> dasdfmt -b 4096 -d cdl -y -p -M quick /dev/dasdX
> fdasd -a /dev/dasdX
> install a guest onto /dev/dasdX1 using virtio-blk
To support multiple SoC's running simultaneously, we need a unique name for
each RAM region. DRAM is created by the machine, but SRAM is created by the
SoC, since in hardware it is part of the SoC's internals.
We need a way to uniquely identify each SRAM region though, for VM
migration. Since each
On Wed, Jun 29, 2022 at 7:18 PM Richard Henderson
wrote:
>
> On 6/29/22 13:45, Vladimir Sementsov-Ogievskiy wrote:
> > The following changes since commit ad4c7f529a279685da84297773b4ec8080153c2d:
> >
> >Merge tag 'pull-semi-20220628' of https://gitlab.com/rth7680/qemu into
> > staging (2022-0
The added enforcing is only relevant in the case of AMD where the
range right before the 1TB is restricted and cannot be DMA mapped
by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST
or possibly other kinds of IOMMU events in the AMD IOMMU.
Although, there's a case where it may mak
This in preparation to allow pc_pci_hole64_start() to be called early
in pc_memory_init(), handle CXL memory region end when its underlying
memory region isn't yet initialized.
Cc: Jonathan Cameron
Signed-off-by: Joao Martins
---
hw/i386/pc.c | 13 +
1 file changed, 13 insertions(+)
On Fri, Jul 1, 2022 at 4:05 AM Hanna Reitz wrote:
>
> On 16.06.22 16:26, John Snow wrote:
> > In certain container environments we may not have FUSE at all, so skip
> > the test in this circumstance too.
> >
> > Signed-off-by: John Snow
> > ---
> > tests/qemu-iotests/108 | 5 +
> > 1 file
On Fri, Jul 01, 2022 at 09:35:00AM -0400, Igor Mammedov wrote:
> HPET AML doesn't depend on piix4 nor q35, move code buiding it
> to common scope to avoid duplication.
>
> Signed-off-by: Igor Mammedov
Apropos, tests/data/acpi/rebuild-expected-aml.sh ignores the
fact that some tables might be ide
Factor out the calculation of the base address of the MR. It will be
used later on for the cxl range end counterpart calculation and as
well in pc_memory_init() CXL mr initialization, thus avoiding
duplication.
Cc: Jonathan Cameron
Signed-off-by: Joao Martins
---
hw/i386/pc.c | 28 +
Move obtaining hole64_start from device_memory MR base/size into an helper
alongside correspondent getters in pc_memory_init() when the hotplug
range is unitialized.
This is the final step that allows pc_pci_hole64_start() to be callable
at the beginning of pc_memory_init() before any MRs are init
On Thu, 30 Jun 2022 09:30:58 -0400
"Michael S. Tsirkin" wrote:
> On Thu, Jun 30, 2022 at 02:40:13PM +0200, Brice Goglin wrote:
> >
> > Le 30/06/2022 à 14:23, Igor Mammedov a écrit :
> > > On Thu, 30 Jun 2022 09:36:47 +0200
> > > Brice Goglin wrote:
> > >
> > > > Allow -numa without initiat
On Tue, 28 Jun 2022 at 05:40, Richard Henderson
wrote:
>
> We can reuse the SVE functions for implementing moves to/from
> horizontal tile slices, but we need new ones for moves to/from
> vertical tile slices.
>
> Signed-off-by: Richard Henderson
> ---
> diff --git a/target/arm/sme_helper.c b/ta
It is assumed that the whole GPA space is available to be DMA
addressable, within a given address space limit, except for a
tiny region before the 4G. Since Linux v5.4, VFIO validates
whether the selected GPA is indeed valid i.e. not reserved by
IOMMU on behalf of some specific devices or platform-
Move calculation of CXL memory region end to separate helper in
preparation to allow pc_pci_hole64_start() to be called before
any mrs are initialized.
Cc: Jonathan Cameron
Signed-off-by: Joao Martins
---
hw/i386/pc.c | 31 +--
1 file changed, 21 insertions(+), 10 de
There's a couple of places that seem to duplicate this calculation
of RAM size above the 4G boundary. Move all those to a helper function.
Signed-off-by: Joao Martins
---
hw/i386/pc.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/hw/i386/pc.c
v5[6] -> v6:
* Rebased to latest staging
* Consider @cxl_base setting to also use above_4g_mem_start (Igor Mammedov)
* Use 4 * GiB instead of raw hex (Igor Mammedov)
* Delete @host_type (Igor Mammedov)
* Rename to i440fx_dev to i440fx_host (Igor Mammedov)
* Rebase on top of patch that removes i440f
Use the pre-initialized pci-host qdev and fetch the
pci-hole64-size into pc_memory_init() newly added argument.
piix needs a bit of care given all the !pci_enabled()
and that the pci_hole64_size is private to i440fx.
This is in preparation to determine that host-phys-bits are
enough and for pci-ho
On Thu, Jun 30, 2022 at 11:22:31AM +0800, Jinhao Fan wrote:
> +static int nvme_init_sq_ioeventfd(NvmeSQueue *sq)
> +{
> +NvmeCtrl *n = sq->ctrl;
> +uint16_t offset = sq->sqid << 3;
> +int ret;
> +
> +ret = event_notifier_init(&sq->notifier, 0);
> +if (ret < 0) {
> +retur
At the start of pc_memory_init() we usually pass a range of
0..UINT64_MAX as pci_memory, when really its 2G (i440fx) or
32G (q35). To get the real user value, we need to get pci-host
passed property for default pci_hole64_size. Thus to get that,
create the qdev prior to memory init to better make e
Rather than hardcoding the 4G boundary everywhere, introduce a
X86MachineState field @above_4g_mem_start and use it
accordingly.
This is in preparation for relocating ram-above-4g to be
dynamically start at 1T on AMD platforms.
Signed-off-by: Joao Martins
Reviewed-by: Igor Mammedov
---
hw/i386
Signed-off-by: Leonardo Bras
---
qapi/migration.json | 5 -
migration/migration.c | 1 +
monitor/hmp-cmds.c| 4
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/qapi/migration.json b/qapi/migration.json
index 7102e474a6..925f009868 100644
--- a/qapi/migration.json
+++
Some errors, like the lack of Scatter-Gather support by the network
interface(NETIF_F_SG) may cause sendmsg(...,MSG_ZEROCOPY) to fail on using
zero-copy, which causes it to fall back to the default copying mechanism.
After each full dirty-bitmap scan there should be a zero-copy flush
happening, wh
If flush is called when no buffer was sent with MSG_ZEROCOPY, it currently
returns 1. This return code should be used only when Linux fails to use
MSG_ZEROCOPY on a lot of sendmsg().
Fix this by returning early from flush if no sendmsg(...,MSG_ZEROCOPY)
was attempted.
Fixes: 2bc58ffc2926 ("QIOCha
The first patch avoid spuriously returning 1 [*] when zero-copy flush is
attempted before any buffer was sent using MSG_ZEROCOPY.
[*] zero-copy not being used, even though it's enabled and supported
by kernel
The second patch introduces a new migration stat (zero-copy-copied)
that will be used to
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> The logic of trying an final ISO or ECKD boot on virtio-block devices
> is
> very weird: Since the geometry hardly ever matches in
> virtio_disk_is_scsi(),
> virtio_blk_setup_device() always sets a "guessed" disk geometry via
> virtio_assume_s
On Tue, 2022-06-28 at 15:21 +0200, Cornelia Huck wrote:
> On Tue, Jun 28 2022, Thomas Huth wrote:
>
> > Use VIRTIO_DASD_BLOCK_SIZE instead of the magic value 4096.
> >
> > Signed-off-by: Thomas Huth
> > ---
> > pc-bios/s390-ccw/virtio.h| 1 +
> > pc-bios/s390-ccw/virtio-blkdev.c | 2 +-
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> Older versions of Clang complain if there is no prototype for main().
> Add one, and while we're at it, make sure that we use the same type
> for main.c and netmain.c - since the return value does not matter,
> declare the return type of main(
On Fri, Jul 1, 2022 at 4:53 PM Marc-André Lureau
wrote:
> Hi
>
> On Fri, Jul 1, 2022 at 7:11 AM zhenwei pi wrote:
>
>> A vCPU thread always reaches 100% utilization when:
>> - guest uses idle=poll
>> - disable HLT vm-exit
>> - enable MWAIT
>>
>> Add new guest agent command 'guest-get-cpustats' t
On Wed, 8 Jun 2022 at 09:17, Jason Wang wrote:
>
> On Tue, May 31, 2022 at 1:40 PM Zhang, Chen wrote:
> >
> >
> >
> > > -Original Message-
> > > From: Qemu-devel > > bounces+chen.zhang=intel@nongnu.org> On Behalf Of Haochen Tong
> > > Sent: Saturday, May 28, 2022 3:07 AM
> > > To: qe
Hi
On Fri, Jul 1, 2022 at 7:11 AM zhenwei pi wrote:
> A vCPU thread always reaches 100% utilization when:
> - guest uses idle=poll
> - disable HLT vm-exit
> - enable MWAIT
>
> Add new guest agent command 'guest-get-cpustats' to get guest CPU
> statistics, we can know the guest workload and how b
On Fri, 15 Oct 2021 at 16:01, Kevin Wolf wrote:
> QDicts are both what QMP natively uses and what the keyval parser
> produces. Going through QemuOpts isn't useful for either one, so switch
> the main device creation function to QDicts. By sharing more code with
> the -object/object-add code path,
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 +++
target/ppc/mmu-hash64.c | 27
target/ppc/translate/storage-ctrl-impl.c.inc | 14
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 5 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 17 -
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate.c | 17 -
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
3 files changed, 16 insertions(+), 17 deletio
Expected change:
+Device (SE8)
+{
+Name (_ADR, 0x001D) // _ADR: Address
+Name (ASUN, 0x1D)
Method (_DSM, 4, Serialized) // _DSM: Device-Specific
Method
{
This is a follow-up for commit 892a4f6a750a ("linux-user: Add partial
support for MADV_DONTNEED"), which added passthrough for anonymous
mappings. File mappings can be handled in a similar manner.
In order to do that, mark pages, for which mmap() was passed through,
with PAGE_PASSTHROUGH, and then
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 26 ---
targe
Expected change:
-Name (_SUN, 0x0X) // _SUN: Slot User Number
Name (_ADR, 0xY) // _ADR: Address
...
+Name (_SUN, 0xX) // _SUN: Slot User Number
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 14 -
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 14 --
target
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 12
target/p
align _DSM method in empty slot descriptor with
a populated slot position.
Expected change:
+Device (SE8)
+{
+Name (_ADR, 0x001D) // _ADR: Address
+Name (ASUN, 0x1D)
Method (_DSM, 4, Serialized) // _DSM: Device
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
target/p
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..1983fa596b 100644
--- a/tests/qtest/bios-ta
From: Matheus Ferst
Equivalent to CHK_SV and CHK_HV, but can be used in decodetree methods.
Reviewed-by: Leandro Lupori
Signed-off-by: Matheus Ferst
Signed-off-by: Lucas Coutinho
---
target/ppc/translate.c | 21 +
target/ppc/translate/fixedpoint-impl.c
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
target/p
.., it will help with code readability and make easier
to extend method in followup patches
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 139 ---
1 file changed, 77 insertions(+), 62 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 7 +++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
ta
Numer of possible arguments to pass to a method is limited
in ACPI. The following patches will need to pass over more
parameters to PDSM method, will hit that limit.
Prepare for this by passing structure (Package) to method,
which let us workaround arguments limitation.
Pass to PDSM all standard a
Resent after rebasing and fixing conflicts with master.
Add Leandro Lupori as reviewer.
Based-on: <20220624191424.190471-1-leandro.lup...@eldorado.org.br>
Implement the following PowerISA v3.0 instuction:
slbiag: SLB Invalidate All Global X-form
Move the following PowerISA v3.0 instuction to dec
From: Matheus Ferst
GEN_PRIV and related CHK_* macros just assumed that variable named
"ctx" would be in scope when they are used, and that it would be a
pointer to DisasContext. Change these macros to receive the pointer
explicitly.
Reviewed-by: Leandro Lupori
Signed-off-by: Matheus Ferst
Si
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..1983fa596b 100644
--- a/tests/qtest/bios-ta
No functional change nor AML bytcode change.
Consolidate code that generates empty and populated slots
descriptors. Beside of eliminating duplication,
it helps to consolidate conditions for generating
parts of Device{} desriptor in one place, which makes
code more compact and easier to read.
Signe
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..1983fa596b 100644
--- a/tests/qtest/bios-ta
add ASUN variable to hotpluggable slots and use it
instead of _SUN which has the same value to reuse
_DMS code on both branches (hot- and non-hotpluggable).
No functional change.
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 56 +---
1 file chang
HPET AML moved after PCI host bridge description (no functional change)
diff example for PC machine:
@@ -54,47 +54,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC",
0x0001)
}
}
-Scope (_SB)
-{
-Device (HPET)
-{
-Name (_HID, EisaId (
no functional change, align order of fields in empty slot
descriptor with a populated slot ordering.
Expected diff:
-Name (_SUN, 0x0X) // _SUN: Slot User Number
Name (_ADR, 0xY) // _ADR: Address
...
+Name (_SUN, 0xX) // _SUN: Slot User Num
An intermediate blobs update to keep changes (last 2 patches)
reviewable.
Includes refactored PDSM that uses Package argument for custom
parameters.
= PDSM taking package as arguments
Return (Local0)
}
-Method (PDSM, 6, Serialized)
+Method (PDSM, 5, Se
It's expected that hotpluggable slots will, get ASUN variable
and use that instead of _SUN with its _DSM method.
For example:
@@ -979,8 +979,9 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC",
0x0001)
Device (S18)
{
-Name (_SUN, 0x03)
HPET AML doesn't depend on piix4 nor q35, move code buiding it
to common scope to avoid duplication.
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index cad6f5ac41..
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 34 +
1 file changed, 34 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..452145badd 100644
--- a/tests/qtest/
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 32 +
1 file changed, 32 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..a7aa428fab 100644
--- a/tests/qtest/
Flushing out ACPI PCI cleanups that preceed conversion of
DSDT PCI slots ennumeration to AcpiDevAmlIf interface.
It's is mostly collection of patches thraet removes code
duplication, we've accumulated around PCI relaterd AML
in DSDT.
git:
https://gitlab.com/imammedo/qemu.git x86_pci_cleanups
I
Whilst the interleave granularity is always small enough that this isn't
a real problem (much less than 4GiB) let's change the constant
to ULL to fix the coverity warning.
Reported-by: Peter Maydell
Fixes: 829de299d1 ("hw/cxl/component: Add utils for interleave parameter
encoding/decoding")
Fixe
This got left behind in the move of the CXL setup code from core
files to the machines that support it.
Link:
https://gitlab.com/qemu-project/qemu/-/commit/1ebf9001fb2701e3c00b401334c8f3900a46adaa
Signed-off-by: Jonathan Cameron
---
include/hw/boards.h | 1 -
1 file changed, 1 deletion(-)
diff
Previously broken_reserved_end was taken into account, but Igor Mammedov
identified that this could lead to a clash between potential RAM being
mapped in the region and CXL usage. Hence always add the size of the
device_memory memory region. This only affects the case where the
broken_reserved_end
Three more or less less unrelated fixes for recently added CXL code.
Jonathan Cameron (3):
hw/machine: Clear out left over CXL related pointer from move of state
handling to machines.
hw/i386/pc: Always place CXL Memory Regions after device_memory
hw/cxl: Fix size of constant in interlea
On [2022 Jul 01] Fri 14:23:17, Cédric Le Goater wrote:
> On 7/1/22 13:40, Francisco Iglesias wrote:
> > Hi Iris,
> >
> > Looks good, a couple of minor comments below!
> >
> > On [2022 Jun 27] Mon 11:52:33, Iris Chen wrote:
> > > Signed-off-by: Iris Chen
> > > ---
> > > hw/block/m25p80.c | 74 +
On Tue, 28 Jun 2022 at 05:32, Richard Henderson
wrote:
>
> These functions will be used to verify that the cpu
> is in the correct state for a given instruction.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, 28 Jun 2022 at 05:39, Richard Henderson
wrote:
>
> The pseudocode for CheckSVEEnabled gains a check for Streaming
> SVE mode, and for SME present but SVE absent.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/translate-a64.c | 22 --
> 1 file changed, 16 inse
Dear Qemu Genius
This is zaifeng (wzf_develo...@foxmail.com) (WeChat ID: QemuKVM).
Yes, I am a cloud engineer. (๑•̀ㅂ•́)و✧
May I ask you some questions about Qemu?
Here is the problem:
If you use IDE disk on a Windows VM, "QEMU HARDDISK" could be found from devi
On 6/20/22 19:19, Daniel P. Berrangé wrote:
> Libvirt provides QMP passthrough APIs for the QEMU driver and these are
> exposed in virsh. It is not especially pleasant, however, using the raw
> QMP JSON syntax. QEMU has a tool 'qmp-shell' which can speak QMP and
> exposes a human friendly interacti
On Tue, 28 Jun 2022 at 05:49, Richard Henderson
wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/sme-fa64.decode | 3 ---
> target/arm/translate-sve.c | 2 ++
>
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