Hi Richard,
On 2022/6/10 上午2:42, Richard Henderson wrote:
void helper_asrtle_d(CPULoongArchState *env, target_ulong rj,
target_ulong rk)
{
if (rj > rk) {
+#ifdef CONFIG_USER_ONLY
+ cpu_loop_exit_sigsegv(env_cpu(env), GETPC(),
+ MMU_DATA_LOAD, true,
On 09/06/2022 11:49, Peter Maydell wrote:
On Sun, 22 May 2022 at 19:19, Mark Cave-Ayland
wrote:
This allows the I8042_MMIO reset function to be registered directly within the
DeviceClass rather than using qemu_register_reset() directly.
Signed-off-by: Mark Cave-Ayland
---
hw/input/pckbd.c
On Thu, Jun 09, 2022 at 04:12:25PM +0200, BALATON Zoltan wrote:
> On Thu, 9 Jun 2022, Gerd Hoffmann wrote:
> > On Wed, May 18, 2022 at 12:37:18PM +0200, Paolo Bonzini wrote:
> > > On 5/17/22 21:47, BALATON Zoltan wrote:
> > > > On Mon, 9 May 2022, BALATON Zoltan wrote:
> > > > > On Mon, 2 May 2022,
On Tue, May 31, 2022 at 01:23:26PM -0700, Dongwon Kim wrote:
> Detaching any addtional guest displays in case there are multiple
> displays assigned to the guest OS (e.g. max_outputs=n) so that
> all of them are visible upon lauching.
>
> Cc: Daniel P. Berrangé
> Cc: Markus Armbruster
> Cc: Phil
On Tue, May 31, 2022 at 01:23:27PM -0700, Dongwon Kim wrote:
> New integer array parameter, 'monitor' is for specifying the target
> displays where individual QEMU windows are placed upon launching.
>
> The array contains a series of numbers representing the monitor where
> QEMU windows are placed
On Thu, May 19, 2022 at 02:30:43AM -0400, Jonah Palmer wrote:
>
> On 5/16/22 16:26, Michael S. Tsirkin wrote:
>
> On Fri, Apr 01, 2022 at 09:23:22AM -0400, Jonah Palmer wrote:
>
> From: Laurent Vivier
>
> Display feature names instead of bitmaps for host, guest, and
>
From: Frank Chang
If the value written to tselect is greater than or equal to the number
of supported triggers, then the following reads of tselect would return
value 0.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 1 +
target/riscv/debug.c | 6 ++
2 files changed, 7 insertions(+)
From: Frank Chang
Type 6 trigger is similar to a type 2 trigger, but provides additional
functionality and should be used instead of type 2 in newer
implementations.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 174 ++-
target/riscv/debug.h | 1
From: Frank Chang
Type 2 trigger cannot be fired in VU/VS modes.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index ab23566113..ce9ff15d75 100644
--- a/target/riscv/debug.c
+++ b/
From: Frank Chang
Trigger actions are shared among all triggers. Extract to a common
function.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 55 ++--
target/riscv/debug.h | 13 +++
2 files changed, 66 insertions(+), 2 deletions(-)
diff -
From: Frank Chang
Current RISC-V debug assumes that only type 2 trigger is supported.
To allow more types of triggers to be supported in the future
(e.g. type 6 trigger, which is similar to type 2 trigger with additional
functionality), we should determine the trigger type from tdata1.type.
RV_
From: Frank Chang
tinfo.info:
One bit for each possible type enumerated in tdata1.
If the bit is set, then that type is supported by the currently
selected trigger.
Signed-off-by: Frank Chang
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 8
target/riscv/debug.c
From: Frank Chang
Introduce build_tdata1() to build tdata1 register content, which can be
shared among all types of triggers.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/riscv/debug.c b/target/r
From: Frank Chang
The value of tselect CSR can be written should be limited within the
range of supported triggers number.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/riscv/debug.c b/target/riscv/debug.
From: Frank Chang
This patchset refactors RISC-V Debug support to allow more types of
triggers to be extended.
The initial support of type 6 trigger, which is similar to type 2
trigger with additional functionality, is also introduced in this
patchset.
Frank Chang (9):
target/riscv: debug: De
From: Frank Chang
Replace type2_trigger_t with the real tdata1, tdata2, and tdata3 CSRs,
which allows us to support more types of triggers in the future.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 6 ++-
target/riscv/debug.c | 101 -
tar
From: Alistair Francis
When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
tcg_gen_gvec_dup_i32().
This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
is required.
Resolves: https://gitla
From: eopXD
The tail elements in the destination mask register are updated under
a tail-agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165449614532.19704.7000832880482980398...@git.sr.ht>
Signed-off-by: Alistai
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165449614532.19704.700083288048298039...@git.sr.ht>
Signed-off-by: Alistair Francis
From: eopXD
`vmadc` and `vmsbc` produces a mask value, they always operate with
a tail agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165449614532.19704.700083288048298039...@git.sr.ht>
Signed-off-by: Alistair
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
A vector segment load / store instruction may contain fractional lmul
with nf * lmul > 1. The rest of the elements in the last register should
be treated as tail eleme
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165449614532.19704.7000832880482980398...@git.sr.ht>
Signed-off-by: Alistair Francis
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165449614532.19704.7000832880482980398...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 40 +
target
From: Alistair Francis
There are currently two types of RISC-V CPUs:
- Generic CPUs (base or any) that allow complete custimisation
- "Named" CPUs that match existing hardware
Users can use the base CPUs to custimise the extensions that they want, for
example -cpu rv64,v=true.
We originally e
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165449614532.19704.7000832880482980398...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c | 20
1 file changed, 20 ins
From: eopXD
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165449614532.19704.7000832880482980398...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c | 220 ++-
1 file
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id: <165449614532.19704.700083288048298039...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c
From: Frédéric Pétrot
Add an MXL_RV128 case in two switches so that no error is triggered when
using the -cpu x-rv128 option.
Signed-off-by: Frédéric Pétrot
Acked-by: Alistair Francis
Reviewed-by: Bin Meng
Message-Id: <20220602155246.38837-1-frederic.pet...@univ-grenoble-alpes.fr>
Signed-off-
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Alistair Francis
Message-Id: <165449614532.19704.700083288048298039...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c | 35 ---
1 file c
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165449614532.19704.7000832880482980398...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 20
target/risc
From: Jamie Iles
Various loader functions return an int which limits images to 2GB which
is fine for things like a BIOS/kernel image, but if we want to be able
to load memory images or large ramdisks then any file over 2GB would
silently fail to load.
Cc: Luc Michel
Signed-off-by: Jamie Iles
R
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165449614532.19704.700083288048298039...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 11 +++
target/riscv/insn_tra
From: Andrew Bresticker
Whether or not VSEIP is pending isn't reflected in env->mip and must
instead be determined from hstatus.vgein and hgeip. As a result a
CPU in WFI won't wake on a VSEIP, which violates the WFI behavior as
specified in the privileged ISA. Just use riscv_cpu_all_pending()
ins
From: Atish Patra
fw_cfg DT node is generated after the create_fdt without any check
if the DT is being loaded from the commandline. This results in
FDT_ERR_EXISTS error if dtb is loaded from the commandline.
Generate fw_cfg node only if the DT is not loaded from the commandline.
Signed-off-by:
From: Alistair Francis
Since commit ad40be27 "target/riscv: Support start kernel directly by
KVM" we have been overflowing the addr_config on "M,MS..."
configurations, as reported https://gitlab.com/qemu-project/qemu/-/issues/1050.
This commit changes the loop in sifive_plic_create() from iterat
From: Weiwei Li
Add support for the zmmul extension v0.1. This extension includes all
multiplication operations from the M extension but not the divide ops.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Víctor Colombo
Reviewed-by: Alistair Francis
Message-Id: <2022053103
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220509091339.26016-1-alistair.fran...@wdc.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5580a36b68..b3af081c51 100644
--- a/MAINT
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id: <165449614532.19704.700083288048298039...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c
From: Alistair Francis
The following changes since commit 9cc1bf1ebca550f8d90f967ccd2b6d2e00e81387:
Merge tag 'pull-xen-20220609' of
https://xenbits.xen.org/git-http/people/aperard/qemu-dm into staging
(2022-06-09 08:25:17 -0700)
are available in the Git repositor
Dear Paul Brook:
in qemu/tcg/README:
"
...
QOP code generator written by Paul Brook.
...
"
Is there some text about QOP? or basically what QOP stands for?
I can't find out anything about QOP from Google. thanks.
Hello Daniel,
On Thu, Jun 9, 2022 at 5:10 AM Daniel P. Berrangé wrote:
>
> On Wed, Jun 08, 2022 at 06:04:02PM -0300, Leonardo Bras wrote:
> > During implementation of MSG_ZEROCOPY feature, a lot of #ifdefs were
> > introduced, particularly at qio_channel_socket_writev().
> >
> > Rewrite some of t
Hi Xuerui.
Thanks for you comments.
On 2022/6/9 下午6:04, WANG Xuerui wrote:
On 2022/6/9 10:42, Song Gao wrote:
We should disable '__BITS_PER_LONG' at [1] before run gensyscalls.sh
[1] arch/loongarch/include/uapi/asm/bitsperlong.h
I'm not sure why this is necessary, is this for building on
Hello, At least one machines, the PC (i440fx machine), have an NV25 graphic chip by default (GeForce4 Ti 4200) and It must be pbus, pcrtc, pfb, pfifo, pgraph, pmc, pramdac, and ptimer same as NV2A GPU. It must be NV25 vendor ID and device ID to 10DE:0253. But sadly, I don’t have an patch emulation
On Tue, Jun 7, 2022 at 7:22 PM Chao Peng wrote:
>
> On Tue, Jun 07, 2022 at 05:55:46PM -0700, Marc Orr wrote:
> > On Tue, Jun 7, 2022 at 12:01 AM Chao Peng
> > wrote:
> > >
> > > On Mon, Jun 06, 2022 at 01:09:50PM -0700, Vishal Annapurve wrote:
> > > > >
> > > > > Private memory map/unmap and co
On Thu, Jun 9, 2022 at 9:47 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
> true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
> tcg_gen_gvec_dup_i32().
>
> This patch checks that condition and ins
On 6/9/22 08:35, Peter Maydell wrote:
+if (!disas_sme(s, insn)) {
+unallocated_encoding(s);
+}
+break;
I still think we should check bit 31 here.
We don't do anything similar over in a32, where we've done the full conversion:
if (disas_a32_uncond(s
Because reset always initializes the AA64 version, SCR_EL3,
test the mode of EL3 instead of the type of the cpreg.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
Since DDI0487F.a, the RW bit is RAO/WI. When specifically
targeting such a cpu, e.g. cortex-a76, it is legitimate to
ignore the bit within the secure monitor.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 5 +
target/
Adjust RW, fixing #1062, and adjusting bits [4:2].
Changes for v2:
* Fix patch 1 vs reset.
r~
Richard Henderson (2):
target/arm: Adjust format test in scr_write
target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]
target/arm/cpu.h| 5 +
target/arm/helper.c | 18 -
Creating 1GB image for a simple qtest is unnecessary
and could lead to failures. We reduce the image size
to 1MB to reduce the test overhead.
Signed-off-by: Hao Wu
---
tests/qtest/npcm7xx_sdhci-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/npcm7xx_sdhci-t
Hi,
We did some experiments on this issue. It looks like the image size
restriction is in firmware. So in qtest we can make it
much smaller (e.g. 1MB) and the test still passes. We can send a patch with
this change if necessary.
On Thu, May 26, 2022 at 9:21 AM Patrick Venture wrote:
>
>
> On Th
This function is no longer used outside debug_helper.c.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 21 -
target/arm/debug_helper.c | 21 +
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/ta
Create a new wrapper function that passes the default
exception target to gen_exception_el.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index fc5eafaeeb..edb7d3f394 100644
--- a/target/arm/translate.c
+++ b/tar
On 13/05/2022 13:21, Markus Armbruster wrote:
Laurent Vivier writes:
As qemu_opts_parse_noisily() flattens the QAPI structures ("type" field
of Netdev structure can collides with "type" field of SocketAddress),
To remember how this works, I have to write a more verbose version of
the above.
Split out a common helper function for gen_exception_el
and gen_exception_insn_el_v.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/trans
Handle the debug vs current el exception test in one place.
Leave EXCP_BKPT alone, since that treats debug < current differently.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 44 +--
1 file changed, 24 insertions
This function is not required by any other translation file.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 8
target/arm/translate.c | 7 +++
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.h b/target/ar
This function is no longer used. At the same time, remove
DisasContext.secure_routed_to_el3, as it in turn becomes unused.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 16
target/arm/translate-a64.c | 5 -
target/arm/transla
On Wed, Jun 08, 2022, Vishal Annapurve wrote:
> ...
> > With this patch series, it's actually even not possible for userspace VMM
> > to allocate private page by a direct write, it's basically unmapped from
> > there. If it really wants to, it should so something special, by intention,
> > that's b
We were using arm_is_secure and is_a64, which are
tests against the current EL, as opposed to
arm_el_is_aa64 and arm_is_secure_below_el3, which
can be applied to a different EL than current.
Consolidate the two tests.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/he
With the helper we can use exception_target_el at runtime,
instead of default_exception_el at translate time.
While we're at it, remove the DisasContext parameter from
gen_exception, as it is no longer used.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h
On Wed, Jun 08, 2022 at 06:05:28PM +0100, Dr. David Alan Gilbert wrote:
> > @@ -2005,7 +2005,17 @@ static void loadvm_postcopy_handle_run_bh(void
> > *opaque)
> > /* TODO we should move all of this lot into postcopy_ram.c or a shared
> > code
> > * in migration.c
> > */
> > -
This function now now only used in debug_helper.c, so there is
no reason to have a declaration in a header.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h| 25 -
target/arm/debug_helper.c | 26 ++
2 file
Create a new wrapper function that passes the default
exception target to gen_exception_insn_el.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.h| 1 +
target/arm/translate-a64.c| 15 ++-
target/arm/translate-m-nocp.c | 3 +--
targ
Use the accessor rather than the raw structure member.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 20a0e4261a..a18a09a0c3
We no longer need this value during translation,
as it is now handled within the helpers.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 6 ++
target/arm/translate.h | 2 --
target/arm/helper.c| 12 ++--
target/arm/translat
Move the function to op_helper.c, near raise_exception.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 16 +---
target/arm/op_helper.c | 15 +++
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/target/arm/internal
Create a function below gen_exception_insn that takes
the target_el as a TCGv_i32, replacing gen_exception_el.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.h| 4 ++--
target/arm/translate-a64.c| 36
target/arm/translate-m-nocp.c | 16 +++---
target/arm/translate-mve.c| 4 ++--
target/arm/translate-vfp.c
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 31 +++
target/arm/op_helper.c| 29 -
2 files changed, 31 insertions(+), 29 deletions(-)
diff --git a/target/arm/debug_helper.c b/target/arm/de
Rename to helper_exception_with_syndrome_el, to emphasize
that the target el is a parameter.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 2 +-
target/arm/translate.h | 6 +++---
target/arm/op_helper.c | 6 +++---
target/arm/translate.c | 6 +++---
4
Move the computation from gen_swstep_exception into a helper.
This fixes a bug when:
- MDSCR_EL1.KDE == 1 to enable debug exceptions within EL_D itself
- we singlestep an ERET from EL_D to some lower EL
Previously we were computing 'same el' based on the EL which
executed the ERET instruction
On 6/9/22 09:53, Peter Maydell wrote:
On Tue, 7 Jun 2022 at 04:06, Richard Henderson
wrote:
Not a bug, because arm_is_el2_enabled tests for secure,
and SCR_EL3.EEL2 cannot be set for AArch32, however the
ordering of the tests looks odd. Mirror the structure
over in exception_target_el().
I
Move arm_generate_debug_exceptions and its two subroutines,
{aa32,aa64}_generate_debug_exceptions into debug_helper.c,
and the one interface declaration to internals.h.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 91 ---
Move the function to debug_helper.c, and the
declaration to internals.h.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 --
target/arm/internals.h| 1 +
target/arm/debug_helper.c | 12
3 files changed, 13 insertions(+), 1
With ARMv8, this field is always RES0.
With ARMv7, targeting EL2 and TA=0, it is always 0xA.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/syndrome.h | 7 ---
target/arm/translate-a64.c | 3 ++-
target/arm/translate-vfp.c | 14 --
3 files chan
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index b1334e0c42..5161cdf73d 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -44,9
This is mostly code movement at this point, out of headers
and into op_helper.c and debug_helper.c.
Changes for v3:
* Drop helper_exception_advsimdfp_access.
* Drop Rearrange Secure PL1 test in arm_debug_target_el.
* Improve patch comment for helper_exception_swstep.
All patches are reviewe
Hi Iris,
Looks good some, a couple of comments below.
On [2022 Jun 08] Wed 20:13:19, Iris Chen wrote:
> From: Iris Chen
>
> Signed-off-by: Iris Chen
> ---
> Addressed all comments from V1. The biggest change: removed
> object_class_property_add.
>
> hw/block/m25p80.c | 37 ++
On 6/9/22 10:21, Kevin Wolf wrote:
The following changes since commit 028f2361d0c2d28d6f918fe618f389228ac22b60:
Merge tag 'pull-target-arm-20220609' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-06-09
06:47:03 -0700)
are available in the Git repository a
On 6/8/22 19:42, Song Gao wrote:
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 85c11a60d4..ee42707868 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -93,8 +93,7 @@ DEF_HELPER_2(frint_d, i64, env, i64)
DEF_HELPER_FLAGS_2(set_rounding_mode,
> On Jun 9, 2022, at 12:22 PM, Francisco Iglesias
> wrote:
>
> Hi Iris,
>
> Looks good some, a couple of comments below.
>
> On [2022 Jun 08] Wed 20:13:19, Iris Chen wrote:
>> From: Iris Chen
>>
>> Signed-off-by: Iris Chen
>> ---
>> Addressed all comments from V1. The biggest change: remo
On Thu, Jun 09, 2022 at 07:27:57PM +0200, Klaus Jensen wrote:
> > It's not just unnecessary, but enabling shadow doorbells on admin queues
> > will
> > actively break device implementations (such as SPDK), which have had to
> > presume
> > that driver implementations don't use shadow doorbells f
On 20:00 Thu 26 May , Peter Maydell wrote:
> Currently we mishandle the --semihosting-config option if the
> user specifies it on the command line more than once. For
> example with:
> --semihosting-config target=gdb --semihosting-config arg=foo,arg=bar
>
> the function qemu_semihosting_confi
On 20:00 Thu 26 May , Peter Maydell wrote:
> In two places in gdbstub.c we look at gdbserver_state.init to decide
> whether we're going to do a semihosting syscall via the gdb remote
> protocol:
> * when setting up, if the user didn't explicitly select either
>native semihosting or gdb sem
On Thu, Jun 09, 2022 at 05:47:12PM +0100, Stefan Hajnoczi wrote:
It may not be obvious why laio_io_unplug() checks max batch. I discussed
this with Stefano and have added a comment summarizing the reason.
Cc: Stefano Garzarella
Cc: Kevin Wolf
Signed-off-by: Stefan Hajnoczi
---
block/linux-aio
On Thu, Jun 09, 2022 at 05:47:11PM +0100, Stefan Hajnoczi wrote:
Every laio_io_plug() call has a matching laio_io_unplug() call. There is
a plugged counter that tracks the number of levels of plugging and
allows for nesting.
The plugged counter must reflect the balance between laio_io_plug() and
https://xenbits.xen.org/git-http/people/aperard/qemu-dm.git
tags/pull-xen-20220609
for you to fetch changes up to 6a8a8b62bdc8e3d7c5fc0f82ef4583707183b12f:
include/hw/ide: Unexport pci_piix3_xen_ide_unplug() (2022-06-09 14:47
From: Stefan Hajnoczi
Commit 1b7fd729559c ("block: rename buffer_alignment to
guest_block_size") noted:
At this point, the field is set by the device emulation, but completely
ignored by the block layer.
The last time the value of buffer_alignment/guest_block_size was
actually used was befo
From: Stefan Hajnoczi
bdrv_co_drain() has not been used since commit 9a0cec664eef ("mirror:
use bdrv_drained_begin/bdrv_drained_end") in 2016. Remove it so there
are fewer drain scenarios to worry about.
Use bdrv_drained_begin()/bdrv_drained_end() instead. They are "mixed"
functions that can be
From: Vladimir Sementsov-Ogievskiy
We have too much logic to simply check that bitmaps are of the same
size. Let's just define that hbitmap_merge() and
bdrv_dirty_bitmap_merge_internal() require their argument bitmaps be of
same size, this simplifies things.
Let's look through the callers:
For
From: Xie Yongji
Now the req->size is set to the correct value only
when handling VIRTIO_BLK_T_GET_ID request. This patch
fixes it.
Signed-off-by: Xie Yongji
Message-Id: <20220523084611.91-3-xieyon...@bytedance.com>
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Kevin Wolf
---
block/export/vhos
From: Vladimir Sementsov-Ogievskiy
We don't need extra bitmap. All we need is to backup the original
bitmap when we do first merge. So, drop extra temporary bitmap and work
directly with target and backup.
Still to keep old semantics, that on failure target is unchanged and
user don't need to re
On 09/06/2022 18.31, Vince Del Vecchio wrote:
On Thu, Jun 9, 2022 at 10:34AM, Thomas Huth wrote:
On 09/06/2022 16.15, Claudio Fontana wrote:
On 6/9/22 13:27, Claudio Fontana wrote:
On 6/9/22 10:57, Daniel P. Berrangé wrote:
On Thu, Jun 09, 2022 at 10:47:24AM +0200, Thomas Huth wrote:
On 08/0
On Thu, Jun 09, 2022 at 05:46:29PM +0100, Dr. David Alan Gilbert wrote:
> * Daniel P. Berrangé (berra...@redhat.com) wrote:
> > This directly implements the get_buffer logic using QIOChannel APIs.
> >
> > Signed-off-by: Daniel P. Berrangé
> > ---
> > migration/qemu-file-channel.c | 29 --
On Jun 9 16:52, John Levon wrote:
> On Thu, Jun 09, 2022 at 08:29:30AM -0600, Keith Busch wrote:
>
> > On Wed, Jun 08, 2022 at 10:55:30PM +0200, Klaus Jensen wrote:
> > >
> > > Keith, is this a bug in the kernel? If the code here would expect the
> > > doorbell buffer to be updated for the admin
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