Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 1 -
target/arm/helper.c | 16
target/arm/ptw.c| 16
3 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/target/arm/ptw.h b/target/arm/ptw.h
index 3d3061a435..ed152ddaf4 100644
--- a/tar
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 1 -
target/arm/helper.c | 24
target/arm/ptw.c| 22 ++
3 files changed, 22 insertions(+), 25 deletions(-)
diff --git a/target/arm/ptw.h b/target/arm/ptw.h
index 85ad576794..3d3061a435 10
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 3 ---
target/arm/helper.c | 64 -
target/arm/ptw.c| 64 +
3 files changed, 64 insertions(+), 67 deletions(-)
diff --git a/target/arm/ptw.h b/ta
The use of ARM_CPU to recover env from cs calls
object_class_dynamic_cast, which shows up on the profile.
This is pointless, because all callers already have env, and
the reverse operation, env_cpu, is only pointer arithmetic.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 23 +-
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 2 --
target/arm/helper.c | 70 -
target/arm/ptw.c| 70 +
3 files changed, 70 insertions(+), 72 deletions(-)
diff --git a/target/arm/ptw.h b/tar
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 17
target/arm/helper.c | 47 -
target/arm/ptw.c| 47 -
3 files changed, 46 insertions(+), 65 deletions(-)
delete mode 100644 ta
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 32
target/arm/ptw.c| 28
2 files changed, 28 insertions(+), 32 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1c75962a3b..1018cd24eb 100644
---
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 3 --
target/arm/helper.c | 128
target/arm/ptw.c| 128
3 files changed, 128 insertions(+), 131 deletions(-)
diff --git a/target/arm/ptw.h b/
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 26 --
target/arm/ptw.c| 24
2 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7390798463..1c75962a3b 100644
--- a/target/
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 10 ++
target/arm/helper.c | 416 +---
target/arm/ptw.c| 411 +++
3 files changed, 429 insertions(+), 408 deletions(-)
diff --git a/target/arm/ptw.h b/t
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 2 --
target/arm/helper.c | 25 -
target/arm/ptw.c| 25 +
3 files changed, 25 insertions(+), 27 deletions(-)
diff --git a/target/arm/ptw.h b/target/arm/ptw.h
index 28b8cb9fb8..fba650d0
Move the ptw load functions, plus 3 common subroutines:
S1_ptw_translate, ptw_attrs_are_device, and regime_translation_big_endian.
This also allows get_phys_addr_lpae to become static again.
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 13
target/arm/helper.c | 141 --
This is the final user of get_phys_addr_pmsav7_default
within helper.c, so make it static within ptw.c.
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 3 -
target/arm/helper.c | 136 -
target/arm/ptw.c| 146 +++
These functions are used for both page table walking and for
deciding what format in which to deliver exception results.
Since ptw.c is only present for system mode, put the functions
into tlb_helper.c.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 24
t
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 3 ---
target/arm/helper.c | 15 ---
target/arm/ptw.c| 16
3 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/target/arm/ptw.h b/target/arm/ptw.h
index d2d2711908..6c47a57599 100644
--- a/ta
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 5 ---
target/arm/helper.c | 75 ---
target/arm/ptw.c| 77 +
3 files changed, 77 insertions(+), 80 deletions(-)
diff --git a/target/arm/ptw.h b/targ
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 4 ++--
target/arm/helper.c | 26 +-
target/arm/ptw.c| 23 +++
3 files changed, 26 insertions(+), 27 deletions(-)
diff --git a/target/arm/ptw.h b/target/arm/ptw.h
index 6c47a57599..dd6fb93
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 10 --
target/arm/helper.c | 77 --
target/arm/ptw.c| 81 +
3 files changed, 81 insertions(+), 87 deletions(-)
diff --git a/target/arm/ptw.h b/ta
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 2 --
target/arm/helper.c | 19 ---
target/arm/ptw.c| 21 +
3 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/arm/ptw.h b/target/arm/ptw.h
index 8d2e239714..d2d2711908 100644
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 3 +++
target/arm/helper.c | 41 -
target/arm/ptw.c| 41 +
3 files changed, 44 insertions(+), 41 deletions(-)
diff --git a/target/arm/ptw.h b/target/arm
This function has one private helper, v8m_is_sau_exempt,
so move that at the same time.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 123 --
target/arm/ptw.c| 126
2 files changed, 126 insertio
There are a handful of helpers for combine_cacheattrs
that we can move at the same time as the main entry point.
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 3 -
target/arm/helper.c | 218 ---
target/arm/ptw.c| 221
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 10 +--
target/arm/helper.c | 194 +---
target/arm/ptw.c| 190 +++
3 files changed, 198 insertions(+), 196 deletions(-)
diff --git a/target/arm/ptw.h b/
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 11 +--
target/arm/helper.c | 161 +---
target/arm/ptw.c| 153 +
3 files changed, 161 insertions(+), 164 deletions(-)
diff --git a/target/arm/ptw.h b/ta
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 4 ---
target/arm/helper.c | 85 -
target/arm/ptw.c| 85 +
3 files changed, 85 insertions(+), 89 deletions(-)
diff --git a/target/arm/ptw.h b/ta
Begin moving all of the page table walking functions
out of helper.c, starting with get_phys_addr().
Create a temporary header file, "ptw.h", in which to
share declarations between the two C files while we
are moving functions.
Move a few declarations to "internals.h", which will
remain used by m
Signed-off-by: Richard Henderson
---
target/arm/ptw.h| 15 +++--
target/arm/helper.c | 137 +++-
target/arm/ptw.c| 123 +++
3 files changed, 140 insertions(+), 135 deletions(-)
diff --git a/target/arm/ptw.h b/ta
Move the decl from ptw.h to internals.h. Provide an inline
version for user-only, just as we do for arm_stage1_mmu_idx.
Move an endif down to make the definition in helper.c be
system only.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 5 +
target/arm/helper.c| 5 ++---
The object here is to move 2500 lines out of helper.c. Yay!
r~
Richard Henderson (28):
target/arm: Move stage_1_mmu_idx decl to internals.h
target/arm: Move get_phys_addr to ptw.c
target/arm: Move get_phys_addr_v5 to ptw.c
target/arm: Move get_phys_addr_v6 to ptw.c
target/arm: Move g
GCC11 from crossbuild-essential-armhf from ubuntu 22.04 errors:
cc1: error: ‘-mfloat-abi=hard’: selected architecture lacks an FPU
Signed-off-by: Richard Henderson
---
tests/tcg/arm/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/tcg/arm/Makefile
On 6/3/22 12:53, Klaus Jensen wrote:
From: Klaus Jensen
Hi Peter,
The following changes since commit 70e975203f366f2f30daaeb714bb852562b7b72f:
Merge tag 'pull-request-2022-06-03' of https://gitlab.com/thuth/qemu into
staging (2022-06-03 06:43:38 -0700)
are available in the Git repository
We had been using the i686 platform string for x86_64.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1041
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/linux-user/elfload.c
When metadata is present in the namespace and deallocates are issued, the first
deallocate could fail to zero the block range, resulting in another
deallocation to be issued. Normally after the deallocation completes and the
range is checked for zeroes, a deallocation is then issued for the metadat
On 6/2/22 13:33, Frederic Barrat wrote:
On 31/05/2022 23:49, Daniel Henrique Barboza wrote:
To enable user creatable PnvPHB devices for powernv9 we'll revert the
powernv9 related changes made in 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices".
This change alone isn't enough to
On Thu, May 12, 2022 at 11:30:55AM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> The internally maintained AEN mask is not cleared on reset. Fix this.
Looks good.
Reviewed-by: Keith Busch
On 6/2/22 05:12, Mark Cave-Ayland wrote:
On 31/05/2022 22:49, Daniel Henrique Barboza wrote:
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until now, has no additional attributes.
The main di
On Apr 19 07:20, Wertenbroek Rick wrote:
> Adds the optional -cmbdev= option that takes a QEMU memory backend
> -object to be used to for the CMB (Controller Memory Buffer).
> This option takes precedence over cmb_size_mb= if both used.
> (The size will be deduced from the memory backend option).
>
On May 12 11:30, Klaus Jensen wrote:
> From: Klaus Jensen
>
> The internally maintained AEN mask is not cleared on reset. Fix this.
>
> Signed-off-by: Klaus Jensen
> ---
> hw/nvme/ctrl.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
> index 1e6e0fcad
On 6/2/22 04:56, Mark Cave-Ayland wrote:
On 31/05/2022 22:49, Daniel Henrique Barboza wrote:
We need a handful of changes that needs to be done in a single swoop to
turn PnvPHB3 into a PnvPHB backend.
In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and
will hold the PCI bu
From: Klaus Jensen
This reverts commit d97eee64fef35655bd06f5c44a07fdb83a6274ae.
The emulated controller correctly accounts for not including bit buckets
in the controller-to-host data transfer, however it doesn't correctly
account for the holes for the on-disk data offsets.
Reported-by: Keith
On Jun 1 15:28, Lukasz Maniak wrote:
> On Wed, May 25, 2022 at 09:35:24AM +0200, Klaus Jensen wrote:
> >
> > +stl_le_p(&n->bar.intms, 0);
> > +stl_le_p(&n->bar.intmc, 0);
> > +stl_le_p(&n->bar.cc, 0);
>
> Looks fine, though it seems the NVMe spec says the above registers
From: Klaus Jensen
Since version 5.2 commit 6eb7a071292a ("hw/block/nvme: change controller
pci id"), the emulated NVMe controller has defaulted to a non-Intel PCI
identifier.
Deprecate the compatibility parameter so we can get rid of it once and
for all.
Reviewed-by: Philippe Mathieu-Daudé
Si
From: Klaus Jensen
The Linux kernel quirks the QEMU NVMe controller pretty heavily because
of the namespace identifier mess. Since this is now fixed, bump the
firmware revision number to allow the quirk to be disabled for this
revision.
As of now, bump the firmware revision number to be equal to
On Jun 3 13:14, Jonathan Derrick wrote:
> When metadata is present in the namespace and deallocates are issued, the
> first
> deallocate could fail to zero the block range, resulting in another
> deallocation to be issued. Normally after the deallocation completes and the
> range is checked for z
From: Klaus Jensen
Do not report the "null uuid" (all zeros) in the namespace
identification descriptors.
Reported-by: Luis Chamberlain
Reported-by: Christoph Hellwig
Reviewed-by: Christoph Hellwig
Reviewed-by: Keith Busch
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 17 +++
From: Klaus Jensen
Do not default to generate an UUID for namespaces if it is not
explicitly specified.
This is a technically a breaking change in behavior. However, since the
UUID changes on every VM launch, it is not spec compliant and is of
little use since the UUID cannot be used reliably an
From: Dmitry Tikhov
NVMe command set specification for end-to-end data protection formatted
namespace states:
o If the Reference Tag Check bit of the PRCHK field is set to ‘1’ and
the namespace is formatted for Type 3 protection, then the
controller:
▪ should not compar
From: Klaus Jensen
Pass the right constant to nvme_smart_event(). The NVME_AER* values hold
the bit position in the SMART byte, not the shifted value that we expect
it to be in nvme_smart_event().
Fixes: c62720f137df ("hw/block/nvme: trigger async event during injecting smart
warning")
Acked-by
From: Dmitry Tikhov
Since there is no return after nvme_dsm_cb invocation, metadata
associated with non-zero block range is currently zeroed. Also this
behaviour leads to segfault since we schedule iocb->bh two times.
First when entering nvme_dsm_cb with iocb->idx == iocb->nr and
second because o
From: Klaus Jensen
The Identify Controller Serial Number (SN) is the serial number for the
NVM subsystem and must be the same across all controller in the NVM
subsystem.
Enforce this.
Reviewed-by: Christoph Hellwig
Reviewed-by: Keith Busch
Signed-off-by: Klaus Jensen
---
hw/nvme/nvme.h |
From: Klaus Jensen
We cannot provide auto-generated unique or persistent namespace
identifiers (EUI64, NGUID, UUID) easily. Since 6.1, namespaces have been
assigned a generated EUI64 of the form "52:54:00:".
This is will be unique within a QEMU instance, but not globally.
Revert that this is ass
From: Dmitry Tikhov
Since nlbas is of type int, it does not work with large namespace size
values, e.g., 9 TB size of file backing namespace and 8 byte metadata
with 4096 bytes lbasz gives negative nlbas value, which is later
promoted to negative int64_t type value and results in negative
ns->mof
From: Klaus Jensen
Hi Peter,
The following changes since commit 70e975203f366f2f30daaeb714bb852562b7b72f:
Merge tag 'pull-request-2022-06-03' of https://gitlab.com/thuth/qemu into
staging (2022-06-03 06:43:38 -0700)
are available in the Git repository at:
git://git.infradead.org/qemu-nvm
From: Dmitry Tikhov
Current implementation have problem in the read part of copy command.
Because there is no metadata mangling before nvme_dif_check invocation,
reftag error could be thrown for blocks of namespace that have not been
previously written to.
Signed-off-by: Dmitry Tikhov
Reviewed-
On Fri, Jun 03, 2022 at 01:14:40PM -0600, Jonathan Derrick wrote:
> When metadata is present in the namespace and deallocates are issued, the
> first
> deallocate could fail to zero the block range, resulting in another
> deallocation to be issued. Normally after the deallocation completes and the
During the previous changesets piix4_create() became a trivial
wrapper around more generic functions. Modernize the code.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/piix4.c| 13 -
hw/mips/malta.c | 5 -
include/h
During the previous changesets piix3_create() became a trivial
wrapper around more generic functions. Modernize the code.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i386/pc_piix.c | 6 +-
hw/isa/piix3.c| 13 -
include/
PCI interrupt wiring was performed in create() functions which are
obsolete. Move these tasks into QOM functions to modernize the code.
In order to avoid duplicate checking for xen_enabled() the realize
methods are now split.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c | 67 +
PCI interrupt wiring and device creation were performed in create()
functions which are obsolete. Move these tasks into QOM functions to
modernize the code.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/piix4.c | 30 ++
1 file changed
Reported-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/piix4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 9a6d981037..1d04fb6a55 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@
The pci_map_irq_fn was implemented below type_init() which made it
inaccessible to QOM functions. So move it up.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/piix3.c | 22 +++---
1 file changed, 11 insertions(+), 1
Just like the real hardware, create the PIIX4 ACPI controller as part of
the PIIX4 southbridge. This also mirrors how the IDE and USB functions
are already created.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c| 24 +---
hw/mips/malta.c | 5
Modernizes the code.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 3 ++-
hw/isa/piix3.c| 3 +--
include/hw/southbridge/piix.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/p
TYPE_PIIX3_PCI_DEVICE resides there as already, so add the remaining
ones, too.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/piix3.c| 3 ---
include/hw/isa/isa.h | 2 --
include/hw/southbridge/piix.h | 4 +
Modernizes the code.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/piix4.c| 6 +-
hw/mips/malta.c | 3 ++-
include/hw/southbridge/piix.h | 2 +-
3 files changed, 4 insertions(+), 7 deletions(-)
di
The pci_map_irq_fn was implemented below type_init() which made it
inaccessible to QOM functions. So move it up.
Signed-off-by: Bernhard Beschow
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/piix4.c | 50 +-
1 file
v4:
* Rebase onto
https://patchew.org/QEMU/20220530112718.26582-1-philippe.mathieu.da...@gmail.com/
* Cosmetics (fix typo, omit "include") (Mark, Philippe)
* Split piix3 and piix4 (Philippe)
* s/Found-by/Reported-by/ (Philippe)
* Don't alias smbus (Mark)
v3:
* Rebase onto 'hw/acpi/piix4: remove l
On 5/25/22 06:49, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Based on already existing QEMU implementation, created an unsigned 256
bit by 128 bit division needed to implement the vector divide extended
unsigned instruction from PowerISA3.1
Signed-off-by: Lucas Ma
On 5/25/22 06:49, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vmodsw: Vector Modulo Signed Word
vmoduw: Vector Modulo Unsigned Word
vmodsd: Vector Modulo Signed Doubleword
vmodud: Vector Modulo Unsigned Doubleword
On 5/25/22 06:49, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivesw: Vector Divide Extended Signed Word
vdiveuw: Vector Divide Extended Unsigned Word
Signed-off-by: Lucas Mateus Castro (alqotel)
---
target/ppc
On 5/25/22 06:49, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivsw: Vector Divide Signed Word
vdivuw: Vector Divide Unsigned Word
vdivsd: Vector Divide Signed Doubleword
vdivud: Vector Divide Unsigned Doubleword
On Jun 3, 2022, at 11:34 AM, Yu Zhang
mailto:yu.zh...@ionos.com>> wrote:
Hello Dongli, Elena, John, and Jagannathan,
I'm interested in the "multi-process QEMU" feature and got the kind reply by
Mr. Vivier that I may contact you for this.
On one of the QEMU docs [1] I saw the command line:
+
On 03/06/2022 19.26, Claudio Fontana wrote:
On 6/3/22 18:42, Thomas Huth wrote:
The disassembly via capstone should be superiour to our old vixl
sources nowadays, so let's finally cut this old disassembler out
of the QEMU source tree.
Signed-off-by: Thomas Huth
agreed, one thought: at the ti
On 6/3/22 09:42, Thomas Huth wrote:
The disassembly via capstone should be superiour to our old vixl
sources nowadays, so let's finally cut this old disassembler out
of the QEMU source tree.
Signed-off-by: Thomas Huth
---
See also the discussions here:
- https://lists.gnu.org/archive/html/q
Am 14.03.2022 um 14:37 hat Emanuele Giuseppe Esposito geschrieben:
> From: Paolo Bonzini
>
> We want to make sure access of job->aio_context is always done
> under either BQL or job_mutex. The problem is that using
> aio_co_enter(job->aiocontext, job->co) in job_start and job_enter_cond
> makes t
On 6/1/22 03:25, Xiaojuan Yang wrote:
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c | 45 +++-
1 file changed, 44 insertions(+), 1 deletion(-)
Acked-by: Richard Henderson
+#define PM_BASE 0x1008
+#define PM_SIZ
On 6/1/22 03:25, Xiaojuan Yang wrote:
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
MAINTAINERS| 1 +
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 3 +
hw/rtc/Kconfig | 3 +
hw/rtc/ls
Am 14.03.2022 um 14:36 hat Emanuele Giuseppe Esposito geschrieben:
> Introduce the job locking mechanism through the whole job API,
> following the comments in job.h and requirements of job-monitor
> (like the functions in job-qmp.c, assume lock is held) and
> job-driver (like in mirror.c and all
On 6/1/22 03:25, Xiaojuan Yang wrote:
+static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
+{
+LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+unsigned long offset = addr & 0x;
+uint32_t index, cpu, ret = 0;
+
+switch (offset) {
+case EXTIOI_NODETYPE_STA
On 03/06/2022 18.17, Richard Henderson wrote:
On 6/3/22 05:48, Thomas Huth wrote:
The job definitions recently got a second "variables:" section by
accident and thus are failing now if one tries to run them. Merge
the two sections into one again to fix the issue.
And while we're at it, bump the
Am 14.03.2022 um 14:36 hat Emanuele Giuseppe Esposito geschrieben:
> In preparation to the job_lock/unlock usage, create _locked
> duplicates of some functions, since they will be sometimes called with
> job_mutex held (mostly within job.c),
> and sometimes without (mostly from JobDrivers using the
On an additional note, my changes are not backward compatible with
older compiler. The build will break when built with a centos 7
docker/vm/host:
/home/anisinha/workspace/bits/build/grub/grub-core/contrib-deps/python/Modules/_ctypes/_ctypes.c:
In function '_build_callargs':
/home/anisinha/workspa
On 6/3/22 05:48, Thomas Huth wrote:
The job definitions recently got a second "variables:" section by
accident and thus are failing now if one tries to run them. Merge
the two sections into one again to fix the issue.
And while we're at it, bump the timeout here (70 minutes are currently
not eno
Accesses to henvcfg, henvcfgh and senvcfg are allowed
only if corresponding bit in mstateen0/hstateen0 is
enabled. Otherwise an illegal instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 84 ++
1 file changed, 78 in
If smstateen is implemented then accesses to AIA
registers CSRS, IMSIC CSRs and other IMSIC registers
is controlled by setting of corresponding bits in
mstateen/hstateen registers. Otherwise an illegal
instruction trap or virtual instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
---
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.c | 2 +
This series adds support for the Smstateen specification which provides
a mechanism plug potential covert channels which are opened by extensions
that add to processor state that may not get context-switched. Currently
access to AIA registers, *envcfg registers and floating point(fcsr) is
controlle
If smstateen is implemented and sstateen0.fcsr is clear
then the floating point operations must return illegal
instruction exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 24
1 file changed, 24 insertions(+)
diff --git a/target/riscv/csr.c b/target/r
Am 14.03.2022 um 14:36 hat Emanuele Giuseppe Esposito geschrieben:
> Categorize the fields in struct Job to understand which ones
> need to be protected by the job mutex and which don't.
>
> Signed-off-by: Emanuele Giuseppe Esposito
I suppose it might be a result of moving things back and forth
Hello Dongli, Elena, John, and Jagannathan,
I'm interested in the "multi-process QEMU" feature and got the kind reply
by Mr. Vivier that I may contact you for this.
On one of the QEMU docs [1] I saw the command line:
+ /usr/bin/qemu-system-x86_64\
+
On 6/3/22 08:05, Andrew Jones wrote:
On Fri, Jun 03, 2022 at 06:56:41AM -0700, Richard Henderson wrote:
On 6/3/22 02:25, Andrew Jones wrote:
The max cpu type is the best default cpu type for tests to use
when specifying the cpu type for AArch64 mach-virt. Switch all
tests to it.
This won't wo
On 6/2/22 23:58, Thomas Huth wrote:
The following changes since commit 1e62a82574fc28e64deca589a23cf55ada2e1a7d:
Merge tag 'm68k-for-7.1-pull-request' of https://github.com/vivier/qemu-m68k
into staging (2022-06-02 06:30:24 -0700)
are available in the Git repository at:
https://gitlab.c
On Fri, Jun 03, 2022 at 07:04:01AM -0700, Richard Henderson wrote:
> On 6/3/22 04:18, Andrew Jones wrote:
> > The max cpu type is the best default cpu type for tests to use
> > when specifying the cpu type for AArch64 mach-virt. Switch all
> > tests to it.
> >
> > Cc: Alex Bennée
> > Signed-off-b
On 03/06/2022 15.48, Richard Henderson wrote:
On 6/2/22 22:21, Thomas Huth wrote:
So is capstone disassembly better now with Ubuntu 20.04 or should we still
revert the submodule removal?
It's better, yes. At least it's giving me disassembly of the system registers.
Also, if libvixl is so ba
On Fri, Jun 03, 2022 at 06:56:41AM -0700, Richard Henderson wrote:
> On 6/3/22 02:25, Andrew Jones wrote:
> > The max cpu type is the best default cpu type for tests to use
> > when specifying the cpu type for AArch64 mach-virt. Switch all
> > tests to it.
>
> This won't work without further chang
On 6/1/22 05:53, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
The extract64 arguments are not endian dependent as they are only used
for bitwise operations. The current behavior in little-endian hosts is
correct; since the indexes in VRB are in PowerISA-ordering, we should
always inv
On 6/3/22 04:18, Andrew Jones wrote:
The max cpu type is the best default cpu type for tests to use
when specifying the cpu type for AArch64 mach-virt. Switch all
tests to it.
Cc: Alex Bennée
Signed-off-by: Andrew Jones
For avoidance of doubt, copying v1 comment to v2:
diff --git a/tests/a
On 6/3/22 02:25, Andrew Jones wrote:
The max cpu type is the best default cpu type for tests to use
when specifying the cpu type for AArch64 mach-virt. Switch all
tests to it.
This won't work without further changes.
@@ -147,7 +147,7 @@ def test_aarch64_virt(self):
"""
:av
On 6/3/22 7:18 PM, Andrew Jones wrote:
The max cpu type is the best default cpu type for tests to use
when specifying the cpu type for AArch64 mach-virt. Switch all
tests to it.
Cc: Alex Bennée
Signed-off-by: Andrew Jones
---
tests/avocado/boot_xen.py | 6 +++---
tests/avocado/rep
On 6/2/22 22:21, Thomas Huth wrote:
So is capstone disassembly better now with Ubuntu 20.04 or should we still revert the
submodule removal?
It's better, yes. At least it's giving me disassembly of the system registers.
Also, if libvixl is so bad, why do we still have that in the repo?
Wel
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