On Tue, May 24, 2022 at 01:49:41PM +0200, Dario Faggioli wrote:
> Hello! Sorry for bringing up an old thread, but I'd have a question
> about this series.
>
> As far as I can see, the patches were fine, and they were Acked, but
> then the series was never committed... Is this correct?
>
> If yes,
Dario Faggioli writes:
> [[PGP Signed Part:Undecided]]
> On Mon, 2022-05-23 at 19:19 +, Dario Faggioli wrote:
>> As soon as I get rid of _both_ "-flto=auto" _and_ "--enable-lto", the
>> above tests seem to work fine.
>>
>> When they fail, they fail immediately, while creating the graph, li
On 5/25/22 07:34, Jamin Lin wrote:
1. replace HWADDR_PRIx with PRIx64
2. fix indent issue
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/gpio/aspeed_gpio.c | 8
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 5 insertions(+), 5 del
On 5/25/22 07:34, Jamin Lin wrote:
AST1030 integrates one set of Parallel GPIO Controller
with maximum 151 control pins, which are 21 groups
(A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4
S5 S6 S7 ) and the group T and U are input only.
Signed-off-by: Jamin Lin
Reviewed-by: Cédr
The 05/11/2022 06:14, Cédric Le Goater wrote:
Hi Cerdic,
> Hello Jamin,
>
> (Adding a few people that could help with the review)
>
> On 3/21/22 10:14, Jamin Lin wrote:
>
> > 1. Add GPIO read/write trace event.
>
> Do we really need the "DEVICE(s)->canonical_path" parameter ?
> That would be pa
AST1030 integrates one set of Parallel GPIO Controller
with maximum 151 control pins, which are 21 groups
(A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4
S5 S6 S7 ) and the group T and U are input only.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast10x0.c | 11 +++
hw/gpio/a
1. replace HWADDR_PRIx with PRIx64
2. fix indent issue
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 8
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index c834bf19f5..a62
-v2 changes
Create separate patches to support the following features
1. Add GPIO read/write trace event.
2. Support GPIO index mode for write operation.
It did not support GPIO index mode for read operation.
3. AST1030 integrates one set of Parallel GPIO Controller
with maximum 151 control pins,
It did not support GPIO index mode for read operation.
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 168 ++
include/hw/gpio/aspeed_gpio.h | 14 +++
2 files changed, 182 insertions(+)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
inde
Add GPIO read/write trace event for aspeed model.
Signed-off-by: Jamin Lin
---
hw/gpio/aspeed_gpio.c | 54 +++
hw/gpio/trace-events | 5
2 files changed, 44 insertions(+), 15 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
i
On Tue, May 24, 2022 at 10:03:02PM +0800, Chenyi Qiang wrote:
> There are cases that malicious virtual machine can cause CPU stuck (due
> to event windows don't open up), e.g., infinite loop in microcode when
> nested #AC (CVE-2015-5307). No event window means no event (NMI, SMI and
> IRQ) can be d
On 5/24/22 17:44, yangxiaojuan wrote:
在 2022/5/25 6:41, Richard Henderson 写道:
On 5/24/22 15:32, Richard Henderson wrote:
When the syntax errors are fixed, it does not pass "make check".
When I configure with --enable-debug --enable-sanitizers I get
I got the same error.
The 'make check '
On 5/24/22 15:44, Alistair Francis wrote:
From: Alistair Francis
The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d:
Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into
staging (2022-05-20 08:04:30 -0700)
are available in the Git repository a
在 2022/5/25 6:41, Richard Henderson 写道:
On 5/24/22 15:32, Richard Henderson wrote:
When the syntax errors are fixed, it does not pass "make check".
When I configure with --enable-debug --enable-sanitizers I get
I got the same error.
The 'make check ' result:
Summary of Failures:
95/117
Hi, Richard
在 2022/5/25 6:32, Richard Henderson 写道:
On 5/24/22 01:17, Xiaojuan Yang wrote:
Hi All,
As this series only supports running binary files in ELF format, and
does not depend on BIOS and kernel file. so this series are changed
from RFC to patch vX.
The manual:
-
https://github
On 5/25/22 03:35, Sean Christopherson wrote:
On Fri, May 20, 2022, zhenwei pi wrote:
@@ -59,6 +60,12 @@ enum virtio_balloon_config_read {
VIRTIO_BALLOON_CONFIG_READ_CMD_ID = 0,
};
+/* the request body to commucate with host side */
+struct __virtio_balloon_recover {
+ stru
On 5/24/2022 3:48 PM, Moger, Babu wrote:
On 5/24/22 10:19, Igor Mammedov wrote:
On Tue, 24 May 2022 11:10:18 -0400
Igor Mammedov wrote:
CCing AMD folks as that might be of interest to them
I am trying to recreate the bug on my AMD system here.. Seeing this message..
qemu-system-x86_64: -nu
From: Bin Meng
VxWorks 7 uses the same boot interface as the Linux kernel on Arm
(64-bit only), PowerPC and RISC-V architectures. Add logic to set
is_linux to true for VxWorks uImage for these architectures in
load_uboot_image().
Signed-off-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Revi
From: Bin Meng
Sync uboot_image.h from upstream U-Boot v2022.01 release [1].
[1] https://source.denx.de/u-boot/u-boot/-/blob/v2022.01/include/image.h
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220324134812.541274-1-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
From: Tsukasa OI
QEMU allowed inconsistent configurations that made floating point
arithmetic effectively unusable.
This commit adds certain checks for consistent FP arithmetic:
- F requires Zicsr
- Zfinx requires Zicsr
- Zfh/Zfhmin require F
- D requires F
- V requires D
Because F/D
From: "Hongren (Zenithal) Zheng"
Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.
Signed-off-by: Hongren (Zenithal) Zheng
Tested-by: Jiatai He
Reviewed-by: Alistair Francis
Message-Id:
Signed-off-b
From: Anup Patel
When both APLIC and IMSIC are present in virt machine, the APLIC should
be used as parent interrupt controller for dynamic platform devices.
In case of multiple sockets, we should prefer interrupt controller of
socket0 for dynamic platform devices.
Fixes: 3029fab64309 ("hw/ris
From: Anup Patel
When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.
Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode")
Signed-off-by: Anup Patel
Revie
From: Bernhard Beschow
The QOM API already provides getters for uint64 and uint32 values, so reuse
them.
Signed-off-by: Bernhard Beschow
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220301225220.239065-2-shen...@gmail.com>
Signed-off-by: Alistair Francis
-
From: Tsukasa OI
Because ext_? members are boolean variables, operator `&&' should be
used instead of `&'.
Signed-off-by: Tsukasa OI
Reviewed-by: Alistair Francis
Reviewed-by: Víctor Colombo
Message-Id:
<91633f8349253656dd08bc8dc36498a9c7538b10.1652583332.git.research_tra...@irq.a4lg.com>
Si
From: Frank Chang
"mimpid" cpu option was mistyped to "mipid".
Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid
CSR values")
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20220523153147.15371-1-frank.ch...@sifive.com>
Signed-off-by: Alist
From: Tsukasa OI
On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei".
Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to
be (virtually) enabled as well, it should be safe to change its expansion.
Signed-off-by: Tsukasa OI
Reviewed-by: Alistair Francis
From: Weiwei Li
- setting ext_g will implicitly set ext_i
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id: <20220518012611.6772-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 24
1 fil
From: Tsukasa OI
If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system). This kind of error handling should be used only when a serious
runtime error occurs.
This commit makes error handling on CPU conf
From: Tsukasa OI
If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system). This kind of error handling should be used only when a serious
runtime error occurs.
This commit makes error handling on CPU conf
From: Bernhard Beschow
The QOM API already provides accessors for uint32 values, so reuse them.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-Id: <20220301225220.239065-3-shen...@gmail.com>
Signed-off-by: Alistair Francis
---
hw/ri
From: Tsukasa OI
Because some operating systems don't correctly parse long ISA extension
string, this commit adds short-isa-string boolean option to disable
generating long ISA extension strings on Device Tree.
For instance, enabling Zfinx and Zdinx extensions and booting Linux (5.17 or
earlier)
From: Tsukasa OI
This commit moves ISA string conversion for Zhinx and Zhinxmin extensions.
Because extension category ordering of "H" is going to be after "V",
their ordering is going to be valid (on canonical order).
Signed-off-by: Tsukasa OI
Acked-by: Alistair Francis
Message-Id:
<7a988aed
From: Anup Patel
Currently, the [m|s]tval CSRs are set with trapping instruction encoding
only for illegal instruction traps taken at the time of instruction
decoding.
In RISC-V world, a valid instructions might also trap as illegal or
virtual instruction based to trapping bits in various CSRs (
From: Tsukasa OI
We should separate "check" and "configure" steps as possible.
This commit separates both steps except vector/Zfinx-related checks.
Signed-off-by: Tsukasa OI
Reviewed-by: Alistair Francis
Message-Id:
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 31 ++
From: eopXD
Vector whole register load instructions have EEW encoded in the opcode,
so we shouldn't take SEW here. Vector whole register store instructions
are always EEW=8.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Acked-by: Alistair Francis
Message-Id: <165181414065.18540.14828125053
From: Atish Patra
timecmp update function should be invoked with hartid for which
timecmp is being updated. The following patch passes the incorrect
hartid to the update function.
Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")
Signed-off-by: Atish Patra
Review
From: Anup Patel
Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.
This patch updates riscv_cpu_do_interrupt() to fix the above issue.
Fixes: 86d0c457396b ("target/riscv: Fix
From: Tsukasa OI
Because "G" virtual extension expands to "IMAFD", we cannot separately
disable extensions like "F" or "D" without disabling "G". Because all
"IMAFD" are enabled by default, it's harmless to disable "G" by default.
Signed-off-by: Tsukasa OI
Reviewed-by: Alistair Francis
Messag
From: Dylan Reid
VS mode access to hypervisor CSRs should generate virtual, not illegal,
instruction exceptions.
Don't return early and indicate an illegal instruction exception when
accessing a hypervisor CSR from VS mode. Instead, fall through to the
`hmode` predicate to return the correct vir
From: Alistair Francis
The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d:
Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into
staging (2022-05-20 08:04:30 -0700)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tag
On 5/24/22 15:32, Richard Henderson wrote:
When the syntax errors are fixed, it does not pass "make check".
When I configure with --enable-debug --enable-sanitizers I get
$ QTEST_QEMU_BINARY='./qemu-system-loongarch64'
./tests/qtest/device-introspect-test -v
...
# Testing device 'loongarch_ip
On 5/24/22 01:17, Xiaojuan Yang wrote:
Hi All,
As this series only supports running binary files in ELF format, and
does not depend on BIOS and kernel file. so this series are changed from RFC to
patch vX.
The manual:
- https://github.com/loongson/LoongArch-Documentation/releases/tag/2022.
On Thu, May 12, 2022 at 12:47 AM Anup Patel wrote:
>
> This series does fixes and improvements to have nested virtualization
> on QEMU RISC-V.
>
> These patches can also be found in riscv_nested_fixes_v2 branch at:
> https://github.com/avpatel/qemu.git
>
> The RISC-V nested virtualization was test
Four tests are added for preempt mode:
- Postcopy plain
- Postcopy recovery
- Postcopy tls
- Postcopy tls+recovery
Signed-off-by: Peter Xu
---
tests/qtest/migration-test.c | 58
1 file changed, 58 insertions(+)
diff --git a/tests/qtest/migration-tes
We just added TLS tests for precopy but not postcopy. Add the
corresponding test for vanilla postcopy.
Rename the vanilla postcopy to "postcopy/plain" because all postcopy tests
will only use unix sockets as channel.
Signed-off-by: Peter Xu
---
tests/qtest/migration-test.c | 61 +++
To allow postcopy recovery, the ram fast load (preempt-only) dest QEMU thread
needs similar handling on fault tolerance. When ram_load_postcopy() fails,
instead of stopping the thread it halts with a semaphore, preparing to be
kicked again when recovery is detected.
A mutex is introduced to make
This patch enables postcopy-preempt feature.
It contains two major changes to the migration logic:
(1) Postcopy requests are now sent via a different socket from precopy
background migration stream, so as to be isolated from very high page
request delays.
(2) For huge page enabled hosts:
This patch is based on the async preempt channel creation. It continues
wiring up the new channel with TLS handshake to destionation when enabled.
Note that only the src QEMU needs such operation; the dest QEMU does not
need any change for TLS support due to the fact that all channels are
establi
With preemption mode on, when we see a postcopy request that was requesting
for exactly the page that we have preempted before (so we've partially sent
the page already via PRECOPY channel and it got preempted by another
postcopy request), currently we drop the request so that after all the
other p
It's easy to build this upon the postcopy tls test. Rename the old
postcopy recovery test to postcopy/recovery/plain.
Signed-off-by: Peter Xu
---
tests/qtest/migration-test.c | 38 +++-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/mi
So that it can be used in postcopy tests too soon.
Signed-off-by: Peter Xu
---
tests/qtest/migration-test.c | 144 +--
1 file changed, 72 insertions(+), 72 deletions(-)
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index d33e8060f9..cb5
Firstly, postcopy already preempts precopy due to the fact that we do
unqueue_page() first before looking into dirty bits.
However that's not enough, e.g., when there're host huge page enabled, when
sending a precopy huge page, a postcopy request needs to wait until the whole
huge page that is sen
Add a property field that can conditionally disable the "break sending huge
page" behavior in postcopy preemption. By default it's enabled.
It should only be used for debugging purposes, and we should never remove
the "x-" prefix.
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Manish Mishra
It's useful for specifying tls credentials all in the cmdline (along with
the -object tls-creds-*), especially for debugging purpose.
The trick here is we must remember to not free these fields again in the
finalize() function of migration object, otherwise it'll cause double-free.
The thing is w
This patch allows the postcopy preempt channel to be created
asynchronously. The benefit is that when the connection is slow, we won't
take the BQL (and potentially block all things like QMP) for a long time
without releasing.
A function postcopy_preempt_wait_channel() is introduced, allowing the
Add migrate_channel_requires_tls() to detect whether the specific channel
requires TLS, leveraging the recently introduced migrate_use_tls(). No
functional change intended.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
---
migration/channel.c | 9 ++---
migration/migration.
This is v7 of postcopy preempt series. It can also be found here:
https://github.com/xzpeter/qemu/tree/postcopy-preempt
RFC: https://lore.kernel.org/qemu-devel/20220119080929.39485-1-pet...@redhat.com
V1: https://lore.kernel.org/qemu-devel/20220216062809.57179-1-pet...@redhat.com
V2: https:/
Create a new socket for postcopy to be prepared to send postcopy requested
pages via this specific channel, so as to not get blocked by precopy pages.
A new thread is also created on dest qemu to receive data from this new channel
based on the ram_load_postcopy() routine.
The ram_load_postcopy(PO
On Tue, May 24, 2022 at 12:02:17PM +0100, Daniel P. Berrangé wrote:
> This removes one further custom impl of QEMUFile, in favour of a
> QIOChannel based impl.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> migration/ram.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
Reviewed
On Fri, May 20, 2022 at 09:59:22AM +0200, Fabian Ebner wrote:
> On 64-bit platforms, assigning SIZE_MAX to the int64_t max_pdiscard
> results in a negative value, and the following assertion would trigger
> down the line (it's not the same max_pdiscard, but computed from the
> other one):
> qemu-sy
On Tue, May 24, 2022 at 12:02:16PM +0100, Daniel P. Berrangé wrote:
> This is for code which needs a portable equivalent to a QIOChannelFile
> connected to /dev/null.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> include/io/channel-null.h | 55 +++
> io/channel-null.c
On Thu, May 19, 2022 at 03:48:36PM +0100, Alberto Faria wrote:
> For consistency with other I/O functions, and in preparation to
> implement bdrv_{pread,pwrite}() using generated_co_wrapper.
>
> unsigned int fits in int64_t, so all callers remain correct.
>
> Signed-off-by: Alberto Faria
> ---
>
On Thu, May 19, 2022 at 11:11:34AM +0100, Daniel P. Berrangé wrote:
> On Tue, May 17, 2022 at 03:57:28PM -0400, Peter Xu wrote:
> > We just added TLS tests for precopy but not postcopy. Add the
> > corresponding test for vanilla postcopy.
> >
> > Rename the vanilla postcopy to "postcopy/plain" be
On Tue, May 24, 2022 at 8:11 PM Konstantin Kostiuk wrote:
>
> There are 2 reason for the bump:
> - Fedora 33 is unsupported anymore
> - Some changes in the guest agent required updates of
>mingw-headers
>
> Signed-off-by: Konstantin Kostiuk
Reviewed-by: Marc-André Lureau
> ---
> tests/d
Tested-by: Jim Shu
On Fri, Mar 4, 2022 at 7:00 PM Damien Hedde
wrote:
>
>
>
> On 3/3/22 14:32, Philippe Mathieu-Daudé wrote:
> > On 23/2/22 10:12, Damien Hedde wrote:
> >> Hi Philippe,
> >>
> >> I suppose it is ok if I change your mail in the reviewed by ?
> >
> > No, the email is fine (git to
Tested-by: Jim Shu
On Thu, Mar 3, 2022 at 10:46 PM Philippe Mathieu-Daudé <
philippe.mathieu.da...@gmail.com> wrote:
> On 23/2/22 10:07, Damien Hedde wrote:
> > Allow plugging any sysbus device on this machine (the sysbus
> > devices still need to be 'user-creatable').
> >
> > This commit is nee
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:14 PM Damien Hedde
wrote:
> This device can be used to create a memory wrapped into a
> sysbus device.
> This device has one property 'readonly' which allows
> to choose between a ram or a rom.
>
> The purpose for this device is to be used with qapi
Tested-by: Jim Shu
On Fri, Mar 4, 2022 at 11:23 PM Philippe Mathieu-Daudé <
philippe.mathieu.da...@gmail.com> wrote:
> On 23/2/22 10:07, Damien Hedde wrote:
> > The devices are:
> > + ibex-timer
> > + ibex-uart
> > + riscv.aclint.swi
> > + riscv.aclint.mtimer
> > + riscv.hart_array
> > + riscv.s
Tested-by: Jim Shu
On Fri, Mar 4, 2022 at 12:36 AM Damien Hedde
wrote:
>
>
> On 3/3/22 15:41, Philippe Mathieu-Daudé wrote:
> > On 23/2/22 10:07, Damien Hedde wrote:
> >> Add the property to configure a the base address of the ram.
> >> The default value remains zero.
> >>
> >> This commit is n
On 22-05-20 18:01:28, Jonathan Cameron wrote:
> As the only I2C emulation in QEMU that supports being both
> a master and a slave, suitable for MCTP over i2c is aspeed-i2c
> add this controller to the arm virt model and hook up our new
> i2c_mctp_cxl_fmapi device.
>
> The current Linux driver for
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:37 PM Damien Hedde
wrote:
> This command allows to map an mmio region of sysbus device onto
> the system memory. Its behavior mimics the sysbus_mmio_map()
> function apart from the automatic unmap (the C function unmaps
> the region if it is already
On Mon, 2022-05-23 at 19:19 +, Dario Faggioli wrote:
> As soon as I get rid of _both_ "-flto=auto" _and_ "--enable-lto", the
> above tests seem to work fine.
>
> When they fail, they fail immediately, while creating the graph, like
> this:
>
> MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:59 PM Damien Hedde
wrote:
> The none machine was using the parent state structure.
> We'll need a custom state to add a field in the following commit.
>
> Signed-off-by: Damien Hedde
> ---
> hw/core/null-machine.c | 24 ++--
> 1
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:18 PM Damien Hedde
wrote:
> rom_set_order_override() and rom_reset_order_override() were called
> in qemu_create_cli_devices() to set the rom_order_override value
> once and for all when creating the devices added on CLI.
>
> Unfortunately this won't
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:36 PM Damien Hedde
wrote:
> phase_until() now supports the following transitions:
> + accel-created -> machine-initialized
> + machine-initialized -> machine-ready
>
> As a consequence we can now support the use of qmp_exit_preconfig()
> from phases
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:41 PM Damien Hedde
wrote:
> phase_until() is implemented in vl.c and is meant to be used
> to make startup progress up to a specified phase being reached().
> At this point, no behavior change is introduced: phase_until()
> only supports a single do
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:37 PM Damien Hedde
wrote:
> Instead of checking the phase everytime, just store the result
> in a flag. We will use more of it in the following commit.
>
> Signed-off-by: Damien Hedde
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> softmmu/qdev-mon
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:37 PM Damien Hedde
wrote:
> From: Mirela Grujic
>
> This commit allows to use the QMP command to add a cold-plugged
> device like we can do with the CLI option -device.
>
> Note: for device_add command in qdev.json adding the 'allow-preconfig'
> op
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:41 PM Damien Hedde
wrote:
> phase_get() returns the current phase, we'll use it in next
> commit.
>
> Signed-off-by: Damien Hedde
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> include/hw/qdev-core.h | 19 +++
> hw/core/qdev.c
Hi all,
Thanks for the work!
I'm from SiFive and we are very interested in this feature.
QMP/QAPI configurable QEMU machine is a useful feature in our use case.
With this feature, we can both model our versatile FPGA-based platforms
more easily and model a new platform without modification of sou
On 5/24/22 10:19, Igor Mammedov wrote:
> On Tue, 24 May 2022 11:10:18 -0400
> Igor Mammedov wrote:
>
> CCing AMD folks as that might be of interest to them
I am trying to recreate the bug on my AMD system here.. Seeing this message..
qemu-system-x86_64: -numa node,nodeid=0,memdev=ram-node0: me
On 5/19/22 17:19, Konstantin Khlebnikov wrote:
Repalce virtio_error() with macro which forms structured Error and
reports it as device runtime-error in addition to present actions.
Signed-off-by: Konstantin Khlebnikov
---
hw/virtio/virtio.c |9 +++--
include/hw/virtio/virtio.
On Fri, May 20, 2022, zhenwei pi wrote:
> @@ -59,6 +60,12 @@ enum virtio_balloon_config_read {
> VIRTIO_BALLOON_CONFIG_READ_CMD_ID = 0,
> };
>
> +/* the request body to commucate with host side */
> +struct __virtio_balloon_recover {
> + struct virtio_balloon_recover vbr;
> + __vir
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> From: Mark Kanda
>
> Add an HMP command to retrieve statistics collected at run-time.
> The command will retrieve and print either all VM-level statistics,
> or all vCPU-level statistics for the currently selected CPU.
>
> Signed-off-by: Paolo Bonzi
Use the associated kvm ioctl operation to enable adapter event notification
and forwarding for devices when requested. This feature will be set up
with or without firmware assist based upon the 'forwarding_assist' setting.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-bus.c | 20 +
First, cover letter is absent. Konstantin, could you please provide a
description what the whole series does?
Second, add maintainers to CC:
+Micheal
+Eric
+Markus
On 5/19/22 17:19, Konstantin Khlebnikov wrote:
This event represents device runtime errors to give time and
reason why device is b
Let's use the reserved pool of simulated PCI groups to allow intercept
devices to have separate groups from interpreted devices as some group
values may be different. If we run out of simulated PCI groups, subsequent
intercept devices just get the default group.
Furthermore, if we encounter any PCI
Lack of MSI-X support is not an issue for interpreted passthrough
devices, so let's let these in. This will allow, for example, ISM
devices to be passed through -- but only when interpretation is
available and being used.
Reviewed-by: Thomas Huth
Reviewed-by: Pierre Morel
Signed-off-by: Matthew
If the appropriate CPU facilty is available as well as the necessary
ZPCI_OP ioctl, then the underlying KVM host will enable load/store
intepretation for any guest device without a SHM bit in the guest
function handle. For a device that will be using interpretation
support, ensure the guest functi
The maximum supported store block length might be different depending
on whether the instruction is interpretively executed (firmware-reported
maximum) or handled via userspace intercept (host kernel API maximum).
Choose the best available value during group creation.
Reviewed-by: Pierre Morel
Si
For QEMU, the majority of the work in enabling instruction interpretation
is handled via SHM bit settings (to indicate to firmware whether or not
interpretive execution facilities are to be used) + a new KVM ioctl is
used to setup firmware-interpreted forwarding of Adapter Event
Notification
In order to interface with the underlying host zPCI device, we need
to know it's function handle. Add a routine to grab this from the
vfio CLP capabilities chain.
Reviewed-by: Pierre Morel
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-vfio.c | 83 ++--
The zpci-interp feature is used to specify whether zPCI interpretation is
to be used for this guest.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-virtio-ccw.c | 1 +
target/s390x/cpu_features_def.h.inc | 1 +
target/s390x/gen-features.c | 2 ++
target/s390x/kvm/kvm.c
This is a placeholder that pulls in unmerged kernel changes
required by this item. A proper header sync can be done once the
associated kernel code merges.
Signed-off-by: Matthew Rosato
---
linux-headers/asm-s390/kvm.h| 1 +
linux-headers/linux/kvm.h | 32
On 20.05.22 09:06, zhenwei pi wrote:
> Hi,
>
> I'm trying to recover hardware corrupted page by virtio balloon, the
> workflow of this feature like this:
>
> Guest 5.MF -> 6.RVQ FE10.Unpoison page
> / \/
> ---+
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 5/24/22 11:05, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Based-on: https://gitlab.com/danielhb/qemu/-/tree/ppc-next
This patch series is a patch series of the Matrix-Multiply Assist (MMA)
ins
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> From: Mark Kanda
>
> Add support for querying fd-based KVM stats - as introduced by Linux kernel
> commit:
>
> cb082bfab59a ("KVM: stats: Add fd-based API to read binary stats data")
>
> This allows the user to analyze the behavior of the VM withou
On Mon, May 23, 2022 at 11:56:14AM +0100, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > With preemption mode on, when we see a postcopy request that was requesting
> > for exactly the page that we have preempted before (so we've partially sent
> > the page already via PR
On 5/24/22 20:30, Emanuele Giuseppe Esposito wrote:
It seems that aio_wait_kick always required a memory barrier
or atomic operation in the caller, but nobody actually
took care of doing it.
Let's put the barrier in the function instead, and pair it
with another one in AIO_WAIT_WHILE. Read aio_w
1 - 100 of 347 matches
Mail list logo
