On Fri, Apr 29, 2022 at 01:17:05AM +0200, Paolo Bonzini wrote:
> On 4/27/22 16:35, Stefan Hajnoczi wrote:
> > This is typical for rx virtqueues where the device uses buffers when
> > some event occurs (e.g. a packet is received, an error condition
> > happens, etc).
> >
> > Polling non-empty virtq
On Fri, Apr 29, 2022 at 10:37:54AM +0200, Emanuele Giuseppe Esposito wrote:
> Am 28/04/2022 um 15:45 schrieb Stefan Hajnoczi:
> > On Tue, Apr 26, 2022 at 04:51:09AM -0400, Emanuele Giuseppe Esposito wrote:
> >> +static int has_writer;
> >
> > bool?
>
> Yes and no. With the latest findings and cur
On Sat, Apr 30, 2022 at 12:30 PM Anup Patel wrote:
> On Sat, Apr 30, 2022 at 8:39 AM Frank Chang
> wrote:
> >
> > Hi Anup,
> >
> > If we want to limit the generated ISA string to/after a specific
> privilege spec version.
> > Shouldn't we also check the privilege spec version when these extensio
On Fri, Apr 29, 2022 at 10:06:33AM +0200, Emanuele Giuseppe Esposito wrote:
>
>
> Am 28/04/2022 um 13:09 schrieb Stefan Hajnoczi:
> > On Tue, Apr 26, 2022 at 04:51:07AM -0400, Emanuele Giuseppe Esposito wrote:
> >> It seems that aio_wait_kick always required a memory barrier
> >> or atomic operat
On Thu, Apr 28, 2022 at 11:56:09PM +0200, Emanuele Giuseppe Esposito wrote:
>
>
> Am 28/04/2022 um 12:45 schrieb Stefan Hajnoczi:
> > On Wed, Apr 27, 2022 at 08:55:35AM +0200, Emanuele Giuseppe Esposito wrote:
> >>
> >>
> >> Am 26/04/2022 um 10:51 schrieb Emanuele Giuseppe Esposito:
> >>> Luckly,
On Sat, Apr 30, 2022 at 8:39 AM Frank Chang wrote:
>
> Hi Anup,
>
> If we want to limit the generated ISA string to/after a specific privilege
> spec version.
> Shouldn't we also check the privilege spec version when these extensions are
> enabled?
> Otherwise, it's possible that one extension i
On Wed, Apr 27, 2022 at 11:01:16AM +0100, Stefan Hajnoczi wrote:
> Commit 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend
> Program conventions for vhost-user-scsi") introduced fd-passing support
> as part of implementing the vhost-user backend program conventions.
>
> When fd passin
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:34 AM Anup Patel wrote:
> When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
> the riscv_csrrw_check() function should generate virtual instruction
> trap instead illegal instruction trap.
>
> Fixes: 533c91e8f22c ("target/riscv:
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:36 AM Anup Patel wrote:
> Currently, the [m|s]tval CSRs are set with trapping instruction encoding
> only for illegal instruction traps taken at the time of instruction
> decoding.
>
> In RISC-V world, a valid instructions might also trap as i
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:44 PM Anup Patel wrote:
> The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
> implementation that don't want to implement can simply have a dummy
> mcountinhibit which always zero.
>
> Fixes: a4b2fa433125 ("target/riscv: In
Hi Anup,
If we want to limit the generated ISA string to/after a specific privilege
spec version.
Shouldn't we also check the privilege spec version when these extensions
are enabled?
Otherwise, it's possible that one extension is enabled,
but the privilege spec version is smaller than the one in
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:41 PM Anup Patel wrote:
> The riscv_cpu_realize() sets priv spec verion to v1.12 when it is
> when "env->priv_ver == 0" (i.e. default v1.10) because the enum
> value of priv spec v1.10 is zero.
>
> Due to above issue, the sifive_u machine will
Hello Dave,
On Thu, Apr 28, 2022 at 1:20 PM Dr. David Alan Gilbert
wrote:
>
> Leo:
> Unfortunately this is failing a couple of CI tests; the MSG_ZEROCOPY
> one I guess is the simpler one; I think Stefanha managed to find the
> liburing fix for the __kernel_timespec case, but that looks like a b
On 4/28/2022 7:30 PM, Jason Wang wrote:
On Wed, Apr 27, 2022 at 5:09 PM Si-Wei Liu wrote:
On 4/27/2022 1:38 AM, Jason Wang wrote:
On Wed, Apr 27, 2022 at 4:30 PM Si-Wei Liu wrote:
On 4/26/2022 9:28 PM, Jason Wang wrote:
在 2022/3/30 14:33, Si-Wei Liu 写道:
Hi,
This patch series attempt
On 4/28/2022 7:24 PM, Jason Wang wrote:
On Fri, Apr 29, 2022 at 10:24 AM Jason Wang wrote:
在 2022/4/27 16:30, Si-Wei Liu 写道:
With MQ enabled vdpa device and non-MQ supporting guest e.g.
booting vdpa with mq=on over OVMF of single vqp, below assert
failure is seen:
../hw/virtio/vhost-vdpa.
On 4/28/2022 7:23 PM, Jason Wang wrote:
在 2022/4/27 16:30, Si-Wei Liu 写道:
With MQ enabled vdpa device and non-MQ supporting guest e.g.
booting vdpa with mq=on over OVMF of single vqp, below assert
failure is seen:
../hw/virtio/vhost-vdpa.c:560: vhost_vdpa_get_vq_index: Assertion
`idx >= de
On 4/29/22 08:22, Paolo Bonzini wrote:
The following changes since commit f22833602095b05733bceaddeb20f3edfced3c07:
Merge tag 'pull-target-arm-20220428' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-28
08:34:17 -0700)
are available in the Git repository at:
h
When CONFIG_MOS6522 is not set, building ppc64-softmmu target fails:
/usr/bin/ld: libqemu-ppc64-softmmu.fa.p/monitor_misc.c.o:(.data+0x1158):
undefined reference to `hmp_info_via'
clang-13: error: linker command failed with exit code 1 (use -v to see
invocation)
Add CONFIG_MOS6522 check
ailable in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220429
for you to fetch changes up to 325b7c4e7582c229d28c47123c3b986ed948eb84:
hw/riscv: Enable TPM backends (2022-04-29 10:4
Rob Landley writes:
> On 4/27/22 10:27, Thomas Huth wrote:
>> On 26/04/2022 12.26, Rob Landley wrote:
>>> When I cut and paste 80-ish characters of text into the Linux serial
>>> console, it
>>> reads 16 characters and stops. When I hit space, it reads another 16
>>> characters,
>>> and if I ke
When cache_info_passthrough is requested, QEMU passes the host values
of the cache information CPUID leaves down to the guest. However,
it blindly assumes that the CPUID leaf exists on the host, and this
cannot be guaranteed: for example, KVM has recently started to
synthesize AMD leaves up to 0x8
On Apple hosts we can read AppleSMC OSK key directly from host's
SMC and forward this value to QEMU Guest.
New 'hostosk' property is added:
* `-device isa-applesmc,hostosk=on`
The property is set to 'on' by default for machine version > 7.0
Apple licence allows use and run up to two additional co
Hi, I'm still figuring out how this should work in the future, but for
now I am just going to drop a manual note here on the mailing list
that points to a new merge request for qemu.qmp that adds preliminary
GitLab configuration:
https://gitlab.com/qemu-project/python-qemu-qmp/-/merge_requests/1
On Fri, Apr 29, 2022 at 10:12:01AM +0100, Joao Martins wrote:
> On 4/29/22 03:26, Jason Wang wrote:
> > On Fri, Apr 29, 2022 at 5:14 AM Joao Martins
> > wrote:
> >> @@ -3693,7 +3759,8 @@ static void vtd_init(IntelIOMMUState *s)
> >>
> >> /* TODO: read cap/ecap from host to decide which cap t
On 4/28/22 11:15, Ulrich Weigand wrote:
Richard Henderson wrote:
Create and record the two signal trampolines.
Use them when the guest does not use SA_RESTORER.
This patch caused a regression when running the wasmtime CI under qemu:
https://github.com/bytecodealliance/wasmtime/pull/4076
The
On 4/29/22 02:52, Damien Hedde wrote:
The following checks are missing:
+ for HFG[W/R]TR_EL2.SCXTNUM_EL0/1
We do not yet support FEAT_FGT.
+ HCR_EL2. when accessing SCXTNUM_EL1, but maybe these are always
guaranteed to fail because we don't support the features ?
+ HCR_EL2.NV whe
On 4/27/22 16:07, Peter Collingbourne wrote:
Currently the loader uses int as the return type for various APIs
that deal with file sizes, which leads to an error if the file
size is >=2GB, as it ends up being interpreted as a negative error
code. Furthermore, we do not tolerate short reads, which
On Fri, Apr 22, 2022 at 2:49 PM John Snow wrote:
>
> GitLab: https://gitlab.com/jsnow/qemu.qmp/-/commits/initial-checkin
>
> Hi, this series is part of an effort to publish the qemu.qmp package on
> PyPI. It is part of the second of three phases to complete this work:
>
> (1) Switch the new As
On 2022/04/30 0:20, Christian Schoenebeck wrote:
On Freitag, 29. April 2022 16:35:07 CEST Greg Kurz wrote:
On Fri, 29 Apr 2022 15:50:35 +0200
Christian Schoenebeck wrote:
On Freitag, 29. April 2022 14:56:50 CEST Greg Kurz wrote:
On Fri, 29 Apr 2022 12:25:11 +0200
Christian Schoenebeck wrot
Signed-off-by: Andrea Bolognani
---
qapi/block-core.json | 4
qapi/block.json | 1 -
qapi/char.json| 1 -
qapi/common.json | 2 --
qapi/control.json | 2 --
qapi/crypto.json | 1 -
qapi/machine.json | 2 --
qapi/migration.json | 7 ---
qapi/misc
Signed-off-by: Andrea Bolognani
---
qapi/block-core.json | 5 +
qapi/block.json | 1 +
qapi/crypto.json | 7 +++
qapi/machine.json| 1 +
qapi/migration.json | 4
5 files changed, 18 insertions(+)
diff --git a/qapi/block-core.json b/qapi/block-core.json
index b66494e8c5
The last patch could very reasonably be squashed into the previous
one, but since the changes could be considered more controversial I
thought it would be better if the two could be reviewed and judged
separately.
Andrea Bolognani (7):
qapi: Drop stray trailing symbol
qapi: Fix comment indenta
On Fri, Apr 29, 2022 at 11:16 PM Christian Schoenebeck
wrote:
>
> On Freitag, 29. April 2022 16:16:54 CEST Bin Meng wrote:
> > On Fri, Apr 29, 2022 at 9:48 PM Christian Schoenebeck
> >
> > wrote:
> > > On Freitag, 29. April 2022 15:29:15 CEST Greg Kurz wrote:
> > > > On Fri, 29 Apr 2022 21:19:51
The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which always zero.
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in
the CSR ops.")
Signed-off-by: Anup Patel
---
target/
Vertical alignment is sacrificed in the process.
Signed-off-by: Andrea Bolognani
---
qapi/block-core.json | 43 +--
qapi/block.json | 6 +++---
qapi/char.json | 6 +++---
qapi/control.json| 6 +++---
qapi/crypto.json | 32
Finish the conversion by moving all the definitions and the constraint
checks to meson_options.txt and meson.build respectively.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 82 ---
meson.build
Care was taken not to break vertical alignment.
Signed-off-by: Andrea Bolognani
---
qapi/block-core.json | 62 +-
qapi/block-export.json | 2 +-
qapi/block.json| 2 +-
qapi/char.json | 2 +-
qapi/control.json | 10 +++
qapi/cr
Cleanup to ease review of the conversion to meson. vhost_net_user and
vhost_net_vdpa are never assigned anything in the command line parsing
loop, so they are always equal to $vhost_user and $vhost_vdpa.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 17 ---
Signed-off-by: Andrea Bolognani
---
qapi/audio.json | 1 -
qapi/block-core.json | 11 ---
qapi/block.json | 3 ---
qapi/char.json | 1 -
qapi/control.json| 1 -
qapi/crypto.json | 12
qapi/job.json| 1 -
qapi/ma
This has no functional change, it only makes the command line shorter
and nicer.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 29 +
meson.build | 2 +-
meson_options.txt | 2 +-
3 files changed, 19 insertions(+), 14 dele
Meson allows directories such as "bindir" to be relative to the prefix. Right
now configure is forcing an absolute path, but that is not really necessary:
just make sure all uses of the directory variables are prefixed appropriately.
Do the same also for the options that are custom for QEMU, i.e.
vhost-user-fs is a device and it should be possible to enable/disable
it with --without-default-devices, not --without-default-features.
Compute its default value in Kconfig to obtain the more intuitive
behavior.
In this case the configure options were undocumented, too.
Reviewed-by: Marc-André L
Signed-off-by: Andrea Bolognani
---
qapi/run-state.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/run-state.json b/qapi/run-state.json
index 8124220bd9..15d6c9a2ed 100644
--- a/qapi/run-state.json
+++ b/qapi/run-state.json
@@ -348,7 +348,7 @@
#
# @poweroff: Shutdo
This is the last CONFIG_* entry in config-host.mak that had to be
special cased.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 6 --
meson.build | 6 ++
meson_options.txt | 2 ++
scripts/meson-buildoptions.s
vhost-scsi and vhost-user-scsi are two devices of their own; it should
be possible to enable/disable them with --without-default-devices, not
--without-default-features. Compute their default value in Kconfig to
obtain the more intuitive behavior.
Reviewed-by: Marc-André Lureau
Signed-off-by: Pa
Use the new support for string option parsing.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 14 --
meson.build | 27 ---
meson_options.txt | 4
scripts/meson-buildoptions.s
On Fri, Apr 29, 2022 at 10:06 AM Beraldo Leal wrote:
>
> On Fri, Apr 22, 2022 at 02:49:32PM -0400, John Snow wrote:
> > Point to this library's URLs instead of the entire project's.
> >
> > Signed-off-by: John Snow
> > ---
> > setup.cfg | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(
vhost-vsock and vhost-user-vsock are two devices of their own; it should
be possible to enable/disable them with --without-default-devices, not
--without-default-features. Compute their default value in Kconfig to
obtain the more intuitive behavior.
Reviewed-by: Marc-André Lureau
Signed-off-by:
Signed-off-by: Paolo Bonzini
---
configure | 20
meson.build | 8
2 files changed, 8 insertions(+), 20 deletions(-)
diff --git a/configure b/configure
index b146763fbd..c54e10ea26 100755
--- a/configure
+++ b/configure
@@ -224,10 +224,6 @@ glob() {
eval test
If an option is not used anywhere by the configure script, it can be just
added to $meson_options even if it is not parsed by the automatically
generated bits in scripts/meson-buildoptions.sh.
The only slightly tricky case is $debug, where the
if test "$fortify_source" = "yes" ; then
QEMU_C
It should start on the very first column.
Signed-off-by: Andrea Bolognani
---
qapi/ui.json | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/qapi/ui.json b/qapi/ui.json
index 059302a5ef..43e62efd76 100644
--- a/qapi/ui.json
+++ b/qapi/ui.json
@@
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 2 +-
meson.build | 16 +---
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/configure b/configure
index 519982800e..b146763fbd 100755
--- a/configure
+++ b/configure
@@ -2508,7 +2508,7 @@
Most of the multi-letter extensions (such as Svpbmt, Svnapot, Svinval,
etc) are only available after Priv spec v1.12 so ISA string generation
should check the minimum required priv spec version for all extensions.
Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the
device tree")
S
While prefix, bindir and qemu_suffix needs special treatment due to
differences between Windows and POSIX systems, everything else
needs no extra code in configure.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 58 ++-
From: Konstantin Kostiuk
The mingw-w64-tool package in Fedora provides widl tool with a
cross prefix, so adds it automatically for cross builds.
WIDL env can be used to redefine the path to tool.
The same behavior as with windres.
Signed-off-by: Konstantin Kostiuk
Message-Id: <20220428181525.3
The hash is now generated with a Python script.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 23 ---
docs/meson.build | 2 +-
meson.build | 10 +-
meson_options.txt | 2 ++
The riscv_cpu_realize() sets priv spec verion to v1.12 when it is
when "env->priv_ver == 0" (i.e. default v1.10) because the enum
value of priv spec v1.10 is zero.
Due to above issue, the sifive_u machine will see priv spec v1.12
instead of priv spec v1.10.
To fix this issue, we set latest priv s
This series covers few fixes discovered while trying to detect priv spec
version on QEMU virt machine and QEMU sifive_u machine.
These patches can also be found in riscv_priv_version_fixes_v1 branch at:
https://github.com/avpatel/qemu.git
Anup Patel (3):
target/riscv: Don't force update priv sp
The pcspk device is the only user of the init_isa function, and the only
-soundhw option which does not create a new device (it hacks into the
PCSpkState by hand). Remove it, since it was deprecated.
Signed-off-by: Paolo Bonzini
---
hw/audio/pcspk.c | 10 --
hw/audio/soundhw.c
From: Sunil Muthuswamy
Support for xcr0 to be able to enable xsave/xrstor. This by itself
is not sufficient to enable xsave/xrstor. WHPX XSAVE API's also
needs to be hooked up.
Signed-off-by: Sunil Muthuswamy
Message-Id:
Signed-off-by: Paolo Bonzini
---
target/i386/whpx/whpx-all.c | 89
On Freitag, 29. April 2022 16:16:54 CEST Bin Meng wrote:
> On Fri, Apr 29, 2022 at 9:48 PM Christian Schoenebeck
>
> wrote:
> > On Freitag, 29. April 2022 15:29:15 CEST Greg Kurz wrote:
> > > On Fri, 29 Apr 2022 21:19:51 +0800
> > >
> > > Bin Meng wrote:
> > > > On Fri, Apr 29, 2022 at 9:08 PM
When using Meson options rather than config-host.h, the "when" clauses
have to be changed to if statements (which is not necessarily great,
though at least it highlights which parts of the build are per-target
and which are not).
Do that before moving vhost logic to meson.build, though for now
the
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
Kconfig.host| 3 ---
backends/meson.build| 8 ++--
hw/net/meson.build | 8 ++--
hw/virtio/Kconfig | 3 ---
hw/virtio/meson.build | 25 -
meson.build | 1 +
Emulation of a simple CXL Switch downstream port.
The Device ID has been allocated for this use.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-host.c | 43 +-
hw/pci-bridge/cxl_downstream.c | 249 +
hw/pci-bridge/meson.build | 2 +-
3 fil
Since a sourceset already exists for this, avoid unnecessary repeat
of CONFIG_VIRTIO_PCI.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
hw/virtio/meson.build | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/virtio/meson.build b/hw/virtio/meson.bu
Use the new support for string option parsing.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 5 -
meson.build | 3 ++-
meson_options.txt | 2 ++
scripts/meson-buildoptions.sh | 3 +++
4 files changed, 7 insertio
Switches were already introduced, but now we support them update
the documentation to provide an example in diagram and
qemu command line parameter forms.
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 88 -
1 file changed, 86 insertions(+),
Provide an introduction to the main components of a CXL system,
with detailed explanation of memory interleaving, example command
lines and kernel configuration.
This was a challenging document to write due to the need to extract
only that subset of CXL information which is relevant to either
user
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
configure | 24 +---
scripts/meson-buildoptions.py | 5 +
scripts/meson-buildoptions.sh | 9 +
3 files changed, 11 insertions(+), 27 deletions(-)
diff --git a/configure b/config
This is quite a complicated check. I moved all the test programs to
a single file in scripts/, picking the right program with #if and a -D
flag in meson.build's cc.links() invocation.
Signed-off-by: Paolo Bonzini
---
configure| 322 +--
meson.
An initial simple upstream port emulation to allow the creation
of CXL switches. The Device ID has been allocated for this use.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_upstream.c | 216 +++
hw/pci-bridge/meson.build| 2 +-
include/hw/cxl/cxl.h
From: Konstantin Kostiuk
Signed-off-by: Konstantin Kostiuk
Message-Id: <20220428181541.300619-1-kkost...@redhat.com>
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
qga/vss-win32/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qga/vss-win32/
Add a single complex case for aarch64 virt machine.
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 48 +
tests/qtest/meson.build | 1 +
2 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl
Allow using the buildoptions.json file for more options, namely anything
that is not a boolean or multiple-choice.
The mapping between configure and meson is messy for string options,
so allow configure to use to something other than the name in
meson_options.txt. This will come in handy anyway f
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap.
The CFMWs are placed above the extended memmap.
Only create the CEDT table if cxl=on set for the machine.
Signed-off-by: Jonathan Cameron
Signed-off-
The DSDT includes several CXL specific elements and the CEDT
table is only present if we enable CXL.
The test exercises all current functionality with several
CFMWS, CHBS structures in CEDT and ACPI0016/ACPI00017 and _OSC
entries in DSDT.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tab
The following changes since commit f22833602095b05733bceaddeb20f3edfced3c07:
Merge tag 'pull-target-arm-20220428' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-28
08:34:17 -0700)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for
On Freitag, 29. April 2022 16:35:07 CEST Greg Kurz wrote:
> On Fri, 29 Apr 2022 15:50:35 +0200
>
> Christian Schoenebeck wrote:
> > On Freitag, 29. April 2022 14:56:50 CEST Greg Kurz wrote:
> > > On Fri, 29 Apr 2022 12:25:11 +0200
> > >
> > > Christian Schoenebeck wrote:
> > > > mknod() on macO
Tables that differ from normal Q35 tables when running the CXL test.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/CEDT.cxl| Bin 0 -> 184 bytes
tests/data/acpi/q35/DSDT.cxl| Bin 0 -> 9615 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
3 fi
From: Ben Widawsky
Add a trivial handler for now to cover the root bridge
where we could do some error checking in future.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 31 +++
1 file changed, 31 insertions(+)
diff
On Fri, Apr 29, 2022 at 10:33:34AM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Do not default to generate an UUID for namespaces if it is not
> explicitly specified.
>
> This is a technically a breaking change in behavior. However, since the
> UUID changes on every VM launch, it is not s
Add exceptions for the DSDT and the new CEDT tables
specific to a new CXL test in the following patch.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/CEDT.cxl| 0
tests/data/acpi/q35/DSDT.cxl| 0
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
3 files
On Fri, Apr 29, 2022 at 10:33:33AM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> We cannot provide auto-generated unique or persistent namespace
> identifiers (EUI64, NGUID, UUID) easily. Since 6.1, namespaces have been
> assigned a generated EUI64 of the form "52:54:00:".
> This is will be
This adds code to instantiate the slightly extended ACPI root port
description in DSDT as per the CXL 2.0 specification.
Basically a cut and paste job from the i386/pc code.
Signed-off-by: Jonathan Cameron
Signed-off-by: Ben Widawsky
Reviewed-by: Alex Bennée
---
hw/arm/Kconfig | 1 +
On Apple hosts we can read AppleSMC OSK key directly from host's
SMC and forward this value to QEMU Guest.
New 'hostosk' property is added:
* `-device isa-applesmc,hostosk=on`
The property is set to 'on' by default for machine version > 6.2
Apple licence allows use and run up to two additional co
At this stage we can boot configurations with host bridges,
root ports and type 3 memory devices, so add appropriate
tests.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
tests/qtest/cxl-test.c | 127 +
1 file changed, 127 insertions(+)
dif
From: Jonathan Cameron
Both registers and the CFMWS entries in CDAT use simple encodings
for the number of interleave ways and the interleave granularity.
Introduce simple conversion functions to/from the unencoded
number / size. So far the iw decode has not been needed so is
it not implemented.
From: Jonathan Cameron
Add the CFMWs memory regions to the memorymap and adjust the
PCI window to avoid hitting the same memory.
Signed-off-by: Jonathan Cameron
---
hw/i386/pc.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/h
From: Ben Widawsky
The CXL Early Discovery Table is defined in the CXL 2.0 specification as
a way for the OS to get CXL specific information from the system
firmware.
CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host
bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware
From: Ben Widawsky
This should introduce no change. Subsequent work will make use of this
new class member.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 3 +++
hw/mem/cxl_type3.c | 9 +
include/hw/cxl/cxl_device.h | 11 ++
From: Ben Widawsky
Add CXL Fixed Memory Windows to the CXL tests.
Signed-off-by: Ben Widawsky
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/tests/qtest/cxl-test.c b/test
From: Jonathan Cameron
Once a read or write reaches a CXL type 3 device, the HDM decoders
on the device are used to establish the Device Physical Address
which should be accessed. These functions peform the required maths
and then use a device specific address space to access the
hostmem->mr to
From: Ben Widawsky
Implement get and set handlers for the Label Storage Area
used to hold data describing persistent memory configuration
so that it can be ensured it is seen in the same configuration
after reboot.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mai
From: Ben Widawsky
A device's volatile and persistent memory are known Host Defined Memory
(HDM) regions. The mechanism by which the device is programmed to claim
the addresses associated with those regions is through dedicated logic
known as the HDM decoder. In order to allow the OS to properly
From: Jonathan Cameron
These memops perform interleave decoding, walking down the
CXL topology from CFMWS described host interleave
decoder via CXL host bridge HDM decoders, through the CXL
root ports and finally call CXL type 3 specific read and write
functions.
Note that, whilst functional the
From: Jonathan Cameron
Simple function to search a PCIBus to find a port by
it's port number.
CXL interleave decoding uses the port number as a target
so it is necessary to locate the port when doing interleave
decoding.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/pci/pci
From: Ben Widawsky
GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to
info already returned in the IDENTIFY command. To have a more robust
implementation, add those.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 69 +
From: Ben Widawsky
A CXL memory device (AKA Type 3) is a CXL component that contains some
combination of volatile and persistent memory. It also implements the
previously defined mailbox interface as well as the memory device
firmware interface.
Although the memory device is configured like a no
From: Ben Widawsky
The CEDT CXL Fixed Window Memory Window Structures (CFMWs)
define regions of the host phyiscal address map which
(via an impdef means) are configured such that they have
a particular interleave setup across one or more CXL Host Bridges.
Reported-by: Alison Schofield
Signed-of
From: Ben Widawsky
This works like adding a typical pxb device, except the name is
'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as
follows:
-device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1
A CXL PXB is backward compatible with PCIe. What this means in practice
is that an ope
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