From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 44 +
target/riscv/vector_helper.c| 20 +++
2 files changed, 64 insertions(+)
diff --git a/target/riscv/insn_trans/tra
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 15 +
target/riscv/vector_helper.c| 443 +---
From: eopXD
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 ++
target/riscv/translate.c
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/vector_helper.c | 220 ++-
1 file changed, 114 insertions(+), 106 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 +++
target/riscv/vector_helper.c| 11 +++
2 files changed, 22 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An option
'rvv_ta_all_1s' is added to ena
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/vector_helper.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/riscv/vec
From: eopXD
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 76 ++--
1 file changed, 38 insertions(+), 38 deletions(-)
diff
Queued, thanks. (It only took 30 months; thanks to Ivan Shcherbakov
for bringing it to my attention).
Paolo
On 4/28/22 07:32, Alexey Kardashevskiy wrote:
On 4/27/22 17:36, Cédric Le Goater wrote:
Hello Alexey,
On 4/27/22 06:36, Alexey Kardashevskiy wrote:
VFIO-PCI has an "KVM_IRQFD_FLAG_RESAMPLE" optimization for INTx EOI
handling when KVM can unmask PCI INTx (level triggered interrupt) without
sw
On 4/28/22 00:41, Rob Landley wrote:
> On 4/27/22 10:27, Thomas Huth wrote:
>> On 26/04/2022 12.26, Rob Landley wrote:
>>> When I cut and paste 80-ish characters of text into the Linux serial
>>> console, it
>>> reads 16 characters and stops. When I hit space, it reads another 16
>>> character
On Thu, Apr 28, 2022 at 01:52:46PM +0800, Jason Wang wrote:
> On Thu, Apr 28, 2022 at 12:57 PM Michael S. Tsirkin wrote:
> >
> > On Thu, Apr 28, 2022 at 11:01:10AM +0800, Jason Wang wrote:
> > > On Wed, Apr 27, 2022 at 8:25 PM Chenyi Qiang
> > > wrote:
> > > >
> > > >
> > > >
> > > > On 4/22/202
On Thu, Apr 28, 2022 at 12:57 PM Michael S. Tsirkin wrote:
>
> On Thu, Apr 28, 2022 at 11:01:10AM +0800, Jason Wang wrote:
> > On Wed, Apr 27, 2022 at 8:25 PM Chenyi Qiang wrote:
> > >
> > >
> > >
> > > On 4/22/2022 3:11 PM, Chenyi Qiang wrote:
> > > >
> > > >
> > > > On 2/7/2022 7:28 PM, Halil P
On 4/27/22 10:27, Thomas Huth wrote:
> On 26/04/2022 12.26, Rob Landley wrote:
>> When I cut and paste 80-ish characters of text into the Linux serial
>> console, it
>> reads 16 characters and stops. When I hit space, it reads another 16
>> characters,
>> and if I keep at it will eventually catch
On 4/27/22 17:36, Cédric Le Goater wrote:
Hello Alexey,
On 4/27/22 06:36, Alexey Kardashevskiy wrote:
VFIO-PCI has an "KVM_IRQFD_FLAG_RESAMPLE" optimization for INTx EOI
handling when KVM can unmask PCI INTx (level triggered interrupt) without
switching to the userspace (==QEMU).
Unfortunat
On Thu, Apr 28, 2022 at 11:01:10AM +0800, Jason Wang wrote:
> On Wed, Apr 27, 2022 at 8:25 PM Chenyi Qiang wrote:
> >
> >
> >
> > On 4/22/2022 3:11 PM, Chenyi Qiang wrote:
> > >
> > >
> > > On 2/7/2022 7:28 PM, Halil Pasic wrote:
> > >> The commit 04ceb61a40 ("virtio: Fail if iommu_platform is req
在 2022/3/14 下午3:38, ~eopxd 写道:
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Sorry. My fault. I miss a space when I send Reviewed-by. Maybe you can
update this in the next version with other changes.
Rev
Excerpts from Nicholas Piggin's message of April 21, 2022 12:04 pm:
> Excerpts from Leandro Lupori's message of April 21, 2022 4:09 am:
>> On 4/18/22 17:22, Cédric Le Goater wrote:
>>> On 4/18/22 21:10, Leandro Lupori wrote:
Add semihosting support for PPC64. This implementation is
based
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
The tail elements in the destination mask register are updated under
a tail-agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +
target/riscv/vector_helper.c| 30 +++
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 15 +
target/riscv/vector_helper.c| 443 +---
From: eopXD
`vmadc` and `vmsbc` produces a mask value, they always operate with
a tail agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 29 +++
target/riscv/internals.h| 5 +-
target/riscv
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/vector_helper.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 21e20d47e5..e0fd0e62b3 100644
--- a/t
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 44 +
target/riscv/vector_helper.c| 20 +++
2 files changed, 64 insertions(+)
diff --git a/target/riscv/insn_trans/tran
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/vector_helper.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/riscv/vect
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 +++
target/riscv/vector_helper.c| 11 +++
2 files changed, 22 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/vector_helper.c | 220 ++-
1 file changed, 114 insertions(+), 106 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f7
From: eopXD
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 ++
target/riscv/translate.c
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
---
target/riscv/insn_trans/trans_rvv.c.inc | 22 ++
target/riscv/vector_helper.c| 40 +
2 files changed, 62 insertions(+)
diff --git a/target/riscv/insn_trans/t
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 1132 +-
1 file changed, 565 insertions(+), 567 deletions(-)
dif
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 76 ++--
1 file changed, 38 insertions(+), 38 deletions(-)
diff
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An option
'rvv_ta_all_1s' is added to ena
From: eopXD
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv
> From: Alex Williamson
> Sent: Wednesday, April 27, 2022 12:22 AM
> > >
> > > My expectation would be that libvirt uses:
> > >
> > > -object iommufd,id=iommufd0,fd=NNN
> > > -device vfio-pci,fd=MMM,iommufd=iommufd0
> > >
> > > Whereas simple QEMU command line would be:
> > >
> > > -object iomm
On Wed, Apr 27, 2022 at 8:25 PM Chenyi Qiang wrote:
>
>
>
> On 4/22/2022 3:11 PM, Chenyi Qiang wrote:
> >
> >
> > On 2/7/2022 7:28 PM, Halil Pasic wrote:
> >> The commit 04ceb61a40 ("virtio: Fail if iommu_platform is requested, but
> >> unsupported") claims to fail the device hotplug when iommu_pl
在 2022/4/28 上午7:58, Alistair Francis 写道:
On Sun, Apr 24, 2022 at 3:22 PM Tsukasa OI wrote:
This commit disables ISA string conversion for Zhinx and Zhinxmin
extensions for now. Because extension category ordering of "H" is not
ratified, their ordering is likely invalid.
Once "H"-extension o
On Tue, Apr 26, 2022 at 8:14 PM Weiwei Li wrote:
>
> - add zbk* and zk* strings to isa_edata_arr
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --g
I'm playing catch up a bit here, as I was out sick for a few days.
It would be very much appreciated if you could do so, as I'm not
familiar with what is required.
Thanks
- David Miller
On Mon, Apr 25, 2022 at 3:51 AM David Hildenbrand wrote:
>
> On 25.04.22 09:43, Christian Borntraeger wrote:
g_get_real_time() returns the number of MICROSECONDS since
January 1, 1970 UTC, but g_date_time_new_from_unix_utc() expects
a timestamp in SECONDS.
Directly call g_data_time_new_from_unix_utc(g_get_real_time()) causes
overflow and a NULL pointer is returned, then qemu crashes.
Use g_date_time_new
On Sun, Apr 24, 2022 at 7:59 AM Ralf Ramsauer
wrote:
>
> Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> case, walk_pte will erroneously merge them.
>
> Enforce the split up, by tracking the virtual base address.
>
> Let's say we have the mapping:
> 0x8120 -> 0x89623000 (
Hi Stafford,
On Thu, Apr 28, 2022 at 06:48:27AM +0900, Stafford Horne wrote:
> On Wed, Apr 27, 2022 at 07:47:33PM +0100, Peter Maydell wrote:
> > On Wed, 27 Apr 2022 at 18:46, Jason A. Donenfeld wrote:
> > >
> > > Hey Stafford,
> > >
> > > On Mon, Apr 17, 2017 at 08:23:51AM +0900, Stafford Horne
On Sun, Apr 24, 2022 at 3:22 PM Tsukasa OI wrote:
>
> This commit disables ISA string conversion for Zhinx and Zhinxmin
> extensions for now. Because extension category ordering of "H" is not
> ratified, their ordering is likely invalid.
>
> Once "H"-extension ordering is determined, we can add Z
On Sun, Apr 24, 2022 at 7:59 AM Ralf Ramsauer
wrote:
>
> Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> case, walk_pte will erroneously merge them.
>
> Enforce the split up, by tracking the virtual base address.
>
> Let's say we have the mapping:
> 0x8120 -> 0x89623000 (
From: Alistair Francis
Similar to the ARM virt machine add support for adding device tree
entries for dynamically created devices.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
---
hw/riscv/virt.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/hw/ris
From: Alistair Francis
Add support for plugging in devices, this was tested with the TPM
device.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Bin Meng
---
hw/riscv/virt.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/h
From: Alistair Francis
The ARM virt machine currently uses sysbus-fdt to create device tree
entries for dynamically created MMIO devices.
The RISC-V virt machine can also benefit from this, so move the code to
the core directory.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
From: Alistair Francis
Create a platform bus to allow dynamic devices to be connected. This is
based on the ARM implementation.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Bin Meng
---
include/hw/riscv/virt.h | 7 -
hw/riscv/virt.c | 68 ++
From: Alistair Francis
Imply the TPM sysbus devices. This allows users to add TPM devices to
the RISC-V virt board.
This was tested by first creating an emulated TPM device:
swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
--ctrl type=unixio,path=swtpm-sock
Then launching QEMU w
From: Alistair Francis
This series adds support for connecting TPM devices to the RISC-V virt
board. This is similar to how it works for the ARM virt board.
This was tested by first creating an emulated TPM device:
swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
--ctrl type=unix
From: Alistair Francis
Move the binary and device tree loading code to the machine done
notifier. This allows us to prepare for editing the device tree as part
of the notifier.
This is based on similar code in the ARM virt machine.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
On Tue, Apr 26, 2022 at 8:14 PM Weiwei Li wrote:
>
> - add zbk* and zk* strings to isa_edata_arr
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --g
On Thu, Apr 28, 2022 at 1:09 AM ~eopxd wrote:
>
> From: eopXD
>
> This is the first commit regarding the tail agnostic behavior.
> Added option 'rvv_ta_all_1s' to enable the behavior, the option
> is default to false.
>
> Signed-off-by: eop Chen
> Reviewed-by: Frank Chang
> ---
> target/riscv/
On Thu, Apr 28, 2022 at 9:11 AM Alistair Francis wrote:
>
> On Thu, Apr 28, 2022 at 1:09 AM ~eopxd wrote:
> >
> > From: eopXD
> >
> > This is the first commit regarding the tail agnostic behavior.
> > Added option 'rvv_ta_all_1s' to enable the behavior, the option
> > is default to false.
>
> I'
On Thu, Apr 28, 2022 at 1:09 AM ~eopxd wrote:
>
> From: eopXD
>
> This is the first commit regarding the tail agnostic behavior.
> Added option 'rvv_ta_all_1s' to enable the behavior, the option
> is default to false.
I'm not sure I follow.
The spec says that:
"When a set is marked agnostic, t
Currently the loader uses int as the return type for various APIs
that deal with file sizes, which leads to an error if the file
size is >=2GB, as it ends up being interpreted as a negative error
code. Furthermore, we do not tolerate short reads, which are possible
at least on Linux when attempting
On Thu, Apr 28, 2022 at 1:06 AM ~eopxd wrote:
>
> From: eopXD
>
> According to v-spec (section 5.4):
> When vstart ≥ vl, there are no body elements, and no elements are
> updated in any destination vector register group, including that
> no tail elements are updated with agnostic values.
>
> vmsb
On Thu, Apr 28, 2022 at 1:09 AM ~eopxd wrote:
>
> From: eopXD
>
> No functional change intended in this commit.
>
> Signed-off-by: eop Chen
> Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/vector_helper.c | 76 ++--
> 1
On Thu, Apr 28, 2022 at 1:14 AM ~eopxd wrote:
>
> From: eopXD
>
> No functional change intended in this commit.
>
> Signed-off-by: eop Chen
> Reviewed-by: Frank Chang
Can you please keep all previous tags when sending a new version
Reviewed-by: Alistair Francis
Alistair
> ---
> target/ris
On 4/27/22 14:11, Lucas Mateus Martins Araujo e Castro wrote:
Please do convert this from a macro. Given that float16 and bfloat16 are
addressed the
same, I think the only callback you need is the conversion from
float16_to_float64. Drop
the bf16 accessor to ppc_vsr_t.
Will do, although I'm
On 4/27/22 13:24, Lucas Mateus Martins Araujo e Castro wrote:
On 26/04/2022 20:40, Richard Henderson wrote:
On 4/26/22 05:50, Lucas Mateus Castro(alqotel) wrote:
+%xx_at 23:3 !function=times_4
+@XX3_at .. ... .. . . ... &XX3 xt=%xx_at xb=%xx_xb
Hmm. De
On Wed, Apr 27, 2022 at 07:47:33PM +0100, Peter Maydell wrote:
> On Wed, 27 Apr 2022 at 18:46, Jason A. Donenfeld wrote:
> >
> > Hey Stafford,
> >
> > On Mon, Apr 17, 2017 at 08:23:51AM +0900, Stafford Horne wrote:
> > > In openrisc simulators we use hooks like 'l.nop 1' to cause the
> > > simulat
On Wed, Apr 27, 2022 at 05:52:09PM +0200, Kevin Wolf wrote:
> Am 14.03.2022 um 21:38 hat Eric Blake geschrieben:
> > According to the NBD spec, a server that advertises
> > NBD_FLAG_CAN_MULTI_CONN promises that multiple client connections will
> > not see any cache inconsistencies: when properly se
On 26/04/2022 21:26, Richard Henderson wrote:
On 4/26/22 05:50, Lucas Mateus Castro(alqotel) wrote:
+#define VSXGER16(NAME, ORIG_T,
OR_EL) \
+ void NAME(CPUPPCState *env, uint32_t a_r, uint32_t
b_r, \
+ uint32_t at_r, uint32_t mask
On 4/27/22 03:42, Joel Stanley wrote:
These are new hwcap bits added for power10.
Signed-off-by: Joel Stanley
---
MMA support for TCG is on the list so I think it makes sense for this to
land after those are merged.
I believe you mean this series:
[RFC PATCH 0/7] VSX MMA Implementation
assert(dbs->acb) is meant to check the return value of io_func per
documented in commit 6bee44ea34 ("dma: the passed io_func does not
return NULL"). However, there is a chance that after calling
aio_context_release(dbs->ctx); the dma_blk_cb function is called before
the assertion and dbs->acb is se
On Wed, 27 Apr 2022 20:54:17 +0200
Christian Schoenebeck wrote:
> mknod() on macOS does not support creating sockets, so divert to
> call sequence socket(), bind() and fchmodat() respectively if S_IFSOCK
> was passed with mode argument.
>
> Link: https://lore.kernel.org/qemu-devel/17933734.zYzKu
On 26/04/2022 20:40, Richard Henderson wrote:
On 4/26/22 05:50, Lucas Mateus Castro(alqotel) wrote:
+%xx_at 23:3 !function=times_4
+@XX3_at .. ... .. . . ... &XX3
xt=%xx_at xb=%xx_xb
Hmm. Depends, I suppose on whether you want acc[0-7] or vsr[0-28]
I m
On Wed, 27 Apr 2022 20:54:04 +0200
Christian Schoenebeck wrote:
> mknod() on macOS does not support creating regular files, so
> divert to openat_file() if S_IFREG is passed with mode argument.
>
> Furthermore, 'man 2 mknodat' on Linux says: "Zero file type is
> equivalent to type S_IFREG".
>
On Wed, Apr 27, 2022 at 5:35 PM Stefan Hajnoczi wrote:
>
> The virtio-scsi event virtqueue is not emptied by its handler function.
> This is typical for rx virtqueues where the device uses buffers when
> some event occurs (e.g. a packet is received, an error condition
> happens, etc).
>
> Polling
27.04.2022 17:35, Stefan Hajnoczi wrote:
Commit f34e8d8b8d48d73f36a67b6d5e492ef9784b5012 ("virtio-scsi: prepare
virtio_scsi_handle_cmd for dataplane") prepared the virtio-scsi cmd
virtqueue handler function to by used in both the dataplane and
Nitpick: "to BE used".
/mjt
This patch could work successfully in qemu, "zk" could be found in linux device
tree.
Tested-by: Jiatai He
On Fri, Apr 8, 2022 at 1:02 PM Vladimir Sementsov-Ogievskiy
wrote:
>
> Hi all!
>
> I always dreamed about getting rid of pattern
>
> result = self.vm.qmp(...)
> self.assert_qmp(result, 'return', {})
>
> Here is a suggestion to switch to
>
> self.vm.cmd(...)
>
> pattern instead.
Yeah,
qemu_mknodat() is expected to behave according to its POSIX API, and
therefore should always return exactly -1 on any error, and errno
should be set for the actual error code.
Signed-off-by: Christian Schoenebeck
Reviewed-by: Greg Kurz
---
hw/9pfs/9p-util-darwin.c | 3 ++-
1 file changed, 2 ins
Linux and macOS only share some errno definitions with equal macro
name and value. In fact most mappings for errno are completely
different on the two systems.
This patch converts some important errno values from macOS host to
corresponding Linux errno values before eventually sending such error
c
mknod() on macOS does not support creating regular files, so
divert to openat_file() if S_IFREG is passed with mode argument.
Furthermore, 'man 2 mknodat' on Linux says: "Zero file type is
equivalent to type S_IFREG".
Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/
Signed-off
When mapped POSIX ACL is used, we are ignoring errors when trying
to remove a POSIX ACL xattr that does not exist. On Linux hosts we
would get ENODATA in such cases, on macOS hosts however we get
ENOATTR instead.
As we can be sure that ENOATTR is defined as being identical on Linux
hosts (at least
The 'rdev' field in 9p reponse 'Rgetattr' is of type dev_t,
which is actually a system dependant type and therefore both the
size and encoding of dev_t differ between macOS and Linux.
So far we have sent 'rdev' to guest in host's dev_t format as-is,
which caused devices to appear with wrong device
mknod() on macOS does not support creating sockets, so divert to
call sequence socket(), bind() and fchmodat() respectively if S_IFSOCK
was passed with mode argument.
Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/
Signed-off-by: Christian Schoenebeck
---
hw/9pfs/9p-util-dar
A bunch of fixes for recently (in QEMU 7.0) added 9p support on macOS hosts.
Note: there are still issues to address with case-insensitive file systems
on macOS hosts. I sent a separate RFC on that icase issue:
https://lore.kernel.org/qemu-devel/1757498.AyhHxzoH2B@silver/
v3 -> v4:
* Use fchmo
t:
git://git.kraxel.org/qemu tags/kraxel-20220427-pull-request
for you to fetch changes up to a8152c4e4613c70c2f0573a82babbc8acc00cf90:
i386: firmware parsing and sev setup for -bios loaded firmware (2022-04-27
07:51:01 +0200)
vnc: add disp
On Wed, 27 Apr 2022 at 18:46, Jason A. Donenfeld wrote:
>
> Hey Stafford,
>
> On Mon, Apr 17, 2017 at 08:23:51AM +0900, Stafford Horne wrote:
> > In openrisc simulators we use hooks like 'l.nop 1' to cause the
> > simulator to exit. Implement that for qemu too.
> >
> > Reported-by: Waldemar Brodk
On Mittwoch, 27. April 2022 19:37:39 CEST Greg Kurz wrote:
> On Wed, 27 Apr 2022 18:18:31 +0200
>
> Christian Schoenebeck wrote:
> > On Mittwoch, 27. April 2022 15:31:42 CEST Greg Kurz wrote:
> > > On Wed, 27 Apr 2022 14:32:53 +0200
> > >
> > > Christian Schoenebeck wrote:
> > > > On Mittwoch,
The sbsa-ref machine is continuously evolving. Some of the changes we
want to make in the near future, to align with real components (e.g.
the GIC-700), will break compatibility for existing firmware.
Introduce two new properties to the DT generated on machine generation:
- machine-version-major
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innocation Center (quicinc), so update
my email address to reflect this.
Signed-off-by: Leif Lindholm
Cc: Leif Lindholm
Cc:
On Mittwoch, 27. April 2022 19:12:15 CEST Will Cohen wrote:
> On Wed, Apr 27, 2022 at 12:18 PM Christian Schoenebeck <
>
> qemu_...@crudebyte.com> wrote:
> > On Mittwoch, 27. April 2022 15:31:42 CEST Greg Kurz wrote:
> > > On Wed, 27 Apr 2022 14:32:53 +0200
> > >
> > > Christian Schoenebeck wrot
On Wed, Apr 27, 2022 at 7:13 PM Leif Lindholm
wrote:
>
> NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
> separate infrastructure for a transitional period. We've now switched
> over to contributing as Qualcomm Innocation Center (quicinc), so update
> my email address to ref
Hey Stafford,
On Mon, Apr 17, 2017 at 08:23:51AM +0900, Stafford Horne wrote:
> In openrisc simulators we use hooks like 'l.nop 1' to cause the
> simulator to exit. Implement that for qemu too.
>
> Reported-by: Waldemar Brodkorb
> Signed-off-by: Stafford Horne
I'm curious as to why this never
On Wed, 27 Apr 2022 18:18:31 +0200
Christian Schoenebeck wrote:
> On Mittwoch, 27. April 2022 15:31:42 CEST Greg Kurz wrote:
> > On Wed, 27 Apr 2022 14:32:53 +0200
> >
> > Christian Schoenebeck wrote:
> > > On Mittwoch, 27. April 2022 12:18:10 CEST Greg Kurz wrote:
> > > > On Wed, 27 Apr 2022 1
Don't register firmware as rom, not needed (see comment).
Add x86_firmware_configure() call for proper sev initialization.
Signed-off-by: Gerd Hoffmann
Tested-by: Xiaoyao Li
Reviewed-by: Daniel P. Berrangé
Tested-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Michael S.
Switch to usual goto-end-of-function error handling style.
No functional change.
Signed-off-by: Gerd Hoffmann
Tested-by: Xiaoyao Li
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Michael S. Tsirkin
Message-Id: <20220425135051.551037-2-kra...@redhat.com>
---
hw/
move sev firmware setup to separate function so it can be used from
other code paths. No functional change.
Signed-off-by: Gerd Hoffmann
Tested-by: Xiaoyao Li
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Michael S. Tsirkin
Message-Id: <20220425135051.551037-3
From: Vladimir Sementsov-Ogievskiy
Add simple test-case for new display-update qmp command.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Daniel P. Berrangé
Message-Id: <20220401143936.356460-4-vsement...@openvz.org>
Signed-off-by: Gerd Hoffmann
---
tests/avocado/vnc.py | 63 +
From: Carwyn Ellis
In certain circumstances, typically when there is lots changing on the
screen, updates will be discarded resulting in garbled output.
This change simplifies the traversal of the display update FIFO queue
when applying updates. We just track the queue length and iterate up to
t
From: Vladimir Sementsov-Ogievskiy
Add possibility to change addresses where VNC server listens for new
connections. Prior to 6.0 this functionality was available through
'change' qmp command which was deleted.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Daniel P. Berrangé
Message
From: Kshitij Suri
Currently screendump only supports PPM format, which is un-compressed. Added
a "format" parameter to QMP and HMP screendump command to support PNG image
capture using libpng.
QMP example usage:
{ "execute": "screendump", "arguments": { "filename": "/tmp/image",
"format":"png"
From: Vladimir Sementsov-Ogievskiy
Let's use SocketAddressList instead of dynamic arrays.
Benefits:
- Automatic cleanup: don't need specific freeing function and drop
some gotos.
- Less indirection: no triple asterix anymore!
- Prepare for the following commit, which will reuse new interfac
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