Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree

Atish Patra 於 2022年2月23日 週三 上午6:39寫道： > The Linux kernel parses the ISA extensions from "riscv,isa" DT > property. It used to parse only the single letter base extensions > until now. A generic ISA extension parsing framework was proposed[1] > recently that can parse multi-letter ISA extensions a

Re: [PATCH 6/8] char: move qemu_openpty_raw from util/ to char/

On 2/24/22 18:04, Marc-André Lureau wrote: Paolo, This patch is ok, but in some (new?) circumstances it fails with freebsd and reveals that -lutil was missing for kinfo_getproc() in util/oslib-posix.c. Please add: -util_ss.add(when: 'CONFIG_POSIX', if_true: files('oslib-posix.c')) +util_ss.a

Re: [PATCH 1/3] util & iothread: Introduce event-loop abstract class

On 2/24/22 10:48, Stefan Hajnoczi wrote: On Mon, Feb 21, 2022 at 06:08:43PM +0100, Nicolas Saenz Julienne wrote: diff --git a/qom/meson.build b/qom/meson.build index 062a3789d8..c20e5dd1cb 100644 --- a/qom/meson.build +++ b/qom/meson.build @@ -4,6 +4,7 @@ qom_ss.add(files( 'object.c', 'o

[PATCH v3 4/4] tests/acpi: i386: update FACP table differences

After changing the IAPC boot flags register to indicate support of i8042 in the machine chipset to help the guest OS to determine its existence "faster", we need to have the updated FACP ACPI binary images in tree. @@ -1,32 +1,32 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembl

[PATCH v3 3/4] hw/acpi: add indication for i8042 in IA-PC boot flags of the FADT table

This can allow the guest OS to determine more easily if i8042 controller is present in the system or not, so it doesn't need to do probing of the controller, but just initialize it immediately, before enumerating the ACPI AML namespace. Signed-off-by: Liav Albani --- hw/acpi/aml-build.c

[PATCH v3 2/4] tests/acpi: i386: allow FACP acpi table changes

The FACP table is going to be changed for x86/q35 machines. To be sure the following changes are not breaking any QEMU test this change follows step 2 from the bios-tables-test.c guide on changes that affect ACPI tables. Signed-off-by: Liav Albani --- tests/qtest/bios-tables-test-allowed-diff.h

[PATCH v3 1/4] hw/isa: add function to check for existence of device by its type

This function enumerates all attached ISA devices in the machine, and tries to compare a given device type name to the enumerated devices. For example, this can help other code to determine if a i8042 controller exists in the machine. Signed-off-by: Liav Albani --- hw/isa/isa-bus.c | 23

[PATCH v3 0/4] hw/acpi: add indication for i8042 in IA-PC boot flags of the FADT table

This can allow the guest OS to determine more easily if i8042 controller is present in the system or not, so it doesn't need to do probing of the controller, but just initialize it immediately, before enumerating the ACPI AML namespace. To allow "flexible" indication, I don't hardcode the bit at l

[PULL v2 6/6] hw/openrisc/openrisc_sim: Add support for initrd loading

The initrd passed via the command line is loaded into memory. It's location and size is then added to the device tree so the kernel knows where to find it. Signed-off-by: Stafford Horne Reviewed-by: Peter Maydell --- hw/openrisc/openrisc_sim.c | 31 +++ 1 file chang

[PULL v2 5/6] hw/openrisc/openrisc_sim: Add automatic device tree generation

Using the device tree means that qemu can now directly tell the kernel what hardware is configured rather than use having to maintain and update a separate device tree file. This patch adds automatic device tree generation support for the OpenRISC simulator. A device tree is built up based on the

[PULL v2 3/6] hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART

Currently the OpenRISC SMP configuration only supports 2 cores due to the UART IRQ routing being limited to 2 cores. As was done in commit 1eeffbeb11 ("hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs") we can use a splitter to wire more than 2 CPUs. This patch move

[PULL v2 2/6] hw/openrisc/openrisc_sim: Parameterize initialization

Move magic numbers to variables and enums. These will be reused for upcoming fdt initialization. Signed-off-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daudé --- hw/openrisc/openrisc_sim.c | 42 ++ 1 file changed, 34 insertions(+), 8 deletions(-) diff -

[PULL v2 4/6] hw/openrisc/openrisc_sim: Increase max_cpus to 4

Now that we no longer have a limit of 2 CPUs due to fixing the IRQ routing issues we can increase the max. Here we increase the limit to 4, we could go higher, but currently OMPIC has a limit of 4, so we align with that. Signed-off-by: Stafford Horne Reviewed-by: Peter Maydell Reviewed-by: Phil

[PULL v2 1/6] hw/openrisc/openrisc_sim: Create machine state for or1ksim

This will allow us to attach machine state attributes like the device tree fdt. Signed-off-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daudé --- hw/openrisc/openrisc_sim.c | 30 -- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/hw/openrisc/openri

[PULL v2 0/6] OpenRISC DTS Generation patches for 7.0

The following changes since commit 4aa2e497a98bafe962e72997f67a369e4b52d9c1: Merge remote-tracking branch 'remotes/berrange-gitlab/tags/misc-next-pull-request' into staging (2022-02-23 09:25:05 +) are available in the Git repository at: git://github.com/stffrdhrn/qemu.git tags/or1k-pul

[PATCH] tcg/tci: Use tcg_out_ldst in tcg_out_st

The tcg_out_ldst helper will handle out-of-range offsets. We haven't actually encountered any, since we haven't run across the assert within tcg_out_op_rrs, but an out-of-range offset would not be impossible in future. Fixes: 65089889183 ("tcg/tci: Change encoding to uint32_t units") Signed-off-by

Re: [PULL 0/6] OpenRISC DTS Generation patches for 7.0

On Fri, Feb 25, 2022 at 01:52:52PM +, Peter Maydell wrote: > On Fri, 25 Feb 2022 at 09:19, Stafford Horne wrote: > > > > The following changes since commit 4aa2e497a98bafe962e72997f67a369e4b52d9c1: > > > > Merge remote-tracking branch > > 'remotes/berrange-gitlab/tags/misc-next-pull-request

Re: [PATCH v3 00/11] blockdev-replace

26.02.2022 02:42, Vladimir Sementsov-Ogievskiy wrote: Hi all! Finally, that's a proposal for new interface for filter insertion, which provides generic way for inserting between different block graph nodes, like BDS nodes, block exports and block devices. v3: - add transaction support - ad

[PATCH v3 10/11] iotests.py: add VM.qmp_check() helper

I'm tired of this pattern being everywhere. Let's add a helper. Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/iotests.py | 4 1 file changed, 4 insertions(+) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index 1b48c5b9c9..dd33970454 100644

[PATCH v3 08/11] iotests.py: qemu_img_create: use imgfmt by default

Less typing: let's use imgfmt by default if user doesn't specify neither -f nor --image-opts. Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/iotests.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index 6b

[PATCH v3 11/11] iotests: add filter-insertion

Demonstrate new API for filter insertion and removal. Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/tests/filter-insertion | 253 ++ tests/qemu-iotests/tests/filter-insertion.out | 5 + 2 files changed, 258 insertions(+) create mode 100755 tests/qemu-i

[PATCH v3 07/11] block: bdrv_get_xdbg_block_graph(): report export ids

Currently for block exports we report empty blk names. That's not good. Let's try to find corresponding block export and report its id. Signed-off-by: Vladimir Sementsov-Ogievskiy --- include/block/export.h | 1 + block.c | 4 block/export/export.c | 13

[PATCH v3 09/11] iotests.py: introduce VM.assert_edges_list() method

Add an alternative method to check block graph, to be used in further commit. Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/iotests.py | 17 + 1 file changed, 17 insertions(+) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index c

[PATCH v3 05/11] qapi: add x-blockdev-replace command

Add a command that can replace bs in following BdrvChild structures: - qdev blk root child - block-export blk root child - any child BlockDriverState selected by child-name Signed-off-by: Vladimir Sementsov-Ogievskiy --- qapi/block-core.json | 62 b

[PATCH v3 02/11] block/export: add blk_by_export_id()

Signed-off-by: Vladimir Sementsov-Ogievskiy --- include/sysemu/block-backend.h | 1 + block/export/export.c | 18 ++ 2 files changed, 19 insertions(+) diff --git a/include/sysemu/block-backend.h b/include/sysemu/block-backend.h index 904d70f49c..250c7465a5 100644 --- a/

[PATCH v3 04/11] block: bdrv_replace_child_bs(): move to external transaction

We'll need this functionality as part of external transaction, so make the whole function to be transaction action. For this we need to introduce a transaction action helper: bdrv_drained(), which calls bdrv_drained_begin() and postpone bdrv_drained_end() to .clean() phase. Signed-off-by: Vladimir

[PATCH v3 06/11] qapi: add x-blockdev-replace transaction action

Support blockdev-replace in a transaction. Signed-off-by: Vladimir Sementsov-Ogievskiy --- qapi/transaction.json | 14 +- blockdev.c| 34 ++ 2 files changed, 47 insertions(+), 1 deletion(-) diff --git a/qapi/transaction.json b/qapi/transac

[PATCH v3 01/11] block-backend: blk_root(): drop const specifier on return type

We'll need get non-const child pointer for graph modifications in further commits. Signed-off-by: Vladimir Sementsov-Ogievskiy --- include/sysemu/block-backend.h | 2 +- block/block-backend.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/sysemu/block-bac

[PATCH v3 00/11] blockdev-replace

Hi all! Finally, that's a proposal for new interface for filter insertion, which provides generic way for inserting between different block graph nodes, like BDS nodes, block exports and block devices. v3: - add transaction support - add test, that shows transactional filter insertion in diff

[PATCH v3 03/11] block: make bdrv_find_child() function public

To be reused soon. Signed-off-by: Vladimir Sementsov-Ogievskiy --- include/block/block_int.h | 1 + block.c | 13 + blockdev.c| 14 -- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/include/block/block_int.h b/include/b

Re: [PATCH v5 44/49] target/ppc: Refactor VSX_MAX_MINC helper

On 2/25/22 11:09, matheus.fe...@eldorado.org.br wrote: From: Víctor Colombo Refactor xs{max,min}cdp VSX_MAX_MINC helper to prepare for xs{max,min}cqp implementation. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- changes for v5: - use float_flag_invalid_snan as suggested by R

Re: [PATCH v5 34/49] target/ppc: Implement xxeval

On 2/25/22 11:09, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- v5: - Some equivalent functions implemented with tcg_gen_gvec_* --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 + target/ppc/int_helper.c

[PATCH v5 48/49] target/ppc: implement plxssp/pstxssp

From: Leandro Lupori Implement instructions plxssp/pstxssp and port lxssp/stxssp to decode tree. Reviewed-by: Richard Henderson Signed-off-by: Leandro Lupori Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 + target/ppc/insn64.decode| 6 ++ target/ppc/t

[PATCH v5 44/49] target/ppc: Refactor VSX_MAX_MINC helper

From: Víctor Colombo Refactor xs{max,min}cdp VSX_MAX_MINC helper to prepare for xs{max,min}cqp implementation. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- changes for v5: - use float_flag_invalid_snan as suggested by Richard Henderson --- target/ppc/fpu_helper.c | 41 ++

[PATCH v5 42/49] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree

From: Víctor Colombo Reviewed-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 6 +++--- target/ppc/helper.h | 6 +++--- target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx-impl.c.in

[PATCH v5 40/49] target/ppc: Refactor VSX_SCALAR_CMP_DP

From: Víctor Colombo Refactor VSX_SCALAR_CMP_DP, changing its name to VSX_SCALAR_CMP and prepare the helper to be used for quadword comparisons. Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- changes for v5: - Improve refactor as suggested by Ri

Re: [PATCH v5 40/49] target/ppc: Refactor VSX_SCALAR_CMP_DP

On 2/25/22 11:09, matheus.fe...@eldorado.org.br wrote: From: Víctor Colombo Refactor VSX_SCALAR_CMP_DP, changing its name to VSX_SCALAR_CMP and prepare the helper to be used for quadword comparisons. Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst ---

[PATCH v5 39/49] target/ppc: Remove xscmpnedp instruction

From: Víctor Colombo xscmpnedp was added in ISA v3.0 but removed in v3.0B. This patch removes this instruction as it was not in the final version of v3.0. Signed-off-by: Víctor Colombo Acked-by: Greg Kurz Reviewed-by: Cédric Le Goater Reviewed-by: Richard Henderson Signed-off-by: Matheus Fer

Re: [PATCH v5 38/49] target/ppc: Implement xvtlsbb instruction

On 2/25/22 11:09, matheus.fe...@eldorado.org.br wrote: From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- changes for v5: - unroll for-loop as suggested by Richard Henderson --- target/ppc/insn32.decode| 7 + target/ppc/translate/vsx-impl.c.in

[PATCH v5 37/49] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]

From: Matheus Ferst Implement the following PowerISA v3.0 instuctions: xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd] xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] xsnmaddqp[o]: VSX Scalar Negative Multiply-Add Quad-Precision

Re: [PATCH v5 35/49] target/ppc: Implement xxgenpcv[bhwd]m instruction

On 2/25/22 11:09, matheus.fe...@eldorado.org.br wrote: +#define XXGENPCV(NAME) \ +static bool trans_##NAME(DisasContext *ctx, arg_X_imm5 *a) \ +{ \ +TCGv_ptr xt, vrb; \ +

Re: [PATCH v2 13/18] tests/tcg: add vectorised sha512 versions

On 2/25/22 07:20, Alex Bennée wrote: +++ b/tests/tcg/i386/Makefile.target @@ -71,3 +71,9 @@ TESTS=$(MULTIARCH_TESTS) $(I386_TESTS) # On i386 and x86_64 Linux only supports 4k pages (large pages are a different hack) EXTRA_RUNS+=run-test-mmap-4096 + +sha512-sse: CFLAGS=-msse4.1 -O3 +sha512

Re: [PATCH v5 26/49] target/ppc: implement vrlqnm

On 2/25/22 11:09, matheus.fe...@eldorado.org.br wrote: +/* t = t >> 1 */ +tcg_gen_shli_i64(t0, th, 63); +tcg_gen_shri_i64(tl, tl, 1); +tcg_gen_shri_i64(th, th, 1); +tcg_gen_or_i64(tl, t0, tl); tcg_gen_extract2_i64(tl, tl, th, 1); tcg_gen_shri_i64(th, th, 1); +if (mask)

Re: [PATCH v5 45/49] target/ppc: Implement xs{max,min}cqp

On 2/25/22 11:09, matheus.fe...@eldorado.org.br wrote: From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- changes for v5: - Update the helper macro call with the new parameters added to VSX_MAX_MINC --- target/ppc/fpu_helper.c | 2 ++ target/ppc

Re: [PATCH v5 46/49] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions

On 2/25/22 11:09, matheus.fe...@eldorado.org.br wrote: +void helper_XVCVSPBF16(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) +{ +ppc_vsr_t t = { }; +int i, status; + +for (i = 0; i < 4; i++) { +t.VsrH(2 * i + 1) = float32_to_bfloat16(xb->VsrW(i), &env->fp_status); +} + +

[PATCH v5 33/49] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i

From: Matheus Ferst Following the implementation of tcg_gen_gvec_3i, add a four-vector and immediate operand expansion method. Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- include/tcg/tcg-op-gvec.h | 22 ++ tcg/tcg-op-gvec.c | 146 ++

Re: [PATCH v5 35/49] target/ppc: Implement xxgenpcv[bhwd]m instruction

On 2/25/22 11:09, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- v5: - One helper for each IMM value. --- target/ppc/helper.h | 16 + target/ppc/insn32.decode| 10 target/ppc/int_helper.c | 91 +

Re: [PATCH v5 27/49] target/ppc: implement vrlqmi

On 2/25/22 11:09, matheus.fe...@eldorado.org.br wrote: +if (insert) { +get_avr64(n, a->vrt, true); +get_avr64(vrb, a->vrt, false); +tcg_gen_not_i64(ah, ah); +tcg_gen_not_i64(al, al); +tcg_gen_and_i64(n, n, ah); +tcg_g

[PATCH v5 29/49] target/ppc: Move xxsel to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/insn64.decode| 24 target/ppc/translate/vsx-impl.c.inc | 20 ++ target/ppc/translate/vsx-ops.c.inc | 43 --

[PATCH v5 46/49] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 18 + target/ppc/helper.h | 1 + target/ppc/insn32.decode| 11 +++--- target/ppc/translate/vsx-impl.c.inc | 31

[PATCH v5 28/49] target/ppc: Move vsel and vperm/vpermr to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 5 +-- target/ppc/insn32.decode| 5 +++ target/ppc/int_helper.c | 13 +- target/ppc/translate/vmx-impl.c.inc | 69 ++--

Re: [PATCH v5 24/49] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree

On 2/25/22 11:09, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- I couldn't figure out how to use tcg_gen_gvec_rotlv here. Since the code is in the fniv implementation, we have TCGv_vec instead of offsets. I'm keeping the masking for now, so the generat

[PATCH v5 49/49] target/ppc: implement lxvr[bhwd]/stxvr[bhwd]x

From: Lucas Coutinho Implement the following PowerISA v3.1 instuctions: lxvrbx: Load VSX Vector Rightmost Byte Indexed X-form lxvrhx: Load VSX Vector Rightmost Halfword Indexed X-form lxvrwx: Load VSX Vector Rightmost Word Indexed X-form lxvrdx: Load VSX Vector Rightmost Doubleword Indexed X-form

Re: [PATCH v5 04/49] target/ppc: vmulh* instructions without helpers

On 2/25/22 11:08, matheus.fe...@eldorado.org.br wrote: +static void do_vx_vmulhw_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign) +{ +TCGv_i64 hh, lh, temp; + +uint64_t c; +hh = tcg_temp_new_i64(); +lh = tcg_temp_new_i64(); +temp = tcg_temp_new_i64(); + +c = 0x;

[PATCH v5 45/49] target/ppc: Implement xs{max,min}cqp

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- changes for v5: - Update the helper macro call with the new parameters added to VSX_MAX_MINC --- target/ppc/fpu_helper.c | 2 ++ target/ppc/helper.h | 2 ++ target/ppc/insn32.decod

[PATCH v5 23/49] target/ppc: move vrl[bhwd] to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 5 + target/ppc/translate/vmx-impl.c.inc | 13 + target/ppc/translate/vmx-ops.c.inc | 6 ++ 3 files changed, 12 insertions(+), 12 deletions(-) diff

[PATCH v5 36/49] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 23 ++-- target/ppc/helper.h | 16 - target/ppc/insn32.decode| 22 target/ppc/translate/vsx-impl.c.inc | 56 +++

[PATCH v5 47/49] target/ppc: implement plxsd/pstxsd

From: Leandro Lupori Implement instructions plxsd/pstxsd and port lxsd/stxsd to decode tree. Reviewed-by: Richard Henderson Signed-off-by: Leandro Lupori Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/insn64.decode| 10 ++ target/ppc/

[PATCH v5 20/49] target/ppc: implement vslq

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 40 + 2 files changed, 41 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.d

[PATCH v5 43/49] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3

From: Víctor Colombo Also, fixes these instructions not being capitalized. Reviewed-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 8 target/ppc/helper.h | 8 target/ppc/translate/

[PATCH v5 41/49] target/ppc: Implement xscmp{eq,ge,gt}qp

From: Víctor Colombo Reviewed-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 3 +++ target/ppc/helper.h | 3 +++ target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx-impl.c.inc | 31

[PATCH v5 31/49] target/ppc: Move xxpermdi to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 4 ++ target/ppc/translate/vsx-impl.c.inc | 71 + target/ppc/translate/vsx-ops.c.inc | 2 - 3 files changed, 36 insertions(+), 41 deletions(-

[PATCH v5 38/49] target/ppc: Implement xvtlsbb instruction

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- changes for v5: - unroll for-loop as suggested by Richard Henderson --- target/ppc/insn32.decode| 7 + target/ppc/translate/vsx-impl.c.inc | 40 + 2 files changed, 4

[PATCH v5 18/49] target/ppc: implement vgnb

From: Matheus Ferst Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 5 ++ target/ppc/translate/vmx-impl.c.inc | 135 2 files changed, 140 insertions(+) diff --git a/target/ppc

[PATCH v5 30/49] target/ppc: move xxperm/xxpermr to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 21 --- target/ppc/helper.h | 2 -- target/ppc/insn32.decode| 5 target/ppc/translate/vsx-impl.c.inc | 42 +++

[PATCH v5 17/49] target/ppc: implement vcntmb[bhwd]

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 8 target/ppc/translate/vmx-impl.c.inc | 32 + 2 files changed, 40 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/i

[PATCH v5 34/49] target/ppc: Implement xxeval

From: Matheus Ferst Signed-off-by: Matheus Ferst --- v5: - Some equivalent functions implemented with tcg_gen_gvec_* --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 + target/ppc/int_helper.c | 42 ++ target/ppc/translate/vsx-impl.c.i

[PATCH v5 35/49] target/ppc: Implement xxgenpcv[bhwd]m instruction

From: Matheus Ferst Signed-off-by: Matheus Ferst --- v5: - One helper for each IMM value. --- target/ppc/helper.h | 16 + target/ppc/insn32.decode| 10 target/ppc/int_helper.c | 91 + target/ppc/translate/vsx-impl.c.i

[PATCH v5 27/49] target/ppc: implement vrlqmi

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 21 + 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 87d482c5d9..

[PATCH v5 32/49] target/ppc: Implement xxpermx instruction

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 target/ppc/int_helper.c | 20 target/ppc/translate/vsx-impl.c.inc | 22 +++

[PATCH v5 14/49] target/ppc: implement vstri[bh][lr]

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 target/ppc/insn32.decode| 10 ++ target/ppc/int_helper.c | 28 +++ target/ppc/translate/vmx-impl.c.inc | 30

[PATCH v5 26/49] target/ppc: implement vrlqnm

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 81 +++-- 2 files changed, 77 insertions(+), 5 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index c3d4

[PATCH v5 24/49] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- I couldn't figure out how to use tcg_gen_gvec_rotlv here. Since the code is in the fniv implementation, we have TCGv_vec instead of offsets. I'm keeping the masking for now, so the generated code has the desired effect. --- target/ppc/helper.

[PATCH v5 11/49] target/ppc: Implement Vector Compare Equal Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpequq: Vector Compare Equal Quadword Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 36

[PATCH v5 25/49] target/ppc: implement vrlq

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 48 + 2 files changed, 49 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.d

[PATCH v5 16/49] target/ppc: implement vclrrb

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 32 + 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/target/ppc/insn32.decode b/tar

[PATCH v5 22/49] target/ppc: implement vsraq

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 23 +-- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/target/ppc/insn32.decode b/target/pp

[PATCH v5 12/49] target/ppc: Implement Vector Compare Greater Than Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpgtsq: Vector Compare Greater Than Signed Quadword vcmpgtuq: Vector Compare Greater Than Unsigned Quadword Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ ta

[PATCH v5 15/49] target/ppc: implement vclrlb

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/translate/vmx-impl.c.inc | 40 + 2 files changed, 42 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.

[PATCH v5 21/49] target/ppc: implement vsrq

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 40 + 2 files changed, 31 insertions(+), 10 deletions(-) diff --git a/target/ppc/insn32.decode b/ta

[PATCH v5 07/49] target/ppc: Move vexts[bhw]2[wd] to decodetree

From: Lucas Coutinho Move the following instructions to decodetree: vextsb2w: Vector Extend Sign Byte To Word vextsh2w: Vector Extend Sign Halfword To Word vextsb2d: Vector Extend Sign Byte To Doubleword vextsh2d: Vector Extend Sign Halfword To Doubleword vextsw2d: Vector Extend Sign Word To Doub

[PATCH v5 05/49] target/ppc: Implement vmsumcud instruction

From: Víctor Colombo Based on [1] by Lijun Pan , which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Reviewed-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 4

[PATCH v5 13/49] target/ppc: Implement Vector Compare Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpsq: Vector Compare Signed Quadword vcmpuq: Vector Compare Unsigned Quadword Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/translate/vmx-impl.

[PATCH v5 19/49] target/ppc: move vs[lr][a][bhwd] to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 17 target/ppc/translate/vmx-impl.c.inc | 41 +++-- target/ppc/translate/vmx-ops.c.inc | 13 + 3 files changed, 45 insertions(

[PATCH v5 04/49] target/ppc: vmulh* instructions without helpers

From: "Lucas Mateus Castro (alqotel)" Changed vmulhuw, vmulhud, vmulhsw, vmulhsd to not use helpers. Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 -- target/ppc/int_helper.c | 35 --- target/ppc/tran

[PATCH v5 10/49] target/ppc: Move Vector Compare Not Equal or Zero to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 9 ++-- target/ppc/insn32.decode| 4 ++ target/ppc/int_helper.c | 50 +- target/ppc/translate/vmx-impl.c.inc | 66

[PATCH v5 01/49] target/ppc: Introduce TRANS*FLAGS macros

From: Luis Pires New macros that add FLAGS and FLAGS2 checking were added for both TRANS and TRANS64. Reviewed-by: Richard Henderson Signed-off-by: Luis Pires [ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E - Use the new macros in load/store vector insns ] Signed-off-by: Matheus Ferst

[PATCH v5 03/49] target/ppc: Moved vector multiply high and low to decodetree

From: "Lucas Mateus Castro (alqotel)" Moved instructions vmulld, vmulhuw, vmulhsw, vmulhud and vmulhsd to decodetree Reviewed-by: Richard Henderson Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 8 target/ppc/insn

[PATCH v5 09/49] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 30 -- target/ppc/insn32.decode| 24 target/ppc/int_helper.c | 54 - target/ppc/translate/vmx-impl.c.inc | 89 +

[PATCH 8/9] Avocado tests: classify tests based on what it's booted

This adds some classification to the existing tests, based on the mechanism (and a lot more loosely) on the content of the binary blob. The proposal is to use the "boots" tag, and so far the following values have been defined with the following meaning: - bios: the "-bios" option is used to se

[PATCH v5 00/49] target/ppc: PowerISA Vector/VSX instruction batch

From: Matheus Ferst This patch series implements 5 missing instructions from PowerISA v3.0 and 58 new instructions from PowerISA v3.1, moving 87 other instructions to decodetree along the way. Patches without review: 4, 24, 26, 27, 34, 35, 38, 40, 44-46 This series can also be found at: https:/

[PATCH v5 06/49] target/ppc: Implement vmsumudm instruction

From: Víctor Colombo Based on [1] by Lijun Pan , which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Reviewed-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1

[PATCH v5 08/49] target/ppc: Implement vextsd2q

From: Lucas Coutinho Reviewed-by: Richard Henderson Signed-off-by: Lucas Coutinho Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 18 ++ 2 files changed, 19 insertions(+) diff --git a/target/ppc/insn32.decode

[PATCH 9/9] Avocado tests: don't run tests with TCG that boot full blown distros

Tests that use TCG and boot full blown distros, such as Fedora, will take a good time to run. This excludes those combinations by default on invocations of "make check-avocado". Tests that rely on KVM instead, will continue to run. As a reminder, one can always supply a list of tests or tags to

[PATCH v5 02/49] target/ppc: moved vector even and odd multiplication to decodetree

From: "Lucas Mateus Castro (alqotel)" Moved the instructions vmulesb, vmulosb, vmuleub, vmuloub, vmulesh, vmulosh, vmuleuh, vmulouh, vmulesw, vmulosw, muleuw and vmulouw from legacy to decodetree. Implemented the instructions vmulesd, vmulosd, vmuleud, vmuloud. Reviewed-by: Richard Henderson Si

[PATCH 4/9] Avocado: bump to version 95.0

Even though there have been a number of improvements (and some pretty deep internal changes) since Avocado 88.1, only one change should affect "make check-avocado". With the nrunner architecture, test execution happens in parallel by default. But, tests may fail due to insufficient timeouts or si

[PATCH 0/9] Avocado tests: filter out tests using TCG booting full blown distros

It was previously reported[1] and discussed that tests booting full blown distros and relying on TCG would take too much time to run, especially in the environments given by GitLab CI's shared runners. This is an implementation of a proposal to exclude those tests from being run by default on `mak

[PATCH 6/9] tests/avocado/virtiofs_submounts.py: shared_dir may not exist

If the test is skipped because of their conditionals, the shared_dir attribute may not exist. Check for its existence in the tearDown() method to avoid and AttributeError. Signed-off-by: Cleber Rosa --- tests/avocado/virtiofs_submounts.py | 7 --- 1 file changed, 4 insertions(+), 3 deletion

[PATCH 3/9] Avocado migration test: adapt to "utils.network" API namespace change

Since Avocado 94.0[1], the "avocado.utils.network" dropped a lot of previously deprecated API names, having the new names into a finer grained structure. This simply uses the new API names for the network port utility module. [1] - https://avocado-framework.readthedocs.io/en/latest/releases/94_0

[PATCH 7/9] Avocado tests: improve documentation on tag filtering

It's possible to filter based on a combination of criteria. This adds examples to the documentation. Signed-off-by: Cleber Rosa --- docs/devel/testing.rst | 22 ++ 1 file changed, 22 insertions(+) diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst index 92d40cdd19

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