[PATCH v6 15/19] vfio-user: handle device interrupts

Forward remote device's interrupts to the guest Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman --- include/hw/pci/pci.h | 6 ++ include/hw/remote/vfio-user-obj.h | 6 ++ hw/pci/msi.c | 13 +++- hw/pci/msix.c

[PATCH v6 05/19] remote/machine: add vfio-user property

Add vfio-user to x-remote machine. It is a boolean, which indicates if the machine supports vfio-user protocol. The machine configures the bus differently vfio-user and multiprocess protocols, so this property informs it on how to configure the bus. This property should be short lived. Once vfio-u

[PATCH v6 09/19] vfio-user: find and init PCI device

Find the PCI device with specified id. Initialize the device context with the QEMU PCI device Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman Reviewed-by: Stefan Hajnoczi --- hw/remote/vfio-user-obj.c | 59 +++

[PATCH v6 11/19] vfio-user: handle PCI config space accesses

Define and register handlers for PCI config space accesses Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman Reviewed-by: Stefan Hajnoczi --- hw/remote/vfio-user-obj.c | 45 +++ hw/remote/trace-events| 2 ++

[PATCH v6 04/19] remote/machine: add HotplugHandler for remote machine

Allow hotplugging of PCI(e) devices to remote machine Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman --- hw/remote/machine.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/remote/machine.c b/hw/remote/machine.c index 952105eab5

[PATCH v6 00/19] vfio-user server in QEMU

Hi, This is v6 of the server side changes to enable vfio-user in QEMU. Thank you very much for your feedback for the last revision which helped to streamline the overall design. We've made the following changes to this revision: [PATCH v6 03/19] qdev: unplug blocker for devices - removed test

[PATCH v6 01/19] configure, meson: override C compiler for cmake

The compiler path that cmake gets from meson is corrupted. It results in the following error: | -- The C compiler identification is unknown | CMake Error at CMakeLists.txt:35 (project): | The CMAKE_C_COMPILER: | /opt/rh/devtoolset-9/root/bin/cc;-m64;-mcx16 | is not a full path to an existing compil

Re: [PATCH 3/3] x86: Switch to q35 as the default machine type

On 16/02/2022 18.57, Dr. David Alan Gilbert wrote: * Daniel P. Berrangé (berra...@redhat.com) wrote: On Wed, Feb 16, 2022 at 05:40:44PM +, Dr. David Alan Gilbert wrote: * Thomas Huth (th...@redhat.com) wrote: On 16/02/2022 12.01, Dr. David Alan Gilbert wrote: * Gerd Hoffmann (kra...@redha

Re: [PATCH v8 3/3] qapi/monitor: allow VNC display id in set/expire_password

Am 09.02.22 um 15:07 schrieb Markus Armbruster: > Fabian Ebner writes: > >> From: Stefan Reiter >> >> It is possible to specify more than one VNC server on the command line, >> either with an explicit ID or the auto-generated ones à la "default", >> "vnc2", "vnc3", ... >> >> It is not possible t

Re: [PATCH 2/2] Allow VIRTIO_F_IN_ORDER to be negotiated for vdpa devices

On Tue, Feb 15, 2022 at 12:52:31PM +0530, Gautam Dawar wrote: > This patch adds the ability to negotiate VIRTIO_F_IN_ORDER bit > for vhost-vdpa backend when the underlying device supports this > feature. > This would aid in reaping performance benefits with HW devices > that implement this feature.

Re: QEMU's Haiku CI image

On 16/02/2022 20.21, Daniel P. Berrangé wrote: [...] The main issue is that for non-Linux, we don't have full automation for building the VM templates. We need someone to prepare the image by getting it able to run and expose SSH, whereupon we can provision the build-deps. That's easy: In QEMU

Re: [PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions

在 2022/2/17 上午11:59, Christoph Müllner 写道: On Thu, Feb 17, 2022 at 3:15 AM Weiwei Li > wrote: 在 2022/2/16 下午11:48, Christoph Muellner 写道: > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 39ffb883fc..04500fe352 100644 > --- a/target/

Re: [PATCH 1/2] linux headers: update against Linux 5.17-rc4

On Tue, Feb 15, 2022 at 3:23 PM Gautam Dawar wrote: > > This update is done to bring in the definition of VIRTIO_F_IN_ORDER > from Linux kernel's include/uapi/linux/virtio_config.h. > A patch was recently published to add VIRTIO_F_IN_ORDER's definition > in the Linux kernel on top of version 5.17-

Re: [PATCH 2/2] Allow VIRTIO_F_IN_ORDER to be negotiated for vdpa devices

On Tue, Feb 15, 2022 at 3:23 PM Gautam Dawar wrote: > > This patch adds the ability to negotiate VIRTIO_F_IN_ORDER bit > for vhost-vdpa backend when the underlying device supports this > feature. > This would aid in reaping performance benefits with HW devices > that implement this feature. At the

Re: Call for GSoC and Outreachy project ideas for summer 2022

On Fri, Jan 28, 2022 at 6:04 PM Stefan Hajnoczi wrote: > > Dear QEMU, KVM, and rust-vmm communities, > QEMU will apply for Google Summer of Code 2022 > (https://summerofcode.withgoogle.com/) and has been accepted into > Outreachy May-August 2022 (https://www.outreachy.org/). You can now > submit i

Re: [PATCH v3 0/7] malta: Fix PCI IRQ levels to be preserved during migration, cleanup

On Wed, Feb 16, 2022 at 11:45:12PM +0100, Bernhard Beschow wrote: > Tested with [1]: > > qemu-system-mipsel -M malta -kernel vmlinux-3.2.0-4-4kc-malta -hda \ > debian_wheezy_mipsel_standard.qcow2 -append "root=/dev/sda1 console=tty0" > > It was possible to log in as root and `poweroff` the ma

Re: [PATCH v3 6/7] hw/isa/piix4: Replace some magic IRQ constants

On Wed, Feb 16, 2022 at 11:45:18PM +0100, Bernhard Beschow wrote: > This is a follow-up on patch "malta: Move PCI interrupt handling from > gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably > didn't want to use piix4-specific constants. Now that the interrupt > handing resides i

Re: [PATCH v3 4/7] hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq()

On Wed, Feb 16, 2022 at 11:45:16PM +0100, Bernhard Beschow wrote: > Passing PIIX4State rather than just the qemu_irq allows for resolving > the global piix4_dev variable. > > Signed-off-by: Bernhard Beschow > Reviewed-by: Peter Maydell > Reviewed-by: Philippe Mathieu-Daudé Acked-by: Michael S.

Re: [PATCH v3 3/7] hw/isa/piix4: Resolve redundant i8259[] attribute

On Wed, Feb 16, 2022 at 11:45:15PM +0100, Bernhard Beschow wrote: > This is a follow-up on patch "malta: Move PCI interrupt handling from > gt64xxx_pci to piix4" where i8259[] was moved from MaltaState to > PIIX4State to make the code movement more obvious. However, i8259[] > seems redundant to *is

Re: [PATCH v3 5/7] hw/isa/piix4: Resolve global instance variable

On Wed, Feb 16, 2022 at 11:45:17PM +0100, Bernhard Beschow wrote: > Now that piix4_set_irq's opaque parameter references own PIIX4State, > piix4_dev becomes redundant. > > Signed-off-by: Bernhard Beschow > Reviewed-by: Philippe Mathieu-Daudé Acked-by: Michael S. Tsirkin > --- > hw/isa/piix4.

Re: [PATCH v2 3/8] x86: Grant AMX permission for guest

On Wed, Feb 16, 2022 at 10:04:29PM -0800, Yang Zhong wrote: > Kernel allocates 4K xstate buffer by default. For XSAVE features > which require large state component (e.g. AMX), Linux kernel > dynamically expands the xstate buffer only after the process has > acquired the necessary permissions. Thos

Re: [PATCH v5 01/18] configure, meson: override C compiler for cmake

> On Jan 20, 2022, at 8:27 AM, Paolo Bonzini wrote: > > On 1/19/22 22:41, Jagannathan Raman wrote: >> The compiler path that cmake gets from meson is corrupted. It results in >> the following error: >> | -- The C compiler identification is unknown >> | CMake Error at CMakeLists.txt:35 (project)

[PATCH v2 8/8] linux-header: Sync the linux headers

This patch will be dropped once Qemu sync linux 5.17 header. Making all linux-headers changes here are only for maintainers to easily remove those changes once those patches are queued. Signed-off-by: Yang Zhong --- linux-headers/asm-x86/kvm.h | 17 + linux-headers/linux/kvm.h

[PATCH v2 7/8] x86: Support XFD and AMX xsave data migration

From: Zeng Guang XFD(eXtended Feature Disable) allows to enable a feature on xsave state while preventing specific user threads from using the feature. Support save and restore XFD MSRs if CPUID.D.1.EAX[4] enumerate to be valid. Likewise migrate the MSRs and related xsave state necessarily. Sig

[PATCH v2 6/8] x86: add support for KVM_CAP_XSAVE2 and AMX state migration

From: Jing Liu When dynamic xfeatures (e.g. AMX) are used by the guest, the xsave area would be larger than 4KB. KVM_GET_XSAVE2 and KVM_SET_XSAVE under KVM_CAP_XSAVE2 works with a xsave buffer larger than 4KB. Always use the new ioctls under KVM_CAP_XSAVE2 when KVM supports it. Signed-off-by: Ji

[PATCH v2 2/8] x86: Add AMX XTILECFG and XTILEDATA components

From: Jing Liu The AMX TILECFG register and the TMMx tile data registers are saved/restored via XSAVE, respectively in state component 17 (64 bytes) and state component 18 (8192 bytes). Add AMX feature bits to x86_ext_save_areas array to set up AMX components. Add structs that define the layout

[PATCH v2 5/8] x86: Add AMX CPUIDs enumeration

From: Jing Liu Add AMX primary feature bits XFD and AMX_TILE to enumerate the CPU's AMX capability. Meanwhile, add AMX TILE and TMUL CPUID leaf and subleaves which exist when AMX TILE is present to provide the maximum capability of TILE and TMUL. Signed-off-by: Jing Liu Signed-off-by: Yang Zhon

[PATCH v2 4/8] x86: Add XFD faulting bit for state components

From: Jing Liu Intel introduces XFD faulting mechanism for extended XSAVE features to dynamically enable the features in runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set as 1, it indicates support for XFD faulting of this state component. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong

[PATCH v2 1/8] x86: Fix the 64-byte boundary enumeration for extended state

From: Jing Liu The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1] indicate whether the extended state component locates on the next 64-byte boundary following the preceding state component when the compacted format of an XSAVE area is used. Right now, they are all zero because no supporte

[PATCH v2 0/8] AMX support in Qemu

Intel introduces Advanced Matrix Extensions (AMX) [1] feature that consists of configurable two-dimensional "TILE" registers and new accelerator instructions that operate on them. TMUL (Tile matrix MULtiply) is the first accelerator instruction set to use the new registers. Since AMX KVM patches h

[PATCH v2 3/8] x86: Grant AMX permission for guest

Kernel allocates 4K xstate buffer by default. For XSAVE features which require large state component (e.g. AMX), Linux kernel dynamically expands the xstate buffer only after the process has acquired the necessary permissions. Those are called dynamically- enabled XSAVE features (or dynamic xfeatur

Re: [PATCH 28/31] vdpa: Expose VHOST_F_LOG_ALL on SVQ

On Wed, Feb 16, 2022 at 11:54 PM Eugenio Perez Martin wrote: > > On Tue, Feb 8, 2022 at 9:25 AM Jason Wang wrote: > > > > > > 在 2022/2/1 下午7:45, Eugenio Perez Martin 写道: > > > On Sun, Jan 30, 2022 at 7:50 AM Jason Wang wrote: > > >> > > >> 在 2022/1/22 上午4:27, Eugenio Pérez 写道: > > >>> SVQ is abl

Re: [PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions

On Thu, Feb 17, 2022 at 3:15 AM Weiwei Li wrote: > > 在 2022/2/16 下午11:48, Christoph Muellner 写道: > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 39ffb883fc..04500fe352 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -764,6 +764,10 @@ static Property risc

[PATCH] tcg: Remove dh_alias indirection for dh_typecode

The dh_alias redirect is intended to handle TCG types as distinguished from C types. TCG does not distinguish signed int from unsigned int, because they are the same size. However, we need to retain this distinction for dh_typecode, lest we fail to extend abi types properly for the host call para

[PATCH v16 7/7] softmmu/dirtylimit: Implement dirty page rate limit

From: Hyman Huang(黄勇) Implement dirtyrate calculation periodically basing on dirty-ring and throttle virtual CPU until it reachs the quota dirty page rate given by user. Introduce qmp commands "set-vcpu-dirty-limit", "cancel-vcpu-dirty-limit", "query-vcpu-dirty-limit" to enable, disable, query d

[PATCH v16 4/7] softmmu/dirtylimit: Implement vCPU dirtyrate calculation periodically

From: Hyman Huang(黄勇) Introduce the third method GLOBAL_DIRTY_LIMIT of dirty tracking for calculate dirtyrate periodly for dirty page rate limit. Add dirtylimit.c to implement dirtyrate calculation periodly, which will be used for dirty page rate limit. Add dirtylimit.h to export util functions

[PATCH v16 3/7] migration/dirtyrate: Refactor dirty page rate calculation

From: Hyman Huang(黄勇) abstract out dirty log change logic into function global_dirty_log_change. abstract out dirty page rate calculation logic via dirty-ring into function vcpu_calculate_dirtyrate. abstract out mathematical dirty page rate calculation into do_calculate_dirtyrate, decouple it f

[PATCH v16 5/7] accel/kvm/kvm-all: Introduce kvm_dirty_ring_size function

From: Hyman Huang(黄勇) Introduce kvm_dirty_ring_size util function to help calculate dirty ring ful time. Signed-off-by: Hyman Huang(黄勇) Acked-by: Peter Xu --- accel/kvm/kvm-all.c| 5 + accel/stubs/kvm-stub.c | 5 + include/sysemu/kvm.h | 2 ++ 3 files changed, 12 insertions(+)

[PATCH v16 6/7] softmmu/dirtylimit: Implement virtual CPU throttle

From: Hyman Huang(黄勇) Setup a negative feedback system when vCPU thread handling KVM_EXIT_DIRTY_RING_FULL exit by introducing throttle_us_per_full field in struct CPUState. Sleep throttle_us_per_full microseconds to throttle vCPU if dirtylimit is in service. Signed-off-by: Hyman Huang(黄勇) Revie

[PATCH v16 2/7] cpus: Introduce cpu_list_generation_id

From: Hyman Huang(黄勇) Introduce cpu_list_generation_id to track cpu list generation so that cpu hotplug/unplug can be detected during measurement of dirty page rate. cpu_list_generation_id could be used to detect changes of cpu list, which is prepared for dirty page rate measurement. Signed-off

[PATCH v16 1/7] accel/kvm/kvm-all: Refactor per-vcpu dirty ring reaping

From: Hyman Huang(黄勇) Add a non-required argument 'CPUState' to kvm_dirty_ring_reap so that it can cover single vcpu dirty-ring-reaping scenario. Signed-off-by: Hyman Huang(黄勇) Reviewed-by: Peter Xu --- accel/kvm/kvm-all.c | 23 +-- 1 file changed, 13 insertions(+), 10 del

[PATCH v16 0/7] support dirty restraint on vCPU

From: Hyman Huang(黄勇) v16 - rebase on master - drop the unused typedef syntax in [PATCH v15 6/7] - add the Reviewed-by and Acked-by tags by the way v15 - rebase on master - drop the 'init_time_ms' parameter in function vcpu_calculate_dirtyrate - drop the 'setup' field in dirtylimit_state and

Re: [PATCH v3 7/7] hw/mips/gt64xxx_pci: Resolve gt64120_register()

On Wed, 16 Feb 2022, Bernhard Beschow wrote: Now that gt64120_register() lost its pic parameter, there is an opportunity to remove it. gt64120_register() is old style by wrapping qdev API, and the new style is to use qdev directly. So take the opportunity and modernize the code. Suggested-by: BA

Re: [PATCH v4 2/2] target/riscv: Enable Zicbo[m,z,p] instructions

在 2022/2/16 下午11:48, Christoph Muellner 写道: diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 39ffb883fc..04500fe352 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -764,6 +764,10 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg

Re: [PATCH] hw/arm/virt: Fix CPU's default NUMA node ID

On 1/26/22 5:14 PM, Igor Mammedov wrote: On Wed, 26 Jan 2022 13:24:10 +0800 Gavin Shan wrote: The default CPU-to-NUMA association is given by mc->get_default_cpu_node_id() when it isn't provided explicitly. However, the CPU topology isn't fully considered in the default association and it caus

Re: [PATCH v2 3/3] target/ppc/kvm: Use KVM_CAP_PPC_AIL_MODE_3 to determine cap-ail-mode-3 support

On Wed, Feb 16, 2022 at 04:39:03PM +1000, Nicholas Piggin wrote: > Use KVM_CAP_PPC_AIL_MODE_3 to determine cap-ail-mode-3 support for KVM > guests. Keep the fallback heuristic for KVM hosts that pre-date this > CAP. > > This is only proposed the KVM CAP has not yet been allocated. I will > ask to

Re: [PATCH 26/27] target/ppc: cpu_init: Move check_pow and QOM macros to a header

On Wed, Feb 16, 2022 at 10:06:26AM -0300, Fabiano Rosas wrote: > David Gibson writes: > > > On Tue, Feb 15, 2022 at 06:41:47PM -0300, Fabiano Rosas wrote: > >> These will need to be accessed from other files once we move the CPUs > >> code to separate files. > >> > >> Signed-off-by: Fabiano Rosa

Re: [PATCH v2 23/27] target/ppc: Rename spr_tcg.h to spr_common.h

On Wed, Feb 16, 2022 at 01:24:22PM -0300, Fabiano Rosas wrote: > Initial intent for the spr_tcg header was to expose the spr_read|write > callbacks that are only used by TCG code. However, although these > routines are TCG-specific, the KVM code needs access to env->sprs > which creation is current

Re: [PATCH v2 2/3] spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for H_SET_MODE hcall

On Wed, Feb 16, 2022 at 04:39:02PM +1000, Nicholas Piggin wrote: > The behaviour of the Address Translation Mode on Interrupt resource is > not consistently supported by all CPU versions or all KVM versions: > KVM-HV does not support mode 2, and does not support mode 3 on POWER7 or > early POWER9 p

Re: [PATCH v2 26/27] target/ppc: cpu_init: Move check_pow and QOM macros to a header

On Wed, Feb 16, 2022 at 01:24:25PM -0300, Fabiano Rosas wrote: > These will need to be accessed from other files once we move the CPUs > code to separate files. > > The check_pow_hid0 and check_pow_hid0_74xx are too specific to be > moved to a header so I'll deal with them later when splitting thi

Re: [PATCH 22/27] target/ppc: cpu_init: Rename register_ne_601_sprs

On Wed, Feb 16, 2022 at 10:19:40AM -0300, Fabiano Rosas wrote: > David Gibson writes: > > > On Tue, Feb 15, 2022 at 06:41:43PM -0300, Fabiano Rosas wrote: > >> The important part of this function is that it applies to non-embedded > >> CPUs, not that it also applies to the 601. We removed support

qemu crash 100% CPU with Ubuntu10.04 guest (solved)

Hi All, I'm cross-posting this from Reddit qemu_kvm, in case it helps in some way. I know my setup is ancient and unique; let me know if you would like more info. Symptoms: 1. Ubuntu10.04 32-bit guest locks up randomly between 0 and 30 days. 2. The console shows a CPU trace dump, nothing else log

Re: Adding a handshake to qemu-guest-agent

On Wed, Feb 16, 2022 at 10:12:36AM +0100, Markus Armbruster wrote: > Michael Roth writes: > > > On Mon, Feb 14, 2022 at 03:14:37PM +0100, Markus Armbruster wrote: > >> Cc: the qemu-ga maintainer > >> > >> John Snow writes: > >> > >> > [Moving our discussion upstream, because it stopped being b

Re: [PATCH v3 2/7] malta: Move PCI interrupt handling from gt64xxx_pci to piix4

On 16/2/22 23:45, Bernhard Beschow wrote: Handling PCI interrupts in piix4 increases cohesion and reduces differences between piix4 and piix3. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 55 ++ hw/mips/gt64xxx_pci.c | 60 -

Re: [PATCH v3 3/7] hw/isa/piix4: Resolve redundant i8259[] attribute

On 16/2/22 23:45, Bernhard Beschow wrote: This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4" where i8259[] was moved from MaltaState to PIIX4State to make the code movement more obvious. However, i8259[] seems redundant to *isa, so remove it. Signed-off-b

Re: [PATCH v3 7/7] hw/mips/gt64xxx_pci: Resolve gt64120_register()

On 16/2/22 23:45, Bernhard Beschow wrote: Now that gt64120_register() lost its pic parameter, there is an opportunity to remove it. gt64120_register() is old style by wrapping qdev API, and the new style is to use qdev directly. So take the opportunity and modernize the code. Suggested-by: BALAT

Re: [PATCH v3 6/7] hw/isa/piix4: Replace some magic IRQ constants

On 16/2/22 23:45, Bernhard Beschow wrote: This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably didn't want to use piix4-specific constants. Now that the interrupt handing resides in piix4, its constants can be

[PATCH v3 5/7] hw/isa/piix4: Resolve global instance variable

Now that piix4_set_irq's opaque parameter references own PIIX4State, piix4_dev becomes redundant. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c| 10 +++--- include/hw/southbridge/piix.h | 2 -- 2 files changed, 3 insertions(+), 9 del

Re: [PATCH v3] Hexagon (target/hexagon) properly handle NaN in dfmin/dfmax/sfmin/sfmax

On 2/16/22 15:39, Taylor Simpson wrote: The float??_minnum implementation differs from Hexagon for SNaN, it returns NaN, but Hexagon returns the other input. So, we use float??_minimum_number. For double precision, we check for QNaN and raise the invalid flag. I'm surprised that the behaviour

[PATCH v3 7/7] hw/mips/gt64xxx_pci: Resolve gt64120_register()

Now that gt64120_register() lost its pic parameter, there is an opportunity to remove it. gt64120_register() is old style by wrapping qdev API, and the new style is to use qdev directly. So take the opportunity and modernize the code. Suggested-by: BALATON Zoltan Signed-off-by: Bernhard Beschow

[PATCH v3 6/7] hw/isa/piix4: Replace some magic IRQ constants

This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably didn't want to use piix4-specific constants. Now that the interrupt handing resides in piix4, its constants can be used. Signed-off-by: Bernhard Beschow ---

[PATCH v3 3/7] hw/isa/piix4: Resolve redundant i8259[] attribute

This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4" where i8259[] was moved from MaltaState to PIIX4State to make the code movement more obvious. However, i8259[] seems redundant to *isa, so remove it. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 7

[PATCH v3 2/7] malta: Move PCI interrupt handling from gt64xxx_pci to piix4

Handling PCI interrupts in piix4 increases cohesion and reduces differences between piix4 and piix3. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 55 ++ hw/mips/gt64xxx_pci.c | 60 -- hw/mips/malta.c

[PATCH v3 4/7] hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq()

Passing PIIX4State rather than just the qemu_irq allows for resolving the global piix4_dev variable. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/is

[PATCH v3 0/7] malta: Fix PCI IRQ levels to be preserved during migration, cleanup

Tested with [1]: qemu-system-mipsel -M malta -kernel vmlinux-3.2.0-4-4kc-malta -hda \ debian_wheezy_mipsel_standard.qcow2 -append "root=/dev/sda1 console=tty0" It was possible to log in as root and `poweroff` the machine. Moreover, I ran: :$ make check Ok: 569 Expected

[PATCH v3 1/7] hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration

Based on commit e735b55a8c11dd455e31ccd4420e6c9485191d0c: piix_pci: eliminate PIIX3State::pci_irq_levels PIIX3State::pci_irq_levels are redundant which is already tracked by PCIBus layer. So eliminate them. The IRQ levels in the PCIBus layer are already preserved during migration. By reusi

Re: Portable inline asm to get address of TLS variable

On 2/16/22 18:46, Stefan Hajnoczi wrote: However, I wonder if the compiler might reuse a register that already contains the address. Then we'd have the coroutine problem again when qemu_coroutine_yield() is called between the earlier address calculation and the asm volatile statement. Yes, the

Re: [PATCH] ppc/spapr: Advertise StoreEOI for POWER10 compat guests

On 2/14/22 11:11, Cédric Le Goater wrote: When an interrupt has been handled, the OS notifies the interrupt controller with a EOI sequence. On a POWER9 and POWER10 systems using nit: s/a EOI sequence/an EOI sequence the XIVE interrupt controller, this can be done with a load or a store o

Re: [PULL v2 07/35] target/riscv: access cfg structure through DisasContext

On Wed, Feb 16, 2022 at 8:24 PM Philipp Tomsich wrote: > > Alistair, > > This PULL seems not to include the fixup (which you had intended to > squash into it) for the regression introduced (i.e. the condition > being inverted): > > https://patchwork.kernel.org/project/qemu-devel/patch/202202031

Re: [PATCH] tcg: Add 'signed' bit to typecodes

Richard Henderson writes: > The signed information is still there, merged with the typecode: > > #define dh_typecode_void 0 > #define dh_typecode_noreturn 0 > #define dh_typecode_i32 2 > #define dh_typecode_s32 3 > #define dh_typecode_i64 4 > #define dh_typecode_s64 5 > #define dh_typecode_ptr 6

Re: [PATCH] tests/tcg/s390x: Build tests with debian11

On 16/2/22 12:51, David Hildenbrand wrote: We need a newer compiler to build upcoming tests that test for z15 features with -march=z15. So let's do it similar to arm64 and powerpc, using an environment based on debian11 to build tests only. Cc: Thomas Huth Cc: Cornelia Huck Cc: Richard Henders

Re: [PATCH 0/6] hw/nvme: enhanced protection information (64-bit guard)

On Mon, Feb 14, 2022 at 01:30:23PM +0100, Klaus Jensen wrote: > From: Klaus Jensen > > This adds support for one possible new protection information format > introduced in TP4068 (and integrated in NVMe 2.0): the 64-bit CRC guard > and 48-bit reference tag. This version does not support storage t

Re: [PATCH 6/6] hw/nvme: 64-bit pi support

On Mon, Feb 14, 2022 at 01:30:29PM +0100, Klaus Jensen wrote: > @@ -384,6 +389,12 @@ static int nvme_ns_check_constraints(NvmeNamespace *ns, > Error **errp) > return -1; > } > > +if (ns->params.pif != NVME_PI_GUARD_16 && > +ns->params.pif != NVME_PI_GUARD_64) { > +

Re: [PATCH v2] tests/qemu-iotests: Rework the checks and spots using GNU sed

On Wed, Feb 16, 2022 at 01:54:54PM +0100, Thomas Huth wrote: > Instead of failing the iotests if GNU sed is not available (or skipping > them completely in the check-block.sh script), it would be better to > simply skip the bash-based tests that rely on GNU sed, so that the other > tests could stil

Re: [PATCH] tcg: Add 'signed' bit to typecodes

On 2/16/22 17:39, Keith Packard wrote: Commit 7319d83a (tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode) converted the tcg type system to a 3-bit field from two separate 1-bit fields. This subtly lost the 'signed' information from the types as it uses the dh_alias macro to reduce the typ

Re: [PULL 00/30] Misc mostly build system patches for 2022-02-15

On 2/16/22 15:41, Peter Maydell wrote: On Wed, 16 Feb 2022 at 14:03, Paolo Bonzini wrote: On 2/16/22 10:56, Peter Maydell wrote: Hi; this fails to build on OpenBSD (on the tests/vm/ setup). Meson thinks it's found OpenGL: OpenGL support (epoxy) : YES 1.5.4 but either it's wrong

Re: [Virtio-fs] [PULL 00/12] virtiofs queue

; > > Merge remote-tracking branch > > 'remotes/alistair/tags/pull-riscv-to-apply-20220216' into staging > > (2022-02-16 09:57:11 +) > > > > are available in the Git repository at: > > > > https://gitl

Re: Portable inline asm to get address of TLS variable

* Stefan Hajnoczi: > I'm basically asking whether the &tls_var input operand is treated as > volatile and part of the inline assembly or whether it's just regular > C code that the compiler may optimize with the surrounding function? &tls_var is evaluated outside of the inline assembly, any compi

[PATCH v5 2/3] s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1

TCG implements everything we need to run basic z15 OS+software Signed-off-by: David Miller --- hw/s390x/s390-virtio-ccw.c | 3 +++ target/s390x/cpu_models.c | 6 +++--- target/s390x/gen-features.c | 7 +-- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/s390x/s390-virti

[PATCH v5 1/3] s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x

resolves: https://gitlab.com/qemu-project/qemu/-/issues/737 implements: AND WITH COMPLEMENT (NCRK, NCGRK) NAND (NNRK, NNGRK) NOT EXCLUSIVE OR (NXRK, NXGRK) NOR (NORK, NOGRK) OR WITH COMPLEMENT(OCRK, OCGRK) SELECT(SELR, SELGR) SELECT HIGH

[PATCH v5 3/3] tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3

tests/tcg/s390x/mie3-compl.c: [N]*K instructions tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction tests/tcg/s390x/mie3-sel.c: SELECT instruction Signed-off-by: David Miller --- tests/tcg/s390x/Makefile.target | 5 ++- tests/tcg/s390x/mie3-compl.c| 55 + tests

Re: Portable inline asm to get address of TLS variable

* Stefan Hajnoczi: > On Wed, 16 Feb 2022 at 18:14, Florian Weimer wrote: >> >> * Stefan Hajnoczi: >> >> > I've been trying to make the inline asm that gets the address of a TLS >> > variable for QEMU coroutines pass QEMU's GitLab CI. >> > https://gitlab.com/stefanha/qemu/-/blob/coroutine-tls-fix/

[PATCH v5 0/3] s390x: Add partial z15 support and tests

Add partial support for s390x z15 ga1 and specific tests for mie3 v4 -> v5: * Readd missing tests/tcg/s390x/mie3-*.c to patch v3 -> v4: * Change popcnt encoding RRE -> RRF_c * Remove redundant code op_sel -> op_loc * Cleanup for checkpatch.pl * Readded mie3-* to Makefile.target v2 -> v3: * Move

Re: [PATCH v4 3/3] tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3

On 16.02.22 21:18, David Miller wrote: > That is strange, if I unstage them show status they are set to be committed: > > null@rygar:~/projects/qemu/build$ git reset --soft HEAD~1 > null@rygar:~/projects/qemu/build$ git status > On branch t2 > Changes to be committed: > (use "git restore --stage

Re: Portable inline asm to get address of TLS variable

On Wed, 16 Feb 2022 at 20:28, Stefan Hajnoczi wrote: > > On Wed, 16 Feb 2022 at 18:14, Florian Weimer wrote: > > > > * Stefan Hajnoczi: > > > > > I've been trying to make the inline asm that gets the address of a TLS > > > variable for QEMU coroutines pass QEMU's GitLab CI. > > > https://gitlab.c

[PATCH v4 0/3] s390x: Add partial z15 support and tests

Add partial support for s390x z15 ga1 and specific tests for mie3 v3 -> v4: * Change popcnt encoding RRE -> RRF_c * Remove redundant code op_sel -> op_loc * Cleanup for checkpatch.pl * Readded mie3-* to Makefile.target v2 -> v3: * Moved tests to separate patch. * Combined patches into series.

Re: Portable inline asm to get address of TLS variable

On Wed, 16 Feb 2022 at 18:14, Florian Weimer wrote: > > * Stefan Hajnoczi: > > > I've been trying to make the inline asm that gets the address of a TLS > > variable for QEMU coroutines pass QEMU's GitLab CI. > > https://gitlab.com/stefanha/qemu/-/blob/coroutine-tls-fix/include/qemu/coroutine-tls.h

[PATCH v4 3/3] tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3

tests/tcg/s390x/mie3-compl.c: [N]*K instructions tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction tests/tcg/s390x/mie3-sel.c: SELECT instruction Signed-off-by: David Miller --- tests/tcg/s390x/Makefile.target | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/tcg/s390x

Re: [PATCH v4 3/3] tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3

On 16.02.22 21:03, David Miller wrote: > tests/tcg/s390x/mie3-compl.c: [N]*K instructions > tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction > tests/tcg/s390x/mie3-sel.c: SELECT instruction > > Signed-off-by: David Miller > --- > tests/tcg/s390x/Makefile.target | 5 - > 1 file changed, 4 ins

[PATCH v4 14/18] iotests.py: add qemu_io_pipe_and_status()

Add helper that returns both status and output, to be used in the following commit Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/iotests.py | 4 1 file changed, 4 insertions(+) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index 6ba65eb1ff.

Re: [PATCH v4 3/3] tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3

That is strange, if I unstage them show status they are set to be committed: null@rygar:~/projects/qemu/build$ git reset --soft HEAD~1 null@rygar:~/projects/qemu/build$ git status On branch t2 Changes to be committed: (use "git restore --staged ..." to unstage) modified: ../tests/tcg/s

[PATCH v4 17/18] qapi: backup: add immutable-source parameter

We are on the way to implement internal-backup with fleecing scheme, which includes backup job copying from fleecing block driver node (which is target of copy-before-write filter) to final target of backup. This job doesn't need own filter, as fleecing block driver node is a kind of snapshot, it's

Re: [PATCH v4 2/3] s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1

On 16.02.22 21:03, David Miller wrote: > TCG implements everything we need to run basic z15 OS+software > > Signed-off-by: David Miller Booting Fedora34 with an upstream kernel (compiled for z15) did work. Reviewed-by: David Hildenbrand Thanks! -- Thanks, David / dhildenb

[PATCH v4 2/3] s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1

TCG implements everything we need to run basic z15 OS+software Signed-off-by: David Miller --- hw/s390x/s390-virtio-ccw.c | 3 +++ target/s390x/cpu_models.c | 6 +++--- target/s390x/gen-features.c | 7 +-- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/s390x/s390-virti

[PATCH v4 18/18] iotests/image-fleecing: test push backup with fleecing

Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/tests/image-fleecing | 121 ++-- tests/qemu-iotests/tests/image-fleecing.out | 63 ++ 2 files changed, 152 insertions(+), 32 deletions(-) diff --git a/tests/qemu-iotests/tests/image-fleecing b/tests/

Re: [PATCH v4 1/3] s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x

> > +/* SELECT */ > +C(0xb9f0, SELR,RRF_a, MIE3, r2, r3, new, r1_32, loc, 0) > +C(0xb9e3, SELGR, RRF_a, MIE3, r2, r3, r1, 0, loc, 0) > +/* SELECT HIGH */ > +C(0xb9c0, SELFHR, RRF_a, MIE3, r2, r3, new, r1_32h, loc, 0) > + Heh, note how I inverted r2 and r3 in my proposal? That'

[PATCH v4 16/18] block: blk_root(): return non-const pointer

In the following patch we'll want to pass blk children to block-copy. Const pointers are not enough. So, return non const pointer from blk_root(). Signed-off-by: Vladimir Sementsov-Ogievskiy --- include/sysemu/block-backend.h | 2 +- block/block-backend.c | 2 +- 2 files changed, 2 inse

[PATCH v4 12/18] block: copy-before-write: realize snapshot-access API

Current scheme of image fleecing looks like this: [guest][NBD export] | | |root | root v v [copy-before-write] -> [temp.qcow2] | target | |file

[PATCH v4 1/3] s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x

resolves: https://gitlab.com/qemu-project/qemu/-/issues/737 implements: AND WITH COMPLEMENT (NCRK, NCGRK) NAND (NNRK, NNGRK) NOT EXCLUSIVE OR (NXRK, NXGRK) NOR (NORK, NOGRK) OR WITH COMPLEMENT(OCRK, OCGRK) SELECT(SELR, SELGR) SELECT HIGH

[PATCH v4 11/18] block: introduce snapshot-access filter

The filter simply utilizes snapshot-access API of underlying block node. In further patches we want to use it like this: [guest] [NBD export] || | root | root v file v [copy-before-write]<--[sna

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