Re: [PATCH v2] target/i386: Add kvm_get_one_msr helper

Ping... Does this v2 meet the requirement? On 1/30/2022 7:07 AM, Yang Weijiang wrote: When try to get one msr from KVM, I found there's no such kind of existing interface while kvm_put_one_msr() is there. So here comes the patch. It'll remove redundant preparation code before finally call KVM_G

[PULL 40/40] docs/system: riscv: Update description of CPU

From: Yu Li Since the hypervisor extension been non experimental and enabled for default CPU, the previous command is no longer available and the option `x-h=true` or `h=true` is also no longer required. Signed-off-by: Yu Li Reviewed-by: Alistair Francis Message-Id: <9040401e-8f87-ef4a-d840-67

[PULL 39/40] target/riscv: add support for svpbmt extension

From: Weiwei Li - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed

[PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

From: Anup Patel We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward all wired interrupts

[PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

From: Weiwei Li For non-leaf PTEs, the D, A, and U bits are reserved for future standard use. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <20220204022658.18097-3-liwei...@iscas.ac.cn> Signed-off-by: Alistair Francis

[PULL 37/40] target/riscv: add support for svnapot extension

From: Weiwei Li - add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <20220204022658.18097-4

[PULL 35/40] target/riscv: Ignore reserved bits in PTE for RV64

From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual

[PULL 38/40] target/riscv: add support for svinval extension

From: Weiwei Li - sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check - do nothing other than extension check for sfence.w.inval and sfence.inval.ir Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel

[PULL 29/40] hw/intc: Add RISC-V AIA APLIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for wired interrupts called APLIC (Advanced Platform Level Interrupt Controller). The APLIC is capabable of forwarding wired interupts to RISC-V HARTs directly or as MSIs (Message Signaled Interup

[PULL 30/40] hw/riscv: virt: Add optional AIA APLIC support to virt machine

From: Anup Patel We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel Signed-off-by: Anup Patel

[PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs

From: Anup Patel To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by: Anu

[PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART

From: Anup Patel We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank

[PULL 33/40] docs/system: riscv: Document AIA options for virt machine

From: Anup Patel We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-23-a...@

[PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level gue

[PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs

From: Anup Patel The AIA specificaiton adds interrupt filtering support for M-mode and HS-mode. Using AIA interrupt filtering M-mode and H-mode can take local interrupt 13 or above and selectively inject same local interrupt to lower privilege modes. At the moment, we don't have any local interr

[PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when available

From: Anup Patel We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Cha

[PULL 20/40] target/riscv: Implement AIA local interrupt priorities

From: Anup Patel The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by subseque

[PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs

From: Anup Patel The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang

[PULL 21/40] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

From: Anup Patel The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-11-a...@brainf

[PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs

From: Anup Patel The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank

[PULL 18/40] target/riscv: Add defines for AIA CSRs

From: Anup Patel The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-8-

[PULL 24/40] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

From: Anup Patel The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang Message-id: 20220204174700.534953-14-a...@brainfault.org [ Changed by AF: -

[PULL 19/40] target/riscv: Allow AIA device emulation to set ireg rmw callback

From: Anup Patel The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-i

[PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation

From: Anup Patel The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example,

[PULL 15/40] target/riscv: Improve delivery of guest external interrupts

From: Anup Patel The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish r

[PULL 22/40] target/riscv: Implement AIA hvictl and hviprioX CSRs

From: Anup Patel The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174

[PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs

From: Anup Patel A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-3-a...@brainfault.org Signed-off-by: A

[PULL 17/40] target/riscv: Add AIA cpu feature

From: Anup Patel We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Alista

[PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

From: Anup Patel We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin M

[PULL 14/40] target/riscv: Implement hgeie and hgeip CSRs

From: Anup Patel The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Me

[PULL 11/40] target/riscv: Fix vill field write in vtype

From: LIU Zhiwei The guest should be able to set the vill bit as part of vsetvl. Currently we may set env->vill to 1 in the vsetvl helper, but there is nowhere that we set it to 0, so once it transitions to 1 it's stuck there until the system is reset. Signed-off-by: LIU Zhiwei Reviewed-by: Ri

[PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr

From: Philipp Tomsich As the number of extensions is growing, copying them individiually into the DisasContext will scale less and less... instead we populate a pointer to the RISCVCPUConfig structure in the DisasContext. This adds an extra indirection when checking for the availability of an ex

[PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps

From: Philipp Tomsich The XVentanaCondOps extension is supported by VRULL on behalf of the Ventana Micro. Add myself as a point-of-contact. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220202005249.3566542-8-philipp.toms...@vrull.

[PULL 09/40] target/riscv: Add XVentanaCondOps custom extension

From: Philipp Tomsich This adds the decoder and translation for the XVentanaCondOps custom extension (vendor-defined by Ventana Micro Systems), which is documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf This com

[PULL 08/40] target/riscv: iterate over a table of decoders

From: Philipp Tomsich To split up the decoder into multiple functions (both to support vendor-specific opcodes in separate files and to simplify maintenance of orthogonal extensions), this changes decode_op to iterate over a table of decoders predicated on guard functions. This commit only adds

[PULL 04/40] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'

From: Philipp Tomsich Signed-off-by: Philipp Tomsich Reviewed-by: Alistair Francis Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Message-Id: <20220202005249.3566542-2-philipp.toms...@vrull.eu> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 78 +

[PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128

From: Frédéric Pétrot The addition of uxl support in gdbstub adds a few checks on the maximum register length, but omitted MXL_RV128, an experimental feature. This patch makes rv128 react as rv64, as previously. Signed-off-by: Frédéric Pétrot Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: LI

[PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext

From: Philipp Tomsich The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow copies (in DisasContext) of some of the elements available in the RISCVCPUConfig structure. This commit redirects accesses to use the cfg_ptr copied into DisasContext and removes the shallow copies. Sig

[PULL 01/40] include: hw: remove ibex_plic.h

From: Wilfred Mallawa This patch removes the left-over/unused `ibex_plic.h` file. Previously used by opentitan, which now follows the RISC-V standard and uses the SiFivePlicState. Fixes: 434e7e021 ("hw/intc: Remove the Ibex PLIC") Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Re

[PULL 07/40] target/riscv: access cfg structure through DisasContext

From: Philipp Tomsich The Zb[abcs] support code still uses the RISCV_CPU macros to access the configuration information (i.e., check whether an extension is available/enabled). Now that we provide this information directly from DisasContext, we can access this directly via the cfg_ptr field. Si

[PULL 02/40] Allow setting up to 8 bytes with the generic loader

From: Petr Tesarik The documentation for the generic loader says that "the maximum size of the data is 8 bytes". However, attempts to set data-len=8 trigger the following assertion failure: ../hw/core/generic-loader.c:59: generic_loader_reset: Assertion `s->data_len < sizeof(s->data)' failed.

[PULL 00/40] riscv-to-apply queue

From: Alistair Francis The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08 11:40:08 +) are available in the Git repository at: g...@github.com:alistair23/qem

Re: [PATCH v4 04/12] mm/shmem: Support memfile_notifier

On 1/18/22 05:21, Chao Peng wrote: It maintains a memfile_notifier list in shmem_inode_info structure and implements memfile_pfn_ops callbacks defined by memfile_notifier. It then exposes them to memfile_notifier via shmem_get_memfile_notifier_info. We use SGP_NOALLOC in shmem_get_lock_pfn since

Re: [PATCH v4 01/12] mm/shmem: Introduce F_SEAL_INACCESSIBLE

On 1/18/22 05:21, Chao Peng wrote: From: "Kirill A. Shutemov" Introduce a new seal F_SEAL_INACCESSIBLE indicating the content of the file is inaccessible from userspace through ordinary MMU access (e.g., read/write/mmap). However, the file content can be accessed via a different mechanism (e.g.

[RFC PATCH 25/25] virtio-snd: Replaced AUD_log with tracepoints

Replaced the use of AUD_log via macros in virtio sound with tracepoints. Signed-off-by: Shreyansh Chouhan --- hw/audio/trace-events | 14 +++ hw/audio/virtio-snd.c | 55 +-- 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/hw/audio/

[RFC PATCH 24/25] virtio-snd: Add event vq and a handler stub

Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index 80a34e1207..81a478d039 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/virtio-snd.c @@ -1080,6 +1080,18 @@ static vo

[RFC PATCH 21/25] virtio-snd: Replaced goto with if else

Removed goto from the ctrl vq handler and added an if else branch for error handling. Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 21 - 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index 7b80a927

[RFC PATCH 17/25] virtio-snd: Add default configs to realize fn

Added default configurations for streams and jacks in the realize function. Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 40 1 file changed, 40 insertions(+) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index b7c4dc691d..5ed

[RFC PATCH 19/25] virtio-snd: Add start/stop handler

Added handlers for VIRTIO_SND_PCM_START and VIRTIO_SND_PCM_STOP. Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 35 +-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index b74c9e4a1f..1b3

[RFC PATCH 14/25] virtio-snd: Add VIRTIO_SND_R_PCM_INFO handler

Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 88 ++- 1 file changed, 87 insertions(+), 1 deletion(-) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index aec3e86db2..a53a6be168 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/v

[RFC PATCH 12/25] virtio-snd: Add VIRTIO_SND_R_JACK_INFO handler

Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 81 +-- 1 file changed, 79 insertions(+), 2 deletions(-) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index a87922f91b..c2af26f3cb 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/

[RFC PATCH 18/25] virtio-snd: Add callback for SWVoiceOut

Added the callback for writing audio using AUD_write. The callback uses two helper functions for reading the buffers from the streams and handling the buffers that were written. initialized the SWVoiceOut using this callback. Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 254 +

[RFC PATCH 23/25] virtio-snd: Add xfer handler

The handler demultiplexes the buffers recieved in the tx/rx virtqueue. It uses a helper function for adding these buffers, (along with the entire virtqueue element,) to their respective streams. Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 71 +

[RFC PATCH 11/25] virtio-snd: Add control virtqueue handler

The handler prints the requests that came in the ctrl virtqueue. Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index 40829fa329..a87922f91b

[RFC PATCH 13/25] virtio-snd: Add stub for VIRTIO_SND_R_JACK_REMAP handler

Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index c2af26f3cb..aec3e86db2 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/virtio-snd.c @@ -167

[RFC PATCH 22/25] virtio-snd: Add code to device unrealize function

Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index cb83db0e89..7dd89c444b 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/virtio-snd.c @@ -1093,8 +1093

[RFC PATCH 09/25] virtio-snd: Add code for the realize function

Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index afa38adee7..b51f6c7523 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/virtio-snd.c @@ -89,8 +8

[RFC PATCH 10/25] virtio-snd: Add macros for logging

Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 8 1 file changed, 8 insertions(+) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index b51f6c7523..40829fa329 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/virtio-snd.c @@ -39,6 +39,10 @@ #define VIRTIO_SOUND

[RFC PATCH 20/25] virtio-snd: Add VIRTIO_SND_R_PCM_RELEASE handler

Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 82 ++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index 1b3e1f75f4..7b80a92737 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/v

[RFC PATCH 16/25] virtio-snd: Add VIRTIO_SND_R_PCM_PREPARE handler

The handler doesn't intialize the SWVoiceOut streams for now. Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 203 +- 1 file changed, 202 insertions(+), 1 deletion(-) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index acb126f392

[RFC PATCH 06/25] virtio-snd: Add PCI wrapper code for VirtIOSound

Added the virito-snd.c file which contains a wrapper for combining the device with the VirtIOPCIProxy. Signed-off-by: Shreyansh Chouhan --- hw/virtio/meson.build | 1 + hw/virtio/virtio-snd-pci.c | 72 ++ 2 files changed, 73 insertions(+) create mode 10

[RFC PATCH 08/25] virtio-snd: Add code for get config function

Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index ae438aa7ec..afa38adee7 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/virtio-snd.c @@ -41,6 +41,15 @@ static void virti

[RFC PATCH 05/25] virtio-snd: Add device implementation structures

Added jacks, pcm streams and the VirtIOSound structure for actual device implementation. Signed-off-by: Shreyansh Chouhan --- include/hw/virtio/virtio-snd.h | 66 ++ 1 file changed, 66 insertions(+) diff --git a/include/hw/virtio/virtio-snd.h b/include/hw/virtio/

[RFC PATCH 15/25] virtio-snd: Add VIRITO_SND_R_PCM_SET_PARAMS handle

Added handler for the VIRTIO_SND_R_PCM_SET_PARAMS control request. The handler was split up into two functions in so that the code could be reused in the realize function. Signed-off-by: Shreyansh Chouhan --- hw/audio/virtio-snd.c | 116 +- 1 file changed,

[RFC PATCH 03/25] virtio-snd: Add PCM control structures

Added structures for handle PCM control requests to the heaer file. Signed-off-by: Shreyansh Chouhan --- include/hw/virtio/virtio-snd.h | 123 + 1 file changed, 123 insertions(+) diff --git a/include/hw/virtio/virtio-snd.h b/include/hw/virtio/virtio-snd.h index f

[RFC PATCH 01/25] virtio-snd: Add virtio sound header file

Added device configuration and common definitions to the header file. Signed-off-by: Shreyansh Chouhan --- include/hw/virtio/virtio-snd.h | 97 ++ 1 file changed, 97 insertions(+) create mode 100644 include/hw/virtio/virtio-snd.h diff --git a/include/hw/virtio/v

[RFC PATCH 07/25] virtio-snd: Add properties for class init

Added properties and function stubs for virtio sound device class init. Signed-off-by: Shreyansh Chouhan --- hw/audio/Kconfig | 5 ++ hw/audio/meson.build | 1 + hw/audio/virtio-snd.c | 126 ++ 3 files changed, 132 insertions(+) create mode 1006

[RFC PATCH 04/25] virtio-snd: Add chmap control structures

Added structures for handling channel map control requests to the header file. Signed-off-by: Shreyansh Chouhan --- include/hw/virtio/virtio-snd.h | 57 ++ 1 file changed, 57 insertions(+) diff --git a/include/hw/virtio/virtio-snd.h b/include/hw/virtio/virtio-snd

[RFC PATCH 02/25] virtio-snd: Add jack control structures

Added structures for handling jack control requests to the header file. Signed-off-by: Shreyansh Chouhan --- include/hw/virtio/virtio-snd.h | 40 ++ 1 file changed, 40 insertions(+) diff --git a/include/hw/virtio/virtio-snd.h b/include/hw/virtio/virtio-snd.h inde

[RFC PATCH v2 00/25] Virtio Sound card Implementation

The second RFC for implementing the VirtIO Sound card as described in the virtio specs. Sorry for the absence of activity on this. The output from the sound card works. What remains to be done: - Features defined in PCM features. (Eg message polling) - Channel maps - Jack remaps - Input I will w

Re: [PATCH v1 09/11] tests/tcg: build sha1-vector with O3 and compare

On 2/12/22 03:03, Alex Bennée wrote: The aim of this is to test code generation for vectorised operations. Unfortunately gcc struggles to do much with the messy sha1 code (try -fopt-info-vec-missed to see why). However it's better than nothing. We assume the non-vectorised output is gold and bar

Re: [PATCH v1 05/11] tests/docker: introduce debian-riscv64-test-cross

On 2/12/22 03:03, Alex Bennée wrote: Cross building QEMU for riscv64 still involves messing about with sid and ports. However for building tests we can have a slimmer compiler only container which should be more stable. Signed-off-by: Alex Bennée --- .gitlab-ci.d/container-cross.yml

Re: [PATCH v1 04/11] tests/docker: update debian-arm64-cross with lci-tool

On 2/12/22 03:03, Alex Bennée wrote: Using lci-tool update debian-arm64-cross to a Debian 11 based system. As a result we can drop debian-arm64-test-cross just for building tests. Signed-off-by: Alex Bennée --- .gitlab-ci.d/container-cross.yml | 10 +- tests/docker/Makefile.incl

Re: [RFC PATCH 0/3] tests/tcg/ppc64le: fix the build of TCG tests with Clang

On 09/02/2022 09:31, Cédric Le Goater wrote: Hello Matheus, [ Adding Miroslav ] On 2/8/22 21:31, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Based-on: https://lists.gnu.org/archive/html/qemu-devel/2022-01/msg06506.html As the configuration scripts used -mbig and -mlittle, bui

Adding a handshake to qemu-guest-agent

[Moving our discussion upstream, because it stopped being brief and simple.] What about something like this: Add a new "request-negotiation" command to qemu-guest-agent 7.0.0. [Modern client to unknown server] 1. A modern client connects to a server of unknown version, and without waiting, issue

Re: [PATCH] scripts/qapi: minor delinting

On Fri, Feb 11, 2022 at 12:11 PM John Snow wrote: > > On Fri, Feb 11, 2022 at 6:58 AM Markus Armbruster wrote: > > > > John Snow writes: > > > > > On Thu, Feb 10, 2022 at 10:56 AM Markus Armbruster > > > wrote: > > >> > > >> John Snow writes: > > >> > > >> > Just cleaning up some cobwebs. > >

[PATCH v2] scripts/qapi: minor delinting

Get isort and pylint tools passing again. Signed-off-by: John Snow --- scripts/qapi/commands.py | 2 +- scripts/qapi/pylintrc| 15 +-- scripts/qapi/types.py| 6 +- scripts/qapi/visit.py| 6 +- 4 files changed, 16 insertions(+), 13 deletions(-) diff --git a/scr

[PATCH v11 4/4] target/ppc: trigger PERFM EBBs from power8-pmu.c

This patch adds the EBB exception support that are triggered by Performance Monitor alerts. This happens when a Performance Monitor alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set. fire_PMC_interrupt() will execute a new ebb_perfm_excp() helper that will check for MMCR0_EBE, BESCR_PME a

[PATCH v11 3/4] target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions

PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB exceptions that had to be postponed because the thread wasn't in problem state at the time the event-based branch was supposed to occur. ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB exception and External EBB

[PATCH v11 2/4] target/ppc: finalize pre-EBB PMU logic

There are still PMU exclusive bits to handle in fire_PMC_interrupt() before implementing the EBB support. Let's finalize it now to avoid dealing with PMU and EBB logic at the same time in the next patches. fire_PMC_interrupt() will fire an Performance Monitor alert depending on MMCR0_PMAE. If we a

[PATCH v11 1/4] target/ppc: fix indent of function parameters

Fix indentation of powerpc_set_excp_state() and ppc_excp_apply_ail() parameters. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza --- target/ppc/excp_helper.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_h

[PATCH v11 0/4] PMU-EBB support for PPC64 TCG

Hi, This new version makes a few modifications to make the EBB support more generic. A new patch (3) was added to implement PPC_INTERRUPT_EBB and its two internal exceptions described by ISA v3.1: POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB. When receiving an EBB interrupt we check BESCR

Re: [PATCH v1 02/11] tests/docker: add NOUSER for alpine image

On Fri, Feb 11, 2022 at 05:51:25PM +, Alex Bennée wrote: > > Daniel P. Berrangé writes: > > > On Fri, Feb 11, 2022 at 04:03:00PM +, Alex Bennée wrote: > >> The alpine image doesn't have a standard useradd binary so disable > >> this convenience feature for it. > > > > Hmm, can you elabor

[PULL 0/3] Block layer patches

The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08 11:40:08 +) are available in the Git repository at: https://gitlab.com/kmwolf/qemu.git tags/for-upstream f

[PULL 3/3] hw/block/fdc-isa: Respect QOM properties when building AML

From: Bernhard Beschow Other ISA devices such as serial-isa use the properties in their build_aml functions. fdc-isa not using them is probably an oversight. Signed-off-by: Bernhard Beschow Message-Id: <20220209191558.30393-1-shen...@gmail.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by

[PULL 1/3] block: Lock AioContext for drain_end in blockdev-reopen

bdrv_subtree_drained_end() requires the caller to hold the AioContext lock for the drained node. Not doing this for nodes outside of the main AioContext leads to crashes when AIO_WAIT_WHILE() needs to wait and tries to temporarily release the lock. Fixes: 3908b7a8994fa5ef7a89aa58cd5a02fc58141592 R

[PULL 2/3] iotests: Test blockdev-reopen with iothreads and throttling

The 'throttle' block driver implements .bdrv_co_drain_end, so blockdev-reopen will have to wait for it to complete in the polling loop at the end of qmp_blockdev_reopen(). This makes AIO_WAIT_WHILE() release the AioContext lock, which causes a crash if the lock hasn't correctly been taken. Signed-

Re: [PATCH v1 02/11] tests/docker: add NOUSER for alpine image

Daniel P. Berrangé writes: > On Fri, Feb 11, 2022 at 04:03:00PM +, Alex Bennée wrote: >> The alpine image doesn't have a standard useradd binary so disable >> this convenience feature for it. > > Hmm, can you elaborate on the problem here ? > > IIUC, the NOUSER env was just about controllin

Re: [PATCH v2 1/8] tests/qemu-iotests/testrunner: Allow parallel test invocations

Am 11.02.2022 um 17:14 hat Hanna Reitz geschrieben: > On 11.02.22 17:00, Kevin Wolf wrote: > > Am 11.02.2022 um 14:53 hat Thomas Huth geschrieben: > > > On 11/02/2022 10.29, Kevin Wolf wrote: > > > > Am 09.02.2022 um 11:15 hat Thomas Huth geschrieben: > > > > > If multiple tests run in parallel, th

Re: [PATCH] scripts/qapi: minor delinting

On Fri, Feb 11, 2022 at 6:58 AM Markus Armbruster wrote: > > John Snow writes: > > > On Thu, Feb 10, 2022 at 10:56 AM Markus Armbruster > > wrote: > >> > >> John Snow writes: > >> > >> > Just cleaning up some cobwebs. > >> > > >> > Signed-off-by: John Snow > >> > --- > >> > scripts/qapi/comm

[PATCH] hw/virtio: vdpa: Fix leak of host-notifier memory-region

If call virtio_queue_set_host_notifier_mr fails, should free host-notifier memory-region. This problem can trigger a coredump with some vDPA drivers (mlx5, but not with the vdpasim), if we unplug the virtio-net card from the guest after a stop/start. The same fix has been done for vhost-user: 1

Re: [PATCH v5 20/43] hw/cxl/device: Add a memory device (8.2.8.5)

On 22-02-11 16:45:19, Jonathan Cameron wrote: > On Fri, 11 Feb 2022 07:50:00 -0800 > Ben Widawsky wrote: > > > On 22-02-02 14:10:14, Jonathan Cameron wrote: > > > From: Ben Widawsky > > > > > > A CXL memory device (AKA Type 3) is a CXL component that contains some > > > combination of volatile

Re: [PATCH 1/6] tests/qemu-iotests: Improve the check for GNU sed

On 11/02/2022 17.14, Eric Blake wrote: On Tue, Feb 08, 2022 at 03:52:19PM +0100, Thomas Huth wrote: The current code with $SED has been introduced almost three years ago already...   Can’t we just do `alias sed=gsed`? Maybe ... but let's ask Philippe and Kevin first, who Signed-off commit b

Re: [PATCH v6 17/43] hw/cxl/device: Add a memory device (8.2.8.5)

On Fri, 11 Feb 2022 12:07:21 + Jonathan Cameron wrote: > From: Ben Widawsky > > A CXL memory device (AKA Type 3) is a CXL component that contains some > combination of volatile and persistent memory. It also implements the > previously defined mailbox interface as well as the memory device

Re: [PATCH] hw/block/fdc-isa: Respect QOM properties when building AML

Am 09.02.2022 um 20:15 hat Bernhard Beschow geschrieben: > Other ISA devices such as serial-isa use the properties in their > build_aml functions. fdc-isa not using them is probably an oversight. > > Signed-off-by: Bernhard Beschow Thanks, applied to the block branch. Kevin

[PATCH v4 11/13] audio/dbus: Fix building with modules on macOS

When configuring QEMU with --enable-modules we get on macOS: --- stderr --- Dependency ui-dbus cannot be satisfied ui-dbus depends on pixman and opengl, so add these dependencies to audio-dbus. Fixes: 739362d420 ("audio: add "dbus" audio backend") Reviewed-by: Li Zhang Signed-off-by: Philip

[PATCH v4 13/13] gitlab-ci: Support macOS 12 via cirrus-run

Add support for macOS 12 build on Cirrus-CI, similarly to commit 0e103a65ba1 ("gitlab: support for ... macOS 11 via cirrus-run"), but with the following differences: - Enable modules (configure --enable-modules) - Do not run softfloat3 tests (make check-softfloat) Generate the vars file by calli

Re: [PATCH v5 20/43] hw/cxl/device: Add a memory device (8.2.8.5)

On Fri, 11 Feb 2022 07:50:00 -0800 Ben Widawsky wrote: > On 22-02-02 14:10:14, Jonathan Cameron wrote: > > From: Ben Widawsky > > > > A CXL memory device (AKA Type 3) is a CXL component that contains some > > combination of volatile and persistent memory. It also implements the > > previously d

[PATCH v4 09/13] block/file-posix: Remove a deprecation warning on macOS 12

When building on macOS 12 we get: block/file-posix.c:3335:18: warning: 'IOMasterPort' is deprecated: first deprecated in macOS 12.0 [-Wdeprecated-declarations] kernResult = IOMasterPort( MACH_PORT_NULL, &masterPort ); ^~~~ IOMainPort Replace

[PATCH v4 10/13] audio/coreaudio: Remove a deprecation warning on macOS 12

When building on macOS 12 we get: audio/coreaudio.c:50:5: error: 'kAudioObjectPropertyElementMaster' is deprecated: first deprecated in macOS 12.0 [-Werror,-Wdeprecated-declarations] kAudioObjectPropertyElementMaster ^ kAudioObjectPropertyElemen

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