[PATCH v4 5/5] tcg/sparc: Support unaligned access for user-only

This is kinda sorta the opposite of the other tcg hosts, where we get (normal) alignment checks for free with host SIGBUS and need to add code to support unaligned accesses. This inline code expansion is somewhat large, but it takes quite a few instructions to make a function call to a helper anyw

[PATCH v4 4/5] tcg/sparc: Add tcg_out_jmpl_const for better tail calls

Due to mapping changes, we now rarely place the code_gen_buffer near the main executable. Which means that direct calls will now rarely be in range. So, always use indirect calls for tail calls, which allows us to avoid clobbering %o7, and therefore we need not save and restore it. Signed-off-by

[PATCH v4 3/5] tcg/sparc: Use the constant pool for 64-bit constants

Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 15 +++ 1 file changed, 15 insertions(+) diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 6349f750cc..47bdf314a0 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -33

[PATCH v4 1/5] tcg/sparc: Add scratch argument to tcg_out_movi_int

This will allow us to control exactly what scratch register is used for loading the constant. Also, fix a theoretical problem in recursing through tcg_out_movi, which may provide a different value for in_prologue. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 20

[PATCH v4 0/5] tcg/sparc: Unaligned access for user-only

Changes from v3: * Rebase on master, two patches merged. r~ Richard Henderson (5): tcg/sparc: Add scratch argument to tcg_out_movi_int tcg/sparc: Improve code gen for shifted 32-bit constants tcg/sparc: Use the constant pool for 64-bit constants tcg/sparc: Add tcg_out_jmpl_const for b

Re: Notes on Generating Python signatures for QMP RPCs

John Snow writes: > On Thu, Feb 3, 2022 at 5:04 AM Markus Armbruster wrote: >> John Snow writes: >> > On Thu, Jan 27, 2022 at 9:03 AM Markus Armbruster >> > wrote: >> >> John Snow writes: > >> >> > (7) I have no idea what to do about functions that "may not return". >> >> > The QGA stuff in

[PATCH v4 2/5] tcg/sparc: Improve code gen for shifted 32-bit constants

We had code for checking for 13 and 21-bit shifted constants, but we can do better and allow 32-bit shifted constants. This is still 2 insns shorter than the full 64-bit sequence. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 12 ++-- 1 file changed, 6 insertions(+),

Re: [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n)

On 2/3/22 21:09, Fabiano Rosas wrote: This series handles the 6xx family: 603, 604, G2, G2LE, What about the e300 ? I guess it's only a 603 variant for QEMU. MPC5xx and MPC8xx. These are linux-user only, no MMU. I wonder if we shouldn't simply drop support. At least we could remove POWERPC

Re: [PATCH v5 2/2] tcg/mips: Support unaligned access for softmmu

On 2/2/22 00:41, Richard Henderson wrote: We can use the routines just added for user-only to emit unaligned accesses in softmmu mode too. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 91 ++- 1 file changed, 51 insertions(+), 40 deletio

Re: [PATCH v5 1/2] tcg/mips: Support unaligned access for user-only

On 2/2/22 00:41, Richard Henderson wrote: This is kinda sorta the opposite of the other tcg hosts, where we get (normal) alignment checks for free with host SIGBUS and need to add code to support unaligned accesses. Fortunately, the ISA contains pairs of instructions that are used to implement u

Re: [PATCH v5 0/2] tcg/mips: Unaligned access support

Cc'ing other reviewers: $ ./scripts/get_maintainer.pl -f tcg/mips/tcg-target.h "Philippe Mathieu-Daudé" (odd fixer:MIPS TCG target) Aurelien Jarno (reviewer:MIPS TCG target) Huacai Chen (reviewer:MIPS TCG target) Jiaxun Yang (reviewer:MIPS TCG target) Aleksandar Rikalo (reviewer:MIPS TCG tar

Re: [PATCH 25/27] meson: require dynamic linking for VSS support

On 3/2/22 18:33, Paolo Bonzini wrote: From: Marc-André Lureau The glib_dynamic detection does not work because the dependency is overridden in the main meson.build. Signed-off-by: Marc-André Lureau [Rewritten commit message, added requirement in qga/meson.build - Paolo] Signed-off-by: Paolo B

Re: [PATCH 24/27] qga/vss-win32: require widl/midl, remove pre-built TLB file

On 3/2/22 18:33, Paolo Bonzini wrote: From: Marc-André Lureau There are no good reason anymore to keep a pre-built file in the repository. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- meson.build | 4 qga/meson.build | 2 ++ qga/vss-w

Re: [PATCH 21/27] qga/vss: use standard windows headers location

On 3/2/22 18:33, Paolo Bonzini wrote: From: Marc-André Lureau Stop using special paths with outdated headers from an old SDK. Instead, use standard include paths. You can still build against the old SDK by running configure with --extra-cxxflags="-isystem `/path/to/inc/win2003/" Superfluous

Re: [PATCH 11/27] meson: define qemu_cflags/qemu_ldflags

On 3/2/22 18:33, Paolo Bonzini wrote: Prepare for moving more compiler tests to Meson. If the full set of compiler flags is needed in a cc.compiles/cc.links test, it will be handy to have a variable analogous to QEMU_CFLAGS. Signed-off-by: Paolo Bonzini --- meson.build | 13 +++-- 1

[PATCH v3] 9pfs: Fix segfault in do_readdir_many caused by struct dirent overread

`struct dirent' returned from readdir(3) could be shorter (or longer) than `sizeof(struct dirent)', thus memcpy of sizeof length will overread into unallocated page causing SIGSEGV. Example stack trace: #0 0x559ebeed v9fs_co_readdir_many (/usr/bin/qemu-system-x86_64 + 0x497eed) #1 0x0

Re: [PATCH 03/27] configure, meson: move AVX tests to meson

On 2/4/22 04:33, Paolo Bonzini wrote: For consistency with other tests, --enable-avx2 and --enable-avx512f fail to compile on x86 systems if cpuid.h is not available. Signed-off-by: Paolo Bonzini --- configure | 103 -- meson.build

Re: [PATCH 01/27] meson: use .allowed() method for features

On 2/4/22 04:33, Paolo Bonzini wrote: The method is now in 0.59, using it simplifies some boolean conditions. The other new methods .require() and .disable_auto_if() can be used too, but introducing them is not just a matter of search-and-replace. Signed-off-by: Paolo Bonzini --- meson.build

[PATCH v9 0/5] support subsets of virtual memory extension

This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0. Specification: https://github.com/riscv/virtual-memory/tree/main/specs The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v9

[PATCH v9 1/5] target/riscv: Ignore reserved bits in PTE for RV64

From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual

[PATCH v9 4/5] target/riscv: add support for svinval extension

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check - do nothing other than extension check for sfence.w.inval and sfence.inval.ir Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alis

[PATCH v9 5/5] target/riscv: add support for svpbmt extension

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Fran

[PATCH v9 3/5] target/riscv: add support for svnapot extension

- add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 2 ++ target/riscv/

[PATCH v9 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

For non-leaf PTEs, the D, A, and U bits are reserved for future standard use. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_helpe

Re: [PATCH] target/riscv: fix inverted checks for ext_zb[abcs]

On Fri, Feb 4, 2022 at 1:42 AM Philipp Tomsich wrote: > > While changing to the use of cfg_ptr, the conditions for REQUIRE_ZB[ABCS] > inadvertently became inverted and slipped through the initial testing (which > used RV64GC_XVentanaCondOps as a target). > This fixes the regression. > > Tested aga

Re: [PATCH v4 4/4] python/aqmp: add socket bind step to legacy.py

On Thu, Feb 3, 2022 at 4:38 AM Daniel P. Berrangé wrote: > > On Wed, Feb 02, 2022 at 02:08:59PM -0500, John Snow wrote: > > On Tue, Feb 1, 2022 at 2:46 PM Kevin Wolf wrote: > > > > > > Am 01.02.2022 um 19:32 hat John Snow geschrieben: > > > > On Tue, Feb 1, 2022 at 8:21 AM Kevin Wolf wrote: > >

Re: [PATCH v2] 9pfs: Fix segfault in do_readdir_many caused by struct dirent overread

On Fri, Feb 04, 2022 at 03:15:16AM +0300, Vitaly Chikunov wrote: [...] > Yes but this will cause another abort() call. I am thinking about v3 fix > like this: > > struct dirent * > qemu_dirent_dup(struct dirent *dent) > { > size_t sz = 0; > #if defined _DIRENT_HAVE_D_RECLEN > /

Re: [PATCH v2] 9pfs: Fix segfault in do_readdir_many caused by struct dirent overread

Christian, On Thu, Feb 03, 2022 at 01:42:19PM +0100, Christian Schoenebeck wrote: > On Freitag, 28. Januar 2022 23:33:26 CET Vitaly Chikunov wrote: > > `struct dirent' returned from readdir(3) could be shorter than > > `sizeof(struct dirent)', thus memcpy of sizeof length will overread > > into un

Re: [PULL 0/4] Python patches

On Thu, Feb 3, 2022 at 11:52 AM Peter Maydell wrote: > > On Thu, 3 Feb 2022 at 16:38, John Snow wrote: > > > On Thu, Feb 3, 2022, 11:20 AM Peter Maydell > > wrote: > >> Summary of Failures: > >> > >> 1/1 qemu:block / qemu-iotests qcow2 ERROR 243.14s exit status 1 I'm not too familia

[PATCH 09/10] target/ppc: 7xx: Software TLB cleanup

This code applies only to the 7xx CPUs, so we can remove the switch statement. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index f29f2

[PATCH 05/10] target/ppc: 7xx: External interrupt cleanup

There is no MSR_HV in the 7xx so remove the LPES0 handling. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 37 - 1 file changed, 37 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 4996b96616..5e2c2aa544 100644

Re: Notes on Generating Python signatures for QMP RPCs

On Thu, Feb 3, 2022 at 5:40 AM Daniel P. Berrangé wrote: > > On Wed, Jan 26, 2022 at 01:58:19PM -0500, John Snow wrote: > > (1) QAPI types the return of many commands as an empty object. That's > > literally indeed what happens on the wire, and it makes sense in that > > if these commands were eve

[PATCH 04/10] target/ppc: 7xx: Machine Check exception cleanup

There's no MSR_HV in the 7xx. Also remove 40x and BookE code. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 24 1 file changed, 24 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 358c3f6206..4996b96616 100644 --- a/targ

[PATCH 10/10] target/ppc: 7xx: Set SRRs directly in exception code

The 7xx CPUs don't have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 13 ++--- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_h

[PATCH 08/10] target/ppc: 7xx: System Reset cleanup

Thre is no HV support in the 7xx. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 18 ++ 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 0bb577b75d..f29f2ecefb 100644 --- a/target/ppc/excp_helper

[PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx

Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP

[PATCH 02/10] target/ppc: Introduce powerpc_excp_7xx

Introduce a new powerpc_excp function specific for PowerPC 7xx CPUs (740, 745, 750, 750cl, 750cx, 750fx, 750gx, 755). This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 469

[PATCH 07/10] target/ppc: 7xx: System Call exception cleanup

There is no Hypervisor mode in the 7xx, so no hypercalls. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 21 ++--- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 8f810f7de5..0bb577b75d 100644 -

[PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n)

This series handles the 7xx family: 740, 745, 750, 750cl, 750cx, 750fx, 750gx and 755. Fabiano Rosas (10): target/ppc: Merge 7x5 and 7x0 exception model IDs target/ppc: Introduce powerpc_excp_7xx target/ppc: Simplify powerpc_excp_7xx target/ppc: 7xx: Machine Check exception cleanup targe

[PATCH 06/10] target/ppc: 7xx: Program exception cleanup

There's no ESR in the 7xx. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 4 1 file changed, 4 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 5e2c2aa544..8f810f7de5 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -84

[PATCH 01/10] target/ppc: Merge 7x5 and 7x0 exception model IDs

Since we've split the exception code by exception model, the exception model IDs are becoming less useful. These two can be merged. Signed-off-by: Fabiano Rosas --- target/ppc/cpu-qom.h | 6 ++ target/ppc/cpu_init.c| 16 target/ppc/excp_helper.c | 2 +- 3 files cha

[PULL 1/2] tpm: CRB: Use ram_device for "tpm-crb-cmd" region

From: Eric Auger Representing the CRB cmd/response buffer as a standard RAM region causes some trouble when the device is used with VFIO. Indeed VFIO attempts to DMA_MAP this region as usual RAM but this latter does not have a valid page size alignment causing such an error report: "vfio_listener

[PULL 2/2] hw/vfio/common: Silence ram device offset alignment error traces

From: Eric Auger Failing to DMA MAP a ram_device should not cause an error message. This is currently happening with the TPM CRB command region and this is causing confusion. We may want to keep the trace for debug purpose though. Signed-off-by: Eric Auger Tested-by: Stefan Berger Acked-by: A

[PULL 0/2] VFIO fixes 2022-02-03

The following changes since commit 8f3e5ce773c62bb5c4a847f3a9a5c98bbb3b359f: Merge remote-tracking branch 'remotes/hdeller/tags/hppa-updates-pull-request' into staging (2022-02-02 19:54:30 +) are available in the Git repository at: git://github.com/awilliam/qemu-vfio.git tags/vfio-fixes

Re: [PATCH 19/20] tcg/i386: Implement more logical operations for avx512

On 2/3/22 21:46, Alex Bennée wrote: Richard Henderson writes: The general ternary logic operation can implement NOT, ORC, NAND, NOR, EQV. Can we not fall back to expanding to use SSE if we don't have AVX512 available or is that done by the exiting fallback expansion? Generic code does tha

Re: [PATCH 06/13] hw/intc/arm_gicv3_its: Fix address calculation in get_ite() and update_ite()

On 2/3/22 21:45, Peter Maydell wrote: On Thu, 3 Feb 2022 at 03:59, Richard Henderson wrote: On 2/2/22 06:32, Peter Maydell wrote: In get_ite() and update_ite() we work with a 12-byte in-guest-memory table entry, which we intend to handle as an 8-byte value followed by a 4-byte value. Unfortu

RE: [RFC v4 08/21] vfio-user: define socket receive functions

> -Original Message- > From: Qemu-devel bounces+thanos.makatos=nutanix@nongnu.org> On Behalf Of John > Johnson > Sent: 12 January 2022 00:44 > To: qemu-devel@nongnu.org > Subject: [RFC v4 08/21] vfio-user: define socket receive functions > > Add infrastructure needed to receive inco

Re: Notes on Generating Python signatures for QMP RPCs

On Thu, Feb 3, 2022 at 5:04 AM Markus Armbruster wrote: > John Snow writes: > > On Thu, Jan 27, 2022 at 9:03 AM Markus Armbruster wrote: > >> John Snow writes: > >> > (7) I have no idea what to do about functions that "may not return". > >> > The QGA stuff in particular, I believe, is prone to

Re: [PATCH v2 0/3] hw/nvme: zoned random write area

On Jan 27 09:19, Klaus Jensen wrote: > From: Klaus Jensen > > This series adds support for a zoned random write area as standardized > in TP 4076 ("Zoned Random Write Area"). > > v2: > * fixed rsvd member in NvmeZoneSendCmd (Keith) > * dropped patch 2 ("hw/nvme: add zone attribute get/set he

RE: [RFC PATCH 0/4] improve coverage of vector backend

> -Original Message- > From: Alex Bennée > Sent: Thursday, February 3, 2022 2:00 PM > To: Taylor Simpson > Cc: richard.hender...@linaro.org; qemu-devel@nongnu.org; qemu- > a...@nongnu.org; f...@euphon.net; berra...@redhat.com; > f4...@amsat.org; aurel...@aurel32.net; pbonz...@redhat.com

Re: [PATCH v2 6/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control

Hi Edgar, On 15:01 Thu 03 Feb , Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Connect the ZynqMP APU Control device. Somehow you don't seem to connect the "wfi_in" pins. I guess it's because currently QEMU ARM CPUs do not expose a "wfi_out" pin right? Reviewed-by: Luc Michel >

Re: [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control

On 00:12 Mon 31 Jan , Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Connect the ZynqMP APU Control device. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Luc Michel > --- > include/hw/arm/xlnx-zynqmp.h | 4 +++- > hw/arm/xlnx-zynqmp.c | 25 +++-

Re: [RFC PATCH 0/4] improve coverage of vector backend

On 2/4/22 07:00, Alex Bennée wrote: Does: #if BYTE_ORDER == BIG_ENDIAN work for your compiler? No, but this does #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ With that change in the source, the tests passes. Will that work for other targets? At least not hppa-linux-user. The joy of havin

Re: [PATCH v1 2/6] target/arm: Make rvbar settable after realize

Hi Edgar, On 00:12 Mon 31 Jan , Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Make the rvbar property settable after realize. This is done > in preparation to model the ZynqMP's runtime configurable rvbar. > > Signed-off-by: Edgar E. Iglesias > --- > target/arm/cpu.c | 7 +++---

Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support

On Thu, Feb 3, 2022 at 4:23 AM Heiko Stübner wrote: > Hi Atish, > > Am Donnerstag, 20. Januar 2022, 21:07:34 CET schrieb Atish Patra: > > The RISC-V privileged specification v1.12 defines few execution > > environment configuration CSRs that can be used enable/disable > > extensions per privilege

[PATCH 09/11] target/ppc: 6xx: System Reset interrupt cleanup

There is no HV support in the 6xx. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 18 ++ 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 28d9a9a887..538905c4dd 100644 --- a/target/ppc/excp_helpe

Re: [PATCH v2 2/6] target/arm: Make rvbar settable after realize

Hi Edgar, Oops I mistakenly answered on v1 :) On 15:01 Thu 03 Feb , Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Make the rvbar property settable after realize. This is done > in preparation to model the ZynqMP's runtime configurable rvbar. > > Signed-off-by: Edgar E. Iglesias

[PATCH 08/11] target/ppc: 6xx: System Call exception cleanup

There is no Hypervisor mode in the 6xx CPUs. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 21 ++--- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a195288dda..28d9a9a887 100644 --- a/target/p

[PATCH 01/11] target/ppc: Merge exception model IDs for 6xx CPUs

We don't need three separate exception model IDs for the 603, 604 and G2. Signed-off-by: Fabiano Rosas --- target/ppc/cpu-qom.h | 8 ++-- target/ppc/cpu_init.c| 18 +- target/ppc/excp_helper.c | 5 ++--- 3 files changed, 13 insertions(+), 18 deletions(-) diff --git

Re: [PATCH v1] hw/arm/xlnx-zynqmp: 'Or' the QSPI / QSPI DMA IRQs

On 15:17 Thu 03 Feb , Francisco Iglesias wrote: > 'Or' the IRQs coming from the QSPI and QSPI DMA models. This is done for > avoiding the situation where one of the models incorrectly deasserts an > interrupt asserted from the other model (which will result in that the IRQ > is lost and will no

[PATCH 02/11] target/ppc: Introduce powerpc_excp_6xx

Introduce a new powerpc_excp function specific for PowerPC 6xx CPUs (603, 604, G2, MPC5xx, MCP8xx). This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 469 +++ 1 file ch

Re: [PATCH v2 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control

On 15:01 Thu 03 Feb , Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Add a model of the Xilinx ZynqMP APU Control. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Luc Michel > --- > include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 95 + > hw/misc/xlnx-zynqmp-apu-ctrl.c

Re: [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF

On 00:12 Mon 31 Jan , Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Connect the ZynqMP CRF - Clock Reset FPD device. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Luc Michel > --- > include/hw/arm/xlnx-zynqmp.h | 2 ++ > hw/arm/xlnx-zynqmp.c | 16

[PATCH 04/11] target/ppc: 6xx: Critical exception cleanup

This only applies to the G2s, the other 6xx CPUs will not have this vector registered. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 15 --- 1 file changed, 15 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index d855a275ca..e27e1c3c70 10

Re: [PATCH v5 5/9] virtiofsd, fuse_lowlevel.c: Add capability to parse security context

* Vivek Goyal (vgo...@redhat.com) wrote: > Add capability to enable and parse security context as sent by client > and put into fuse_req. Filesystems now can get security context from > request and set it on files during creation. > > Signed-off-by: Vivek Goyal > --- > tools/virtiofsd/fuse_commo

[PATCH 01/10] hw/tpm: Clean includes

"tpm_ppi.h" only requires to include "exec/memory.h" to get the MemoryRegion declaration. tpm_ppi.c requires "hw/qdev-core.h" to use the DEVICE() macro, tpm_crb.c is the only source file requiring "exec/address-spaces.h". Signed-off-by: Philippe Mathieu-Daudé --- hw/tpm/tpm_crb.c | 1 + hw/tpm/

[PATCH 10/11] target/ppc: 6xx: Software TLB exceptions cleanup

This code applies only to the 6xx CPUs, so we can remove the switch statement. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 31 +++ 1 file changed, 11 insertions(+), 20 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index

[PATCH 11/11] target/ppc: 6xx: Set SRRs directly in exception code

The 6xx CPUs don't have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 13 ++--- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_h

[PATCH 00/10] exec: Remove 'qemu/log.h' from 'exec-all.h'

Yet another noisy/boring refactor, but it will allow us to better split exec/ includes as being target-agnostic/specific (the next series). Based-on: <20220203191814.45023-1-f4...@amsat.org> "softmmu: Make various objects target agnostic" Philippe Mathieu-Daudé (10): hw/tpm: Clean includes hw

[PATCH 10/10] exec/exec-all: Move 'qemu/log.h' include in units requiring it

Many files use "qemu/log.h" declarations but neglect to include it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is a core component and shouldn't be used that way. Move the "qemu/log.h" inclusion locally to each unit requiring it. Signed-off-by: Philippe Mathieu-Daudé --- bsd-user/

[PATCH 06/11] target/ppc: 6xx: External interrupt cleanup

There's no Hypervisor mode in the 6xx, so remove all LPES0 logic. Also remove BookE IRQ code. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 37 - 1 file changed, 37 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c i

[PATCH 07/11] target/ppc: 6xx: Program exception cleanup

There's no ESR in the 6xx CPUs. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 4 1 file changed, 4 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a008115e5f..a195288dda 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @

[PATCH 09/10] linux-user: Add missing "qemu/timer.h" include

"qemu/timer.h" declares cpu_get_host_ticks(). Signed-off-by: Philippe Mathieu-Daudé --- linux-user/i386/cpu_loop.c | 1 + linux-user/ppc/cpu_loop.c | 1 + 2 files changed, 2 insertions(+) diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 29dfd7cd0c..90bffc1956 100644 -

[PATCH 03/11] target/ppc: Simplify powerpc_excp_6xx

Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP

[PATCH 08/10] target: Add missing "qemu/timer.h" include

cpu_get_host_ticks() and NANOSECONDS_PER_SECOND are declared in "qemu/timer.h". Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 1 + target/arm/helper.c | 1 + target/hppa/cpu.c | 1 + target/riscv/csr.c| 1 + target/sparc/helper.c | 1 + 5 files changed, 5 insertions

[PATCH v2 13/21] softmmu/runstate: Clean headers

Add the missing 'qemu/log.h' header and remove the unused 'exec/exec-all.h' one. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- softmmu/runstate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/softmmu/runstate.c b/softmmu/runstate.c index 10d9b736

Re: [RFC PATCH 0/4] improve coverage of vector backend

Taylor Simpson writes: >> -Original Message- >> From: Alex Bennée >> Sent: Thursday, February 3, 2022 12:26 PM >> To: Taylor Simpson >> Cc: richard.hender...@linaro.org; qemu-devel@nongnu.org; qemu- >> a...@nongnu.org; f...@euphon.net; berra...@redhat.com; >> f4...@amsat.org; aurel...

[PATCH 05/11] target/ppc: 6xx: Machine Check exception cleanup

There's no MSR_HV in the 6xx CPUs. Also remove the 40x and BookE code. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 24 1 file changed, 24 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e27e1c3c70..734170d4c2 100644 -

[PATCH 06/10] exec/ramblock: Add missing includes

Add missing includes to avoid when refactoring include/ include/exec/ramblock.h:26:21: error: field has incomplete type 'struct rcu_head' struct rcu_head rcu; ^ Signed-off-by: Philippe Mathieu-Daudé --- include/exec/ramblock.h | 2 ++ 1 file changed, 2 insertions(+)

[PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n)

This series handles the 6xx family: 603, 604, G2, G2LE, MPC5xx and MPC8xx. There is a patch upfront to move them all into the same POWERPC_EXCP_6xx, but otherwise the rest of the series is pretty much the same as I have done for the other CPUs. This was tested with the 604 only. But I'm not too w

[PATCH v2 11/21] accel: Introduce AccelOpsClass::cpus_are_resettable()

Add cpus_are_resettable() to AccelOps, and implement it for the KVM accelerator. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- accel/kvm/kvm-accel-ops.c | 6 ++ include/sysemu/accel-ops.h | 2 ++ include/sysemu/hw_accel.h | 5 - softmmu/cpus.c |

[PATCH 07/10] core/ptimers: Remove unnecessary 'sysemu/cpus.h' include

Signed-off-by: Philippe Mathieu-Daudé --- hw/core/ptimer.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index 6ba19fd965..eb5ba1aff7 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -14,7 +14,6 @@ #include "sysemu/cpu-timers.h" #include "sysemu/q

[PATCH v2 10/21] accel: Introduce AccelOpsClass::cpu_thread_is_idle()

Add cpu_thread_is_idle() to AccelOps, and implement it for the KVM / WHPX accelerators. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- accel/kvm/kvm-accel-ops.c | 6 ++ include/sysemu/accel-ops.h| 1 + softmmu/cpus.c| 6 --

[PATCH 04/10] hw/acpi/memory_hotplug: Remove unused 'hw/acpi/pc-hotplug.h' header

Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/acpi/memory_hotplug.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/acpi/memory_hotplug.c b/hw/acpi/memory_hotplug.c index a581a2183b..0a7e89a13e 100644 --- a/hw/acpi/memory_hotplug.c +++ b/hw/acpi/memory_hotplug

[PATCH 05/10] qtest: Add missing 'hw/qdev-core.h' include

Add "hw/qdev-core.h" to avoid when refactoring include/: softmmu/qtest.c:404:9: error: use of undeclared identifier 'NamedGPIOList' NamedGPIOList *ngl; ^ Signed-off-by: Philippe Mathieu-Daudé --- softmmu/qtest.c | 1 + 1 file changed, 1 insertion(+) diff --git a/softmmu/qtest

[PATCH 02/10] hw/remote: Add missing include

Currently "qemu/error-report.h" is implicitly included, however if headers in include/ get refactored, we get: hw/remote/proxy-memory-listener.c: In function ‘proxy_memory_listener_commit’: hw/remote/proxy-memory-listener.c:183:9: error: implicit declaration of function ‘error_report’; did yo

[PATCH v2 05/21] sysemu/memory_mapping: Become target-agnostic

target_ulong is target-specific, while vaddr isn't. Remove the unnecessary "exec/cpu-defs.h" target-speficic header from "memory_mapping.h" and use the target-agnostic "hw/core/cpu.h" locally in memory_mapping.c. Remove "exec/memory.h" since MemoryRegion is forward-declared in "qemu/typedefs.h".

[PATCH 03/10] hw/s390x/virtio: Add missing 'cpu.h' include

CPUS390XState is declared in "cpu.h". Signed-off-by: Philippe Mathieu-Daudé --- hw/s390x/s390-virtio-hcall.h | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/s390x/s390-virtio-hcall.h b/hw/s390x/s390-virtio-hcall.h index 9800c4b351..9773ed8a21 100644 --- a/hw/s390x/s390-virtio-hcall.h +++

[PATCH v2 04/21] exec: Make cpu_memory_rw_debug() target agnostic

cpu_memory_rw_debug() is declared in "exec/cpu-all.h" which contains target-specific declarations. To be able to use it from target agnostic source, move the declaration to the generic "exec/cpu-common.h" header. Replace the target-specific 'target_ulong' type by 'vaddr' which better reflects the

[PATCH v2 21/21] softmmu: Build target-agnostic objects once

Various softmmu objects aren't target specific. Move them to the generic softmmu source set. For our 31 softmmu targets, this is in total 330 objects less to build! Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- softmmu/meson.build | 24 1 fil

[PATCH v2 15/21] softmmu/cpu-timers: Remove unused 'exec/exec-all.h' header

Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- softmmu/cpu-timers.c | 1 - 1 file changed, 1 deletion(-) diff --git a/softmmu/cpu-timers.c b/softmmu/cpu-timers.c index 34ddfa02f1..204d946a17 100644 --- a/softmmu/cpu-timers.c +++ b/softmmu/cpu-timers.c @@ -28,7 +28,6 @@

[PATCH v2 03/21] exec: Declare vaddr as a generic target-agnostic type

Move vaddr type declaration to the generic "exec/cpu-common.h" header. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-common.h | 12 include/hw/core/cpu.h | 13 + 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/include/exec/cpu-common.h b

[PATCH v2 20/21] softmmu: Add qemu_init_arch_modules()

module_allow_arch() is the single target-specific call in the whole vl.c file. Move the module initialization out to arch_init.c, that way we'll be able to build vl.o once for all targets (the next commit). Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/arch_init.h | 2 ++ softmmu/arch

[PATCH v2 18/21] exec/gdbstub: Make gdb_exit() / gdb_set_stop_cpu() target agnostic

gdb_exit() and gdb_set_stop_cpu() prototypes don't have to be target specific. Remove this limitation to be able to build softmmu/cpus.c and softmmu/runstate.c once for all targets. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/exec/gdbstub.h | 23

[PATCH v2 01/21] accel: Restrict sysemu stubs to system emulation

Signed-off-by: Philippe Mathieu-Daudé --- accel/stubs/meson.build | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/accel/stubs/meson.build b/accel/stubs/meson.build index 12dd1539af..0249b9258f 100644 --- a/accel/stubs/meson.build +++ b/accel/stubs/meson.build @@ -1

[PATCH v2 14/21] softmmu/physmem: Remove unnecessary include

Signed-off-by: Philippe Mathieu-Daudé --- softmmu/physmem.c | 1 - 1 file changed, 1 deletion(-) diff --git a/softmmu/physmem.c b/softmmu/physmem.c index eb4b3bcae7..09951c0996 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -60,7 +60,6 @@ #include "exec/memory-internal.h" #include

[PATCH v2 19/21] exec/cpu: Make address_space_init/reloading_memory_map target agnostic

cpu_address_space_init() and cpu_reloading_memory_map() are target-agnostic, but are declared in "exec/exec-all.h" which contains target-specific declarations. Any target-agnostic source including "exec/exec-all.h" becomes target-specific and we have to compile it N times for the N targets built.

[PATCH v2 12/21] softmmu/globals: Remove unused 'hw/i386/*' headers

Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- softmmu/globals.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/softmmu/globals.c b/softmmu/globals.c index 7d0fc81183..3ebd718e35 100644 --- a/softmmu/globals.c +++ b/softmmu/globals.c @@ -25,8 +25,6 @@ #include "q

[PATCH v2 17/21] misc: Add missing "sysemu/cpu-timers.h" include

Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-accel-ops-icount.c | 1 + accel/tcg/tcg-accel-ops-mttcg.c | 1 + accel/tcg/tcg-accel-ops-rr.c | 1 + accel/tcg/tcg-accel-ops.c| 1 + include/exec/exec-all.h | 1 - target/riscv/csr.c | 1 + 6 files changed

[PATCH v2 09/21] softmmu/cpus: Code movement

We want cpu_thread_is_idle() to use cpus_accel, so declare this variable earlier. Signed-off-by: Philippe Mathieu-Daudé --- softmmu/cpus.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 7f15106dd9..538e1714af 100644 --- a/soft

  1   2   3   >