Anup Patel 於 2021年12月30日 週四 下午8:48寫道：
> From: Anup Patel
>
> The guest external interrupts from an interrupt controller are
> delivered only when the Guest/VM is running (i.e. V=1). This means
> any guest external interrupt which is triggered while the Guest/VM
> is not running (i.e. V=0) will b
Anup Patel 於 2021年12月30日 週四 下午9:00寫道：
> From: Anup Patel
>
> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> interrupt controller for MSIs (message signal interrupts) called
> IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
> is per-HART device and also suppport
On 11/01/2022 04.27, Yanan Wang wrote:
The pointer assignment "const char *p = path;" in function
qemu_fdt_add_path is unnecessary. Let's remove it and just
use the "path" passed in. No functional change.
Suggested-by: Richard Henderson
Signed-off-by: Yanan Wang
---
Based on: softmmu/device_tr
On 10/01/2022 14.10, Philippe Mathieu-Daudé wrote:
Add support for macOS 12 build on Cirrus-CI, similarly to commit
0e103a65ba1 ("gitlab: support for ... macOS 11 via cirrus-run").
Update the lcitool repository to get the macos12 mappings,
and generate the vars file by calling 'make lcitool-refr
Hi Daniel,
On Wed, Jan 12, 2022 at 10:11:35AM +, Daniel P. Berrangé wrote:
> On Wed, Jan 12, 2022 at 11:55:17AM -0500, Yang Zhong wrote:
> > When Libvirt start, it get the vcpu's unavailable-features from
> > /machine/unattached/device[0] path by qom-get command, but in SGX
> > guest, since th
On 10/01/2022 10.35, Philippe Mathieu-Daudé wrote:
Hi Patrick,
On 1/8/22 04:04, Patrick Venture wrote:
From: Hao Wu
SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
interface that reports AMD SoC's Ttcl (normalized temperature),
and resembles a typical 8-pin remote temperature
On Thu, Jan 13, 2022 at 01:06:09PM +0800, Peter Xu wrote:
> On Wed, Jan 05, 2022 at 12:19:45PM +0800, Jason Wang wrote:
> > @@ -1725,11 +1780,16 @@ static bool vtd_do_iommu_translate(VTDAddressSpace
> > *vtd_as, PCIBus *bus,
> > cc_entry->context_cache_gen = s->context_cache_gen;
> >
On Thu, Jan 06, 2022 at 07:13:42PM -0300, Leonardo Bras wrote:
> Implement zero copy on nocomp_send_write(), by making use of QIOChannel
> writev + flags & flush interface.
>
> Change multifd_send_sync_main() so it can distinguish each iteration sync from
> the setup and the completion, so a flush
On Thu, Jan 06, 2022 at 07:13:41PM -0300, Leonardo Bras wrote:
> void migration_channel_process_incoming(QIOChannel *ioc)
> {
> -MigrationState *s = migrate_get_current();
> Error *local_err = NULL;
>
> trace_migration_set_incoming_channel(
> ioc, object_get_typename(OBJE
On Thu, Jan 13, 2022 at 11:35:19AM +0800, Peter Xu wrote:
> On Wed, Jan 05, 2022 at 12:19:43PM +0800, Jason Wang wrote:
> > We use to warn on wrong rid2pasid entry. But this error could be
> > triggered by the guest and could happens during initialization. So
> > let's don't warn in this case.
> >
On Wed, Jan 05, 2022 at 12:19:43PM +0800, Jason Wang wrote:
> We use to warn on wrong rid2pasid entry. But this error could be
> triggered by the guest and could happens during initialization. So
> let's don't warn in this case.
>
> Signed-off-by: Jason Wang
> ---
> hw/i386/intel_iommu.c | 6 +++
On Thu, Jan 06, 2022 at 07:13:40PM -0300, Leonardo Bras wrote:
> Add property that allows zero-copy migration of memory pages,
> and also includes a helper function migrate_use_zero_copy() to check
> if it's enabled.
>
> No code is introduced to actually do the migration, but it allow
> future imp
On Thu, Jan 06, 2022 at 07:13:39PM -0300, Leonardo Bras wrote:
> @@ -558,15 +575,26 @@ static ssize_t qio_channel_socket_writev(QIOChannel
> *ioc,
> memcpy(CMSG_DATA(cmsg), fds, fdsize);
> }
>
> +if (flags & QIO_CHANNEL_WRITE_FLAG_ZERO_COPY) {
> +sflags = MSG_ZEROCOPY;
On 07/01/2022 12.47, Paolo Bonzini wrote:
If roms/seabios/Makefile is not present, the configure script
is not creating the roms/seabios directory anymore (commit
5dce7b8d8c, "configure: remove DIRS", 2021-12-18); thus, creating
roms/seabios/config.mak fails.
The easiest thing to do is to not cr
On 07/01/2022 19.54, Philippe Mathieu-Daudé wrote:
On 1/7/22 17:07, Thomas Huth wrote:
We already have a CONFIG_ISAPC switch - but we're not using it yet.
Add some "#ifdefs" to make it possible to disable this machine now.
Signed-off-by: Thomas Huth
---
hw/i386/pc_piix.c| 5 -
t
On Thu, Jan 13, 2022 at 02:16:35PM +0800, Jason Wang wrote:
> On Thu, Jan 13, 2022 at 11:35 AM Peter Xu wrote:
> >
> > On Wed, Jan 05, 2022 at 12:19:43PM +0800, Jason Wang wrote:
> > > We use to warn on wrong rid2pasid entry. But this error could be
> > > triggered by the guest and could happens d
On Thu, Jan 06, 2022 at 07:13:38PM -0300, Leonardo Bras wrote:
> diff --git a/io/channel.c b/io/channel.c
> index e8b019dc36..904855e16e 100644
> --- a/io/channel.c
> +++ b/io/channel.c
> @@ -67,12 +67,13 @@ ssize_t qio_channel_readv_full(QIOChannel *ioc,
> }
>
>
> -ssize_t qio_channel_writev_
On Thu, Jan 13, 2022 at 11:35 AM Peter Xu wrote:
>
> On Wed, Jan 05, 2022 at 12:19:43PM +0800, Jason Wang wrote:
> > We use to warn on wrong rid2pasid entry. But this error could be
> > triggered by the guest and could happens during initialization. So
> > let's don't warn in this case.
> >
> > Si
On Thu, Jan 13, 2022 at 1:42 AM Philipp Tomsich
wrote:
>
> Alistair,
>
> Do you (and the other RISC-V custodians of target/riscv) have any opinion on
> this?
> We can go either way — and it boils down to a style and process question.
Sorry, it's a busy week!
I had a quick look over this series
On Wed, Jan 05, 2022 at 12:19:45PM +0800, Jason Wang wrote:
> @@ -1725,11 +1780,16 @@ static bool vtd_do_iommu_translate(VTDAddressSpace
> *vtd_as, PCIBus *bus,
> cc_entry->context_cache_gen = s->context_cache_gen;
> }
>
> +/* Try to fetch slpte form IOTLB */
> +if ((pasid
On Wed, Jan 12, 2022 at 1:44 PM Yifei Jiang wrote:
>
> Add riscv kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> meson.build | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git
On Wed, Jan 12, 2022 at 1:43 PM Yifei Jiang wrote:
>
> Get kernel and fdt start address in virt.c, and pass them to KVM
> when cpu reset. Add kvm_riscv.h to place riscv specific interface.
>
> In addition, PLIC is created without M-mode PLIC contexts when KVM
> is enabled.
>
> Signed-off-by: Yifei
On Wed, Jan 12, 2022 at 6:25 PM Yifei Jiang via wrote:
>
> Add riscv kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
Reviewed-by: Alistair Francis
Alistair
> ---
> meson.build | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/meson.build
On Tue, Jan 11, 2022 at 1:28 PM Yanan Wang via wrote:
>
> The pointer assignment "const char *p = path;" in function
> qemu_fdt_add_path is unnecessary. Let's remove it and just
> use the "path" passed in. No functional change.
>
> Suggested-by: Richard Henderson
> Signed-off-by: Yanan Wang
Rev
On Wed, Jan 05, 2022 at 12:19:44PM +0800, Jason Wang wrote:
> We introduce VTDBus structure as an intermediate step for searching
> the address space. This works well with SID based matching/lookup. But
> when we want to support SID plus PASID based address space lookup,
> this intermediate steps t
On Wed, Jan 05, 2022 at 12:19:43PM +0800, Jason Wang wrote:
> We use to warn on wrong rid2pasid entry. But this error could be
> triggered by the guest and could happens during initialization. So
> let's don't warn in this case.
>
> Signed-off-by: Jason Wang
> ---
> hw/i386/intel_iommu.c | 6 +++
Hi,
I've just exercised the SVE emulation in QEMU with
| `qemu-system-aarch64 -M virt,virtualization=on,gic-version=3 \
| -cpu max -accel tcg [...]`
Since QEMU sets ID_AA64MMFR1_EL1.VH for -cpu max, the Linux guest I use
was booting with VHE enabled and running with E2H+TGE. But I've then
seen
Granted that this patch might not fit for main branch, I hope this snippet
could help someone in need.
Screen cast feature shipped with macOS does support screen recording, but only
for whole screen or selected rectangle, not for a selected window like photo
capture feature.
And pixels are not
- update extension check REQUIRE_ZHINX_OR_ZFH and
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN
- update half float point register read/write
- disable nanbox_h check
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/fpu_helper.c
-- update extension check REQUIRE_ZDINX_OR_D
-- update double float point register read/write
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvd.c.inc | 285 +---
target/risc
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fc3ec5bca1..d5e772b2b8 100644
--- a/target/riscv/cpu.c
+++ b
This patchset implements RISC-V Float-Point in Integer Registers
extensions(Version 1.0), which includes Zfinx, Zdinx, Zhinx and Zhinxmin
extension.
Specification:
https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0.pdf
The port is available here:
https://github.com/plctlab/plct-qemu/tr
- update extension check REQUIRE_ZFINX_OR_F
- update single float point register read/write
- disable nanbox_s check
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/fpu_helper.c | 89 +++
tar
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 12
target/riscv/cpu.h | 4
target/riscv/translate.c | 8
3 files changed, 24 insertions(+)
diff --git a/target/riscv/c
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_helper.c | 6 +-
target/riscv/csr.c| 25 -
target/riscv/translate.c | 4
3 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu
On Wed, Jan 12, 2022 at 10:56:07AM +, Peter Maydell wrote:
> We could have vmstate_register_with_alias_id() iterate through
> and assert presence of the right terminator (probably only if
> qtest enabled, or some other suitable condition). Then the
> existing tests that do the basic "check we c
Before this patch, 'dump-guest-memory -w' was accepting only 64-bit
dump header provided by guest through vmcoreinfo and thus was unable
to produce 32-bit guest Windows dump. So, add 32-bit guest Windows
dumping support.
Signed-off-by: Viktor Prutyanov
---
dump/win_dump.c | 231 +
These structures are required to produce 32-bit guest Windows Complete
Memory Dump. Add 32-bit Windows dump header, CPU context and physical
memory descriptor structures along with corresponding definitions.
Signed-off-by: Viktor Prutyanov
---
include/qemu/win_dump_defs.h | 107 +
Context structure in 64-bit Windows differs from 32-bit one and it
should be reflected in its name.
Signed-off-by: Viktor Prutyanov
---
contrib/elf2dmp/main.c | 6 +++---
dump/win_dump.c | 14 +++---
include/qemu/win_dump_defs.h | 8
3 files changed, 14 inse
Perform read access to Windows dump header fields via helper macros.
This is preparation for the next 32-bit guest Windows dump support.
Signed-off-by: Viktor Prutyanov
---
dump/win_dump.c | 100 +++-
1 file changed, 65 insertions(+), 35 deletions(-)
Since 32-bit versions of Windows still exist, there is a need to take
live and crash dumps of such guests along with 64-bit guests. So, add
an ability for 'dump-guest-memory -w' to take dumps from 32-bit guest.
When running the command QEMU consumes 32-bit Complete Memory Dump
header passed by gues
From: Hao Wu
SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
interface that reports AMD SoC's Ttcl (normalized temperature),
and resembles a typical 8-pin remote temperature sensor's I2C interface
to BMC.
This patch implements a basic AMD SB-TSI sensor that is
compatible with the
v2:
* Split the commit into a separate patch for the qtest
* Moved the common registers into the new header
* Introduced a new header
Hao Wu (2):
hw/sensor: Add SB-TSI Temperature Sensor Interface
tests: add qtest for hw/sensor/sbtsi
hw/sensor/Kconfig| 4 +
hw/sensor/meson.b
From: Hao Wu
Reviewed-by: Doug Evanwqs
Signed-off-by: Hao Wu
Signed-off-by: Patrick Venture
---
tests/qtest/meson.build | 1 +
tests/qtest/tmp_sbtsi-test.c | 161 +++
2 files changed, 162 insertions(+)
create mode 100644 tests/qtest/tmp_sbtsi-test.c
di
On Wed, 12 Jan 2022 17:40:44 +0100
Eric Farman wrote:
> After the recent restructuring, I'd like to volunteer to help
> in some of the s390 I/O areas.
>
> Built on "[PATCH RFC v2] MAINTAINERS: split out s390x sections"
>
> Signed-off-by: Eric Farman
Acked-by: Halil Pasic
Thanks!
> ---
> M
Now that piix4_set_irq's opaque parameter references own PIIX4State,
piix4_dev becomes redundant and pci_irq_levels can be moved into PIIX4State.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c| 22 +-
include/hw/southbridge/piix.h | 2 --
2 files changed,
Passing own DeviceState rather than just the IRQs allows for resolving
global variables.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 6 +++---
hw/pci-host/sh_pci.c| 6 +++---
hw/pci-host/versatile.c | 6 +++---
hw/ppc/ppc440_pcix.c| 6 +++---
hw/ppc/ppc4xx_pci.c | 6
Handling PCI interrupts in piix4 increases cohesion and reduces differences
between piix4 and piix3.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 58 +++
hw/mips/gt64xxx_pci.c | 62 --
hw/mips/malta.c
Hi,
first-time contributor here. Inspired by an article in LWN [1] I figured I'd
get my hands dirty with QEMU development. According to the article my goal is
to eliminate some "accidental complexity".
While studying the code I noticed some (accidental?) differences between piix3
and piix4 where
+Sven
On 12/1/22 22:07, Helge Deller wrote:
This patch fixes two problems which prevented Linux to access the
artist graphics framebuffer:
The check if the framebuffer or the color map should be accessed was
incomplete. By using the vram_read/write_bufidx() functions we now check
correctly if A
On Thu, Dec 16, 2021 at 5:41 AM Daniel P. Berrangé wrote:
>
> On Wed, Dec 15, 2021 at 04:06:10PM -0500, John Snow wrote:
> > (2) To ask for permission to become the maintainer of a
> > 'qemu-project/qemu.qmp' repository, where I would like to host this
> > subproject.
>
> I'd say we need 3 design
> Am 12.01.2022 um 22:06 schrieb Ilya Dryomov :
>
> On Wed, Jan 12, 2022 at 9:39 PM Peter Lieven wrote:
>>
>>> Am 12.01.22 um 10:05 schrieb Ilya Dryomov:
>>> On Mon, Jan 10, 2022 at 12:42 PM Peter Lieven wrote:
the assumption that we can't hit a hole if we do not diff against a
sn
On Wed, 12 Jan 2022 at 11:27, Alex Bennée wrote:
>
> The following changes since commit bf99e0ec9a51976868d7a8334620716df15fe7fe:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
> (2022-01-11 10:12:29 +)
>
> are available in the Git repository at:
>
> https:/
This patch fix the behaviour and positioning of the X11 mouse cursor in HP-UX.
The current code missed to subtract the offset of the CURSOR_CTRL register from
the current mouse cursor position. The HP-UX graphics driver stores in this
register the offset of the mouse graphics compared to the curre
This patch fixes two problems which prevented Linux to access the
artist graphics framebuffer:
The check if the framebuffer or the color map should be accessed was
incomplete. By using the vram_read/write_bufidx() functions we now check
correctly if ARTIST_BUFFER_CMAP should be accessed.
The seco
This brings the hppa_hardware.h file in sync with the copy in the
SeaBIOS-hppa sources.
In order to support up to 16 CPUs, it's required to move the HPA for
MEMORY_HPA out of the address space of the 16th CPU.
Signed-off-by: Helge Deller
---
hw/hppa/hppa_hardware.h | 5 +++--
1 file changed, 3
This patchset fixes some important bugs in the hppa artist graphics driver:
- Fix framebuffer access for Linux
- Mouse cursor fixes for HP-UX
New qemu features for hppa:
- Allow up to 16 emulated CPUs (instead of 8)
- Add support for an emulated TOC/NMI button
A new Seabios-hppa firmware:
- Updat
Almost all PA-RISC machines have either a button that is labeled with 'TOC' or
a BMC/GSP function to trigger a TOC. TOC is a non-maskable interrupt that is
sent to the processor. This can be used for diagnostic purposes like obtaining
a stack trace/register dump or to enter KDB/KGDB in Linux.
Th
On Wed, Jan 12, 2022 at 9:39 PM Peter Lieven wrote:
>
> Am 12.01.22 um 10:05 schrieb Ilya Dryomov:
> > On Mon, Jan 10, 2022 at 12:42 PM Peter Lieven wrote:
> >> the assumption that we can't hit a hole if we do not diff against a
> >> snapshot was wrong.
> >>
> >> We can see a hole in an image if
Am 12.01.22 um 10:05 schrieb Ilya Dryomov:
> On Mon, Jan 10, 2022 at 12:42 PM Peter Lieven wrote:
>> the assumption that we can't hit a hole if we do not diff against a snapshot
>> was wrong.
>>
>> We can see a hole in an image if we diff against base if there exists an
>> older snapshot
>> of t
Hi Hanna, Kevin:
I think this series is pretty close, it's mostly reviewed by Vladimir
and Beraldo. Only patches 22 and 23 touch iotests, and quite
minimally. Everything appears to test fine on my end, but I don't
wanna sneak any changes past you without an ACK.
(OK, admittedly, patch 22 is a tou
Unfortunately I ran out of cycles at the time. Adding test cases seems
like it was the roadblock - I don't think I ever figured out how to
implement the needed build tests for this additional feature in chardev.
I'm not that strong of a C developer, unfortunately.
I haven't looked at picking this
On Wed, Jan 12, 2022 at 12:51 PM Daniel P. Berrangé wrote:
>
> On Wed, Jan 12, 2022 at 12:47:01PM -0500, John Snow wrote:
> > On Wed, Jan 12, 2022 at 12:34 PM Daniel P. Berrangé
> > wrote:
> > >
> > > On Wed, Jan 12, 2022 at 12:25:16PM -0500, John Snow wrote:
> > > > On Wed, Jan 12, 2022 at 5:56
On Wed, Jan 12, 2022 at 12:47:01PM -0500, John Snow wrote:
> On Wed, Jan 12, 2022 at 12:34 PM Daniel P. Berrangé
> wrote:
> >
> > On Wed, Jan 12, 2022 at 12:25:16PM -0500, John Snow wrote:
> > > On Wed, Jan 12, 2022 at 5:56 AM Stefan Hajnoczi
> > > wrote:
> > > >
> > > > [Context: John created
On Wed, Jan 12, 2022 at 12:34 PM Daniel P. Berrangé wrote:
>
> On Wed, Jan 12, 2022 at 12:25:16PM -0500, John Snow wrote:
> > On Wed, Jan 12, 2022 at 5:56 AM Stefan Hajnoczi wrote:
> > >
> > > [Context: John created a PyPI QEMU user in order to publish the qemu.qmp
> > > package. If anyone wants
On Wed, Jan 12, 2022 at 8:52 AM Beraldo Leal wrote:
>
> On Mon, Jan 10, 2022 at 06:28:53PM -0500, John Snow wrote:
> > We have a replacement for async QMP, but it doesn't have feature parity
> > yet. For now, then, port the old tool onto the new backend.
> >
> > Signed-off-by: John Snow
> > Revie
On 11/01/2022 19:10, Sebastian Hasler wrote:
With the current implementation, blocking flock can lead to
deadlock. Thus, it's better to return EOPNOTSUPP if a user attempts
to perform a blocking flock request.
Signed-off-by: Sebastian Hasler
---
tools/virtiofsd/passthrough_ll.c | 6 ++
On Wed, Jan 12, 2022 at 5:07 AM Daniel P. Berrangé wrote:
>
> On Tue, Jan 11, 2022 at 02:48:55PM -0500, John Snow wrote:
> > On Fri, Dec 17, 2021 at 8:46 AM Daniel P. Berrangé
> > wrote:
> >
> > > On Thu, Dec 16, 2021 at 06:35:23PM -0500, John Snow wrote:
> > > > On Thu, Dec 16, 2021 at 5:48 AM D
On Wed, Jan 12, 2022 at 12:25:16PM -0500, John Snow wrote:
> On Wed, Jan 12, 2022 at 5:56 AM Stefan Hajnoczi wrote:
> >
> > [Context: John created a PyPI QEMU user in order to publish the qemu.qmp
> > package. If anyone wants to publish additional Python packages from
> > qemu.git, please contact
Now that virtio-blk and virtio-scsi are ready, get rid of
the handle_aio_output() callback. It's no longer needed.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Stefano Garzarella
Message-id: 20211207132336.36627-7-stefa...@redhat.com
Signed-off-by: Stefan Hajnoczi
---
include/hw/virtio/virtio.h
The return value of virtio_blk_handle_vq() is no longer used. Get rid of
it. This is a step towards unifying the dataplane and non-dataplane
virtqueue handler functions.
Prepare virtio_blk_handle_output() to be used by both dataplane and
non-dataplane by making the condition for starting ioeventfd
The difference between ->handle_output() and ->handle_aio_output() was
that ->handle_aio_output() returned a bool return value indicating
progress. This was needed by the old polling API but now that the bool
return value is gone, the two functions can be unified.
Signed-off-by: Stefan Hajnoczi
R
Am 02.09.2021 um 11:37 hat Vladimir Sementsov-Ogievskiy geschrieben:
> First, this permission never protected a node from being changed, as
> generic child-replacing functions don't check it.
>
> Second, it's a strange thing: it presents a permission of parent node
> to change its child. But gener
On Wed, Jan 12, 2022 at 5:56 AM Stefan Hajnoczi wrote:
>
> [Context: John created a PyPI QEMU user in order to publish the qemu.qmp
> package. If anyone wants to publish additional Python packages from
> qemu.git, please contact him for PyPI access.]
>
> On Tue, Jan 11, 2022 at 03:42:23PM -0500, J
Adaptive polling measures the execution time of the polling check plus
handlers called when a polled event becomes ready. Handlers can take a
significant amount of time, making it look like polling was running for
a long time when in fact the event handler was running for a long time.
For example,
The virtqueue host notifier API
virtio_queue_aio_set_host_notifier_handler() polls the virtqueue for new
buffers. AioContext previously required a bool progress return value
indicating whether an event was handled or not. This is no longer
necessary because the AioContext polling API has been split
Philippe Mathieu-Daudé writes:
> Fix typo in 'make check-help' output.
Queued to testing/next, thanks.
--
Alex Bennée
Prepare virtio_scsi_handle_cmd() to be used by both dataplane and
non-dataplane by making the condition for starting ioeventfd more
specific. This way it won't trigger when dataplane has already been
started.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Stefano Garzarella
Message-id: 202112071323
The following changes since commit 91f5f7a5df1fda8c34677a7c49ee8a4bb5b56a36:
Merge remote-tracking branch
'remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request' into staging
(2022-01-12 11:51:47 +)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags
According to PoP, both 32- and 64-bit shifts use lowest 6 address
bits. The current code special-cases 32-bit shifts to use only 5 bits,
which is not correct. For example, shifting by 32 bits currently
preserves the initial value, however, it's supposed zero it out
instead.
Fix by merging sh32 and
On Wed, Jan 12, 2022 at 03:21:44PM +0300, Vladislav Yaroshchuk wrote:
> vmnet.framework dependency is added with 'vmnet' option
> to enable or disable it. Default value is 'auto'.
>
> vmnet features to be used are available since macOS 11.0,
> corresponding probe is created into meson.build.
>
>
SRDA uses r1_D32 for binding the first operand and s64 for setting CC.
cout_s64() relies on o->out being the shift result, however,
wout_r1_D32() clobbers it.
Fix by using a temporary.
Fixes: a79ba3398a0a ("target-s390: Convert SHIFT DOUBLE")
Signed-off-by: Ilya Leoshkevich
---
target/s390x/tcg
v3: https://lists.nongnu.org/archive/html/qemu-devel/2022-01/msg02680.html
v3 -> v4: Simplify cc_calc_sla().
Free temporaries.
v2: https://lists.nongnu.org/archive/html/qemu-devel/2022-01/msg02488.html
v2 -> v3: Unify CC_OP_SLA_32 and CC_OP_SLA_64.
Add underscores to test macro
SLDA operates on 64-bit values, so its sign bit index should be 63,
not 31.
Fixes: a79ba3398a0a ("target-s390: Convert SHIFT DOUBLE")
Reported-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
Reviewed-by: David Hildenbrand
---
target/s390x/tcg/insn-data.def | 2 +-
1 file changed, 1 inser
Add a test for each shift instruction in order to to prevent
regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/shift.c | 270
2 files changed, 271 insertions(+)
create mode 100644 tests/tcg/s390x/sh
An overflow occurs for SLAG when at least one shifted bit is not equal
to sign bit. Therefore, we need to check that `shift + 1` bits are
neither all 0s nor all 1s. The current code checks only `shift` bits,
missing some overflows.
Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE")
> > I mean, that would be fundamentally broken, because the fsync() would
> > corrupt the file. So I assume in a sane environment, the dst could only
> > have stale clean pagecache pages. And we'd have to get rid of these to
> > re-read everything from file.
> > >>>
> > >>> In c
Anup Patel 於 2021年12月30日 週四 下午8:59寫道：
> From: Anup Patel
>
> We should use the AIA INTC compatible string in the CPU INTC
> DT nodes when the CPUs support AIA feature. This will allow
> Linux INTC driver to use AIA local interrupt CSRs.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Anup Patel
> I mean, that would be fundamentally broken, because the fsync() would
> corrupt the file. So I assume in a sane environment, the dst could only
> have stale clean pagecache pages. And we'd have to get rid of these to
> re-read everything from file.
> >>>
> >>> In case of write
Anup Patel 於 2021年12月30日 週四 下午8:51寫道：
> From: Anup Patel
>
> The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
> which allow indirect access to interrupt priority arrays and per-HART
> IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
>
> Signed-off-by: Anup P
After the recent restructuring, I'd like to volunteer to help
in some of the s390 I/O areas.
Built on "[PATCH RFC v2] MAINTAINERS: split out s390x sections"
Signed-off-by: Eric Farman
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5d37b0ee
On Wed, 2022-01-12 at 16:45 +0100, David Hildenbrand wrote:
> > > If the sign is false, the shifted bits (mask) have to be 0.
> > > If the sign bit is true, the shifted bits (mask) have to be set.
> >
> > IIUC this logic handles sign bit + "shift - 1" bits. So if the last
> > shifted bit is differ
On 12.01.22 17:08, Pankaj Gupta wrote:
I mean, that would be fundamentally broken, because the fsync() would
corrupt the file. So I assume in a sane environment, the dst could only
have stale clean pagecache pages. And we'd have to get rid of these to
re-read everything from fil
On Tue, 11 Jan 2022 at 19:55, Laurent Vivier wrote:
>
> The following changes since commit 64c01c7da449bcafc614b27ecf1325bb08031c84:
>
> Merge remote-tracking branch 'remotes/philmd/tags/sdmmc-20220108' into
> staging (2022-01-11 11:39:31 +)
>
> are available in the Git repository at:
>
>
On Sat, 18 Dec 2021 at 02:28, Richard Henderson
wrote:
> What I don't understand is how these controls get applied to qemu_irq after
> vmload, here
> or in any other device. It seems like we should have some post_load hook
> that calls
> timer_update_irq, etc.
Very late answer, but: we don't n
> static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest)
> {
> if (dest == s->pc_tmp) {
> @@ -4113,9 +4099,15 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps
> *o)
>
> static DisasJumpType op_sla(DisasContext *s, DisasOps *o)
> {
> +TCGv_i64 t;
> uint6
On Wed, Jan 12, 2022 at 01:45:05PM +0100, Cédric Le Goater wrote:
> Hello Gregory,
>
> On 1/12/22 11:57, Graeme Gregory wrote:
> > On Tue, Jan 11, 2022 at 04:45:44PM +0800, Troy Lee wrote:
> > > This series of patch introduce a dummy implemenation of aspeed i3c
> > > model, and it provide just eno
On Wed, Jan 12, 2022 at 04:23:30PM +0300, Vladislav Yaroshchuk wrote:
> ср, 12 янв. 2022 г. в 11:22, Roman Bolshakov :
>
> > On Wed, Jan 12, 2022 at 10:50:04AM +0300, Roman Bolshakov wrote:
> > > On Wed, Jan 12, 2022 at 12:14:15AM +0300, Vladislav Yaroshchuk wrote:
> > > > v9 -> v10
> > > > - Dis
>> If the sign is false, the shifted bits (mask) have to be 0.
>> If the sign bit is true, the shifted bits (mask) have to be set.
>
> IIUC this logic handles sign bit + "shift - 1" bits. So if the last
> shifted bit is different, the overflow is not detected.
Ah, right, because of the - 1ULL ...
> >> I mean, that would be fundamentally broken, because the fsync() would
> >> corrupt the file. So I assume in a sane environment, the dst could only
> >> have stale clean pagecache pages. And we'd have to get rid of these to
> >> re-read everything from file.
> >
> > In case of write back cache
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