On Fri, Jan 7, 2022 at 10:18 AM Atish Patra wrote:
>
> The RISC-V privilege specification provides flexibility to implement
> any number of counters from 29 programmable counters. However, the QEMU
> implements all the counters.
>
> Make it configurable through pmu config parameter which now will
On Fri, Jan 7, 2022 at 10:14 AM Atish Patra wrote:
>
> From: Atish Patra
>
> Currently, the predicate function for PMU related CSRs only works if
> virtualization is enabled. It also does not check mcounteren bits before
> before cycle/minstret/hpmcounterx access.
>
> Support supervisor mode acce
On 05/01/2022 10:48, Thomas Huth wrote:
Add some documentation files to the corresponding machine sections
and mention the machine names in the section titles where it is
not so obvious (e.g. that "taihu" is a 405 machine).
Signed-off-by: Thomas Huth
---
MAINTAINERS | 12
1 fil
On 1/7/22 08:24, Alexey Kardashevskiy wrote:
"PowerPC Processor binding to IEEE 1275" says in
"8.2.1. Initial Register Values" that the initial state is defined as
32bit so do it for both SLOF and VOF.
This should not cause behavioral change as SLOF switches to 64bit very
early anyway. As nothin
"PowerPC Processor binding to IEEE 1275" says in
"8.2.1. Initial Register Values" that the initial state is defined as
32bit so do it for both SLOF and VOF.
This should not cause behavioral change as SLOF switches to 64bit very
early anyway. As nothing enforces LE anywhere, this drops it for VOF.
On 06/01/2022 13.22, Laurent Vivier wrote:
"qemu-system-m68k -M q800 -bios /dev/null" crahses with a segfault
in q800_init().
This happens because the code doesn't check that rom_ptr() returned
a non-NULL pointer .
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/756
Reported-by: Peter Ma
On 05/01/2022 20.52, Lucas Ramage wrote:
Hi Thomas,
I intentionally sent the email via my gmx address. But I want my commit under
the infinite-omicron email address.
I had a few warnings on my end, but it builds fine with Sphinx v3.4.3 on Debian
Bullseye. I can clean up the warnings in the ne
On 1/7/2022 12:06 AM, Laszlo Ersek wrote:
On 01/04/22 14:08, Xiaoyao Li wrote:
+ Laszlo,
Regarding laoding TDVF as pflash, I have some questions:
- pflash requires KVM to support readonly mmeory. However, for TDX, it
doesn't support readonly memory. Is it a must? or we can make an
exception f
On Fri, Jan 7, 2022 at 4:23 PM Frédéric Pétrot
wrote:
>
> On 06/01/2022 22:24, Alistair Francis wrote:
> > On Fri, Jan 7, 2022 at 7:04 AM Frédéric Pétrot
> > wrote:
> >>
> >> This patch adds the support of the '-cpu rv128' option to
> >> qemu-system-riscv64 so that we can indicate that we want to
On 06/01/2022 22:24, Alistair Francis wrote:
On Fri, Jan 7, 2022 at 7:04 AM Frédéric Pétrot
wrote:
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that s
在 2022/1/6 下午12:18, Jason Wang 写道:
在 2021/12/11 下午6:44, Vladislav Yaroshchuk 写道:
macOS provides networking API for VMs called 'vmnet.framework':
https://developer.apple.com/documentation/vmnet
We can provide its support as the new QEMU network backends which
represent three different vmnet.f
On 1/6/22 1:41 AM, Song Gao wrote:
Based-on:<20220106074740.1754661-1-gaos...@loongson.cn>
Hi all,
This series only support linux-user emulation.
More about LoongArch at:https://github.com/loongson/
The latest kernel:
*https://github.com/loongson/linux/tree/loongarch-next
Patches need revi
On 1/6/22 1:41 AM, Song Gao wrote:
+struct target_sigcontext {
+uint64_t sc_pc;
+uint64_t sc_regs[32];
+uint32_t sc_flags;
+uint32_t sc_fcsr;
+uint32_t sc_vcsr;
+uint64_t sc_fcc;
+uint64_t sc_scr[4];
+union fpureg sc_fpregs[32] __attribute__((aligned(32)));
+ui
On Mon, Dec 20, 2021 at 9:17 AM Zhang Chen wrote:
>
> Make the comments consistent with the REGULAR_PACKET_CHECK_MS.
>
> Signed-off-by: Zhang Chen
Applied.
Thanks
> ---
> net/colo-compare.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/net/colo-compare.c b/net/colo-
On Mon, Dec 20, 2021 at 9:16 AM Zhang Chen wrote:
>
> COLO-compare use the glib function g_queue_find_custom to dump
> another VM's networking packet to compare. But this function always
> start find from the queue->head(here is the newest packet), It will
> reduce the success rate of comparison.
On Mon, Dec 27, 2021 at 10:14 AM Zhang, Chen wrote:
>
>
>
> > -Original Message-
> > From: Rao, Lei
> > Sent: Monday, December 27, 2021 9:20 AM
> > To: Zhang, Chen ; lizhij...@cn.fujitsu.com;
> > jasow...@redhat.com
> > Cc: qemu-devel@nongnu.org; Rao, Lei ; Li Zhijian
> >
> > Subject: [P
On 1/6/22 1:41 AM, Song Gao wrote:
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/target_structs.h | 47 +
1 file changed, 47 insertions(+)
create mode 100644 linux-user/loongarch64/target_structs.h
I've just sent a patch set such th
Most targets share the same generic ipc structure definitions.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_structs.h| 59 +-
linux-user/arm/target_structs.h| 52 +--
linux-user/cris/target_structs.h | 59 +--
Place it next to copy_from/to_user_oabi_flock64, the only users,
inside the existing target-specific ifdef. This leaves only
generic ipc structs in target_structs.h.
Signed-off-by: Richard Henderson
---
linux-user/arm/target_structs.h | 8
linux-user/syscall.c| 8
I noticed this while reviewing loongarch64.
r~
Richard Henderson (2):
linux-user/arm: Move target_oabi_flock64 out of target_structs.h
linux-user: Move target_struct.h generic definitions to generic/
linux-user/aarch64/target_structs.h| 59 +
linux-user/arm/targe
On Mon, Dec 20, 2021 at 4:49 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Populate mtval and stval when taking an illegal instruction exception.
>
> The RISC-V spec states that "The stval register can optionally also be
> used to return the faulting instruction bits on an illegal ins
On 1/5/22 12:40 PM, Fabiano Rosas wrote:
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 77 +---
1 file changed, 8 insertions(+), 69 deletions(-)
Reviewed-by: Richard Henderson
r~
在 2022/1/6 下午10:09, Michael S. Tsirkin 写道:
On Thu, Jan 06, 2022 at 10:34:20AM +0800, Jason Wang wrote:
On Wed, Jan 5, 2022 at 8:26 PM Michael S. Tsirkin wrote:
On Wed, Jan 05, 2022 at 05:09:07PM +0800, Jason Wang wrote:
On Wed, Jan 5, 2022 at 4:37 PM Longpeng (Mike, Cloud Infrastructure
Ser
在 2022/1/6 下午4:00, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) 写道:
-Original Message-
From: Jason Wang [mailto:jasow...@redhat.com]
Sent: Thursday, January 6, 2022 10:34 AM
To: Michael S. Tsirkin
Cc: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
; Stefan H
On Fri, Jan 7, 2022 at 3:44 AM Philippe Mathieu-Daudé wrote:
>
> On 6/1/22 19:28, Patrick Venture wrote:
> > From: Peter Foley
> >
> > e.g.
> > 1109 15:16:20.151506 Uninitialized bytes in ioctl_common_pre at offset 0
> > inside [0x7ffc516af9b8, 4)
> > 1109 15:16:20.151659 ==588974==WARNING: Me
From: Atish Patra
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
target/riscv/cpu_helper.c | 26 ++
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Signed-off-by: Atish Patra
Si
On Thu, Jan 6, 2022 at 7:25 PM Stefan Hajnoczi wrote:
>
> On Thu, Jan 06, 2022 at 01:22:19AM +, Longpeng (Mike, Cloud
> Infrastructure Service Product Dept.) wrote:
> >
> >
> > > -Original Message-
> > > From: Stefan Hajnoczi [mailto:stefa...@redhat.com]
> > > Sent: Wednesday, January
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to leverage the extension. A
From: Atish Patra
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by
From: Atish Patra
With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 11 +
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
as a unified counter. Thus, the predicate function doesn't need handle each
case separately.
Simplify the predicate function so that we just handle things differently
between RV32/RV64 and S/HS mode.
Signed-off-by: Atish P
The latest version of the SBI specification includes a Performance Monitoring
Unit(PMU) extension[1] which allows the supervisor to start/stop/configure
various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level
extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Fil
From: Atish Patra
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h |
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many programmable counters should be implemented b
From: Atish Patra
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as wel
From: Atish Patra
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair Franc
From: Atish Patra
mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.
Support mcycle/minstret
On Thu, Jan 6, 2022 at 12:04 PM Alistair Francis wrote:
>
> On Tue, Dec 21, 2021 at 5:30 PM Bin Meng wrote:
> >
> > On Mon, Dec 20, 2021 at 2:49 PM Alistair Francis
> > wrote:
> > >
> > > From: Alistair Francis
> > >
> > > In preperation for adding support for the illegal instruction address
>
On Thu, Jan 06, 2022 at 02:02:01PM +0100, Greg Kurz wrote:
> On Thu, 6 Jan 2022 13:21:46 +0100
> Cédric Le Goater wrote:
>
> > On 1/6/22 12:23, Víctor Colombo wrote:
> > > xscmpnedp was added in ISA v3.0 but removed in v3.0B. This patch
> > > removes this instruction as it was not in the final ve
On Thu, Jan 6, 2022 at 11:27 PM Peter Maydell wrote:
>
> On Tue, 28 Dec 2021 at 03:34, Troy Lee wrote:
> >
> > Hi Klaus,
> >
> > On Thu, Dec 23, 2021 at 11:57 PM Klaus Heinrich Kiwi
> > wrote:
> > >
> > > Em qui., 23 de dez. de 2021 às 09:54, Cédric Le Goater
> > > escreveu:
> > > >
> > > > [
On 1/5/22 12:40 PM, Fabiano Rosas wrote:
Remove the compile time definition and make the logging be controlled
by the `-d mmu` option in the cmdline.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 15 ++-
1 file changed, 6 insertions(+)
On 1/5/22 12:40 PM, Fabiano Rosas wrote:
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 63 +++-
1 file changed, 36 insertions(+), 27 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a779dc936a..2c5d5470de 100
On 12/31/21 2:39 AM, Idan Horowitz wrote:
Some of the instructions added by the FEAT_TLBIOS extension were forgotten
when the extension was originally added to QEMU.
Fixes: 7113d618505b ("target/arm: Add support for FEAT_TLBIOS")
Signed-off-by: Idan Horowitz
---
target/arm/helper.c | 32 ++
On Sun, Dec 26, 2021 at 8:38 PM Frank Chang wrote:
>
> Atish Patra 於 2021年10月26日 週二 上午3:57寫道：
>>
>> The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
>> and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
>> extension allows the perf to handle overflow interrupts a
On 1/4/22 12:54 AM, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Various APIs use 'pval' naming for 'pointer to val'.
rdma_pci_dma_map() uses 'plen' for 'PCI length', but since
'PCI' is already explicit in the function name, simplify
and rename the argument 'len'. No logical change
On 1/4/22 12:54 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ide/ahci.c| 2 +-
hw/rdma/trace-events | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 1/4/22 12:54 AM, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
DMA API should not be included in user-mode emulation.
If so, build should fail. Remove the CONFIG_USER_ONLY check.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/dma
On 1/4/22 12:54 AM, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
The 'resid' field is slightly confusing and could be
interpreted as some ID. Rename it as 'residual' which
is clearer to review. No logical change.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathie
On 1/4/22 12:54 AM, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
On 1/4/22 12:54 AM, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Neither tools nor user-mode emulation require the PCI bus stub.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
stubs/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
On 1/4/22 12:54 AM, Philippe Mathieu-Daudé wrote:
+if have_system or have_tools
...
if have_system
+ stub_ss.add(files('fw_cfg.c'))
Disconnect in tests?
r~
On 1/5/22 5:50 AM, Alex Bennée wrote:
The various approaches to finding memory holes are quite complicated
to follow especially at a distance. Improve the logging so we can see
exactly what method found the space for the guest memory.
Signed-off-by: Alex Bennée
---
linux-user/elfload.c | 18 ++
The Renesas RAA229004 is a PMBus Multiphase Voltage Regulator
Signed-off-by: Titus Rwantare
Reviewed-by: Hao Wu
---
hw/sensor/isl_pmbus.c | 18 ++
include/hw/sensor/isl_pmbus.h | 1 +
tests/qtest/isl_pmbus-test.c | 7 +++
3 files changed, 26 insertions(+)
diff --
Signed-off-by: Titus Rwantare
Reviewed-by: Hao Wu
---
MAINTAINERS | 3 +
hw/arm/Kconfig| 1 +
hw/sensor/Kconfig | 5 +
hw/sensor/isl_pmbus.c | 210 +++
hw/sensor/meson.build | 1 +
include/hw/sensor/isl_pmbus.h
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Titus Rwantare
---
hw/i2c/pmbus_device.c | 18 ++
include/hw/i2c/pmbus_device.h | 20 +++-
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_dev
This patch series contains updates to PMBus in QEMU along with some PMBus
device models for Renesas regulators.
I have also added myself to MAINTAINERS as this code is in use daily,
where I am responsible for it.
Shengtan Mao (1):
hw/i2c: Added linear mode translation for pmbus devices
Titus Rw
- add vout min register
- add PEC unsupported warning to pmbus_device class
- guard against out of range pmbus page accesses
Signed-off-by: Titus Rwantare
Reviewed-by: Hao Wu
---
MAINTAINERS | 12 -
hw/i2c/pmbus_device.c | 88 +++--
Signed-off-by: Titus Rwantare
Reviewed-by: Hao Wu
---
hw/sensor/isl_pmbus.c | 50 ++
include/hw/sensor/isl_pmbus.h | 1 +
tests/qtest/isl_pmbus-test.c | 78 +--
3 files changed, 126 insertions(+), 3 deletions(-)
diff --git a/hw/senso
On 1/6/22 5:16 AM, Michael S. Tsirkin wrote:
Big changes that were tagged originally but did not make the cut:
- SRIOV/nvme (not sure they are my tree material anyway)
- TPM (blocked over Igor's compat concerns)
- ACPI ERST (some coding style violations)
The following changes since commit 7d4ae4
The kernel does not special-case arg2 != NULL, so
neither should we.
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index ce9d64896c..e8f9e0643e 100644
--- a/linux-user/sysc
This is PR_CAPBSET_READ, PR_CAPBSET_DROP and the "legacy"
PR_CAP_AMBIENT PR_GET_SECUREBITS, PR_SET_SECUREBITS.
All of these arguments are integer values only, and do not
require mapping of values between host and guest.
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 5 +
1 file
Hi Laurent, as requested. I did all of the cap_task_prctl options,
and fixed a few existing bugs with PR_GET_DEATHSIG.
r~
Richard Henderson (4):
linux-user: Do not special-case NULL for PR_GET_PDEATHSIG
linux-user: Map signal number in PR_GET_PDEATHSIG
linux-user: Implement PR_SET_PDEATHSI
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 9eb2fb2bb2..8495f5e08e 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6450,6 +6450,9 @@ static abi_long do_prctl(CPU
Convert the host signal number to guest signal number
before returning the value to the guest.
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index e8f9e0643e..9eb2fb2bb2
On 1/5/2022 3:16 PM, Michael S. Tsirkin wrote:
> On Wed, Jan 05, 2022 at 12:22:25PM -0500, Steven Sistare wrote:
>> On 12/22/2021 6:07 PM, Michael S. Tsirkin wrote:
>>> On Wed, Dec 22, 2021 at 11:05:22AM -0800, Steve Sistare wrote:
Export msix_is_pending, msix_init_vector_notifiers, and pci_up
This parameter is to be used in the processor_id lower 32-bit entry in
the type 4 table. The upper 32-bits represent the features for the CPU.
This patch leaves those as 0 when the lower 32-bits are set.
This parameter is set as optional and if left will use the values from
the CPU model.
This e
On Fri, Jan 7, 2022 at 12:30 AM Philipp Tomsich
wrote:
>
> When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set
> them to be enabled by default, the comment about experimental
> extensions was kept in place above them. This moves it down a few
> lines to only cover experimental ext
On Thu, Dec 23, 2021 at 11:14:25AM +0100, Philippe Mathieu-Daudé wrote:
> Add missing vhost-user-blk help:
>
> $ qemu-storage-daemon -h
> ...
> --export [type=]vhost-user-blk,id=,node-name=,
> addr.type=unix,addr.path=[,writable=on|off]
> [,logical-block-size=][,n
Add property that allows zero-copy migration of memory pages,
and also includes a helper function migrate_use_zero_copy() to check
if it's enabled.
No code is introduced to actually do the migration, but it allow
future implementations to enable/disable this feature.
On non-Linux builds this para
A lot of places check parameters.tls_creds in order to evaluate if TLS is
in use, and sometimes call migrate_get_current() just for that test.
Add new helper function migrate_use_tls() in order to simplify testing
for TLS usage.
Signed-off-by: Leonardo Bras
Reviewed-by: Juan Quintela
---
migra
Implement zero copy on nocomp_send_write(), by making use of QIOChannel
writev + flags & flush interface.
Change multifd_send_sync_main() so it can distinguish each iteration sync from
the setup and the completion, so a flush_zero_copy() can be called
after each iteration in order to make sure all
This patch series intends to enable MSG_ZEROCOPY in QIOChannel, and make
use of it for multifd migration performance improvement, by reducing cpu
usage.
Patch #1 creates new callbacks for QIOChannel, allowing the implementation
of zero copy writing.
Patch #2 implements io_writev flags and io_flus
Add flags to io_writev and introduce io_flush as optional callback to
QIOChannelClass, allowing the implementation of zero copy writes by
subclasses.
How to use them:
- Write data using qio_channel_writev(...,QIO_CHANNEL_WRITE_FLAG_ZERO_COPY),
- Wait write completion with qio_channel_flush().
Not
For CONFIG_LINUX, implement the new zero copy flag and the optional callback
io_flush on QIOChannelSocket, but enables it only when MSG_ZEROCOPY
feature is available in the host kernel, which is checked on
qio_channel_socket_connect_sync()
qio_channel_socket_flush() was implemented by counting how
From: Shu-Chun Weng
Linux kernel does it this way (checks read permission before validating `how`)
and the latest version of ABSL's `AddressIsReadable()` depends on this
behavior.
c.f.
https://github.com/torvalds/linux/blob/9539ba4308ad5bdca6cb41c7b73cbb9f796dcdd7/kernel/signal.c#L3147
Reviewe
On Fri, Jan 7, 2022 at 12:30 AM Philipp Tomsich
wrote:
>
> When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set
> them to be enabled by default, the comment about experimental
> extensions was kept in place above them. This moves it down a few
> lines to only cover experimental ext
On Wed, 05 Jan 2022 09:22:39 +,
Eric Auger wrote:
>
> Hi Marc,
>
> On 12/27/21 10:16 PM, Marc Zyngier wrote:
> > Even when the VM is configured with highmem=off, the highest_gpa
> > field includes devices that are above the 4GiB limit.
> > Similarily, nothing seem to check that the memory is
/qemu.git
tags/linux-user-for-7.0-pull-request
for you to fetch changes up to f0effdbc2a5b43422bc4c9c22641ef9dafa0c7ae:
linux-user: netlink: update IFLA_BRPORT entries (2022-01-06 11:40:53 +0100)
linux-user pull request 20220106
On Fri, Jan 7, 2022 at 7:04 AM Frédéric Pétrot
wrote:
>
> This patch adds the support of the '-cpu rv128' option to
> qemu-system-riscv64 so that we can indicate that we want to run rv128
> executables.
> Still, there is no support for 128-bit insns at that stage so qemu fails
> miserably (as expe
The csrs are accessed through function pointers: we add 128-bit read
operations in the table for three csrs (writes fallback to the
64-bit version as the upper 64-bit information is handled elsewhere):
- misa, as mxl is needed for proper operation,
- mstatus and sstatus, to return sd
In addition, w
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We return 128-bit values using the same approach as for div/rem.
Theses helpers all call a unique function that is currently a fallback
on the 64-bit version
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
R
Adding the 128-bit version of lui and auipc, and introducing to that end
a "set register with immediat" function to handle extension on 128 bits.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translat
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 10 ++
target
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 4
target/riscv/machine.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/targe
Get function to retrieve the 64 top bits of a register, stored in the gprh
field of the cpu state. Set function that writes the 128-bit value at once.
The access to the gprh field can not be protected at compile time to make
sure it is accessed only in the 128-bit version of the processor because w
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/riscv/insn32.deco
Mult are generated inline (using a cool trick pointed out by Richard), but
for div and rem, given the complexity of the implementation of these
instructions, we call helpers to produce their behavior. From an
implementation standpoint, the helpers return the low part of the results,
while the high
Yeah, but this same pattern is used elsewhere in the file, so I went with
being consistent.
On Thu, Jan 6, 2022, 2:44 PM Philippe Mathieu-Daudé wrote:
> On 6/1/22 19:28, Patrick Venture wrote:
> > From: Peter Foley
> >
> > e.g.
> > 1109 15:16:20.151506 Uninitialized bytes in ioctl_common_pre at
Introduction of a gen_logic function for bitwise logic to implement
instructions in which no propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 9 +
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by: Frédéric Pétrot
Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Although RV128 is a superset o
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
wher
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Revi
Addition of div and rem on 128-bit integers, using the 128/64->128 divu and
64x64->128 mulu in host-utils.
These operations will be used within div/rem helpers in the 128-bit riscv
target.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Reviewed-by: Alistair Francis
---
include/qe
Adding defines to handle signed 64-bit and unsigned 128-bit quantities in
memory accesses.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
include/exec/memop.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/exec/memop.h b/incl
This series of patches provides partial 128-bit support for the riscv
target architecture, namely RVI and RVM, with minimal csr support.
Thanks for the reviews and advices.
v8:
- rebase on riscv-to-apply.next
v7:
- code motion following reviews
- correction of a bug preventing riscv{32,64}-linux
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