From: Fabiano Rosas
We can just access it directly in powerpc_excp.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Reviewed-by: Richard Henderson
Reviewed-by: David Gibson
[ clg: Took into account removal of inline ]
Message-Id: <20211229165751.3774248-6-faro...@linux.ibm.com>
Si
From: Fabiano Rosas
There are currently only two interrupts that use alternate SRRs, so
let them write to them directly during the setup code.
No functional change intended.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Cédric Le Goater
Reviewed-by: David Gibson
M
On 12/31/21 08:31, Cédric Le Goater wrote:
For Radix translation, the EA range is 64-bits. when EA(2:11) are
nonzero, a segment interrupt should occur.
Signed-off-by: Cédric Le Goater
Applied in ppc-next.
Thanks,
C.
The compiler should know better how to inline code if necessary.
Suggested-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Reviewed-by: Richard Henderson
Message-Id: <20220103063441.3424853-2-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 12 ++--
1
The 405 timers were broken when booke support was added. Assumption
was made that the register numbers were the same but it's not :
SPR_BOOKE_TSR (0x150)
SPR_BOOKE_TCR (0x154)
SPR_40x_TSR (0x3D8)
SPR_40x_TCR (0x3DA)
Cc: Christophe Leroy
Fixes:
This is a small cleanup to ease reading. It includes the removal of a
check done on the returned value of g_malloc0(), which can not fail.
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-6-...@kaod.org>
Signed-off-by: Cédric Le Goater
Message-I
It facilitates reading the logs when mask CPU_LOG_INT is activated. We
should do the same for error codes.
Cc: Fabiano Rosas
Signed-off-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
Reviewed-by: David Gibson
Reviewed-by: Richard Henderson
Message-Id: <20211222064025.1541490-2-...@kaod.org>
From: Richard Henderson
Use the cached pmc_cyc_cnt value in pmu_update_cycles
and pmc_update_overflow_timer. This leaves pmc_get_event
and pmc_is_inactive unused, so remove them.
Signed-off-by: Richard Henderson
Message-Id: <20220103224746.167831-4-danielhb...@gmail.com>
Signed-off-by: Cédric
The following changes since commit b5a3d8bc9146ba22a25116cb748c97341bf99737:
Merge tag 'pull-misc-20220103' of https://gitlab.com/rth7680/qemu into
staging (2022-01-03 09:34:41 -0800)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-ppc-2022010
There is no need to deactivate MMU logging at compile time. Remove all
use of defines. Only keep DUMP_PAGE_TABLES for another series since
page tables could be dumped from the monitor.
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-4-...@kaod.org>
Signed-off-by: Cédric Le Goa
Rework slightly ppc_cpu_dump_state() to replace the various 'if'
statements with a 'switch'.
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-9-...@kaod.org>
Signed-off-by: Cédric Le Goater
Message-Id: <20220103063441.3424853-10-...@kaod.org>
Si
Signed-off-by: Cédric Le Goater
Reviewed-by: Richard Henderson
Message-Id: <20211222071002.1568894-1-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/mmu-radix64.c | 55 +---
1 file changed, 52 insertions(+), 3 deletions(-)
diff --git a/target/pp
Timers are already initialized in ppc4xx_init(). No need to do it a
second time with a wrong set.
Fixes: d715ea961254 ("PPC: 405: Fix ppc405ep initialization")
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
Message-Id: <20211222064025.1541490-7-...@kaod.org>
Signed-off-by: Cédric
It's unused.
Signed-off-by: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20211222063817.1541058-4-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 --
hw/pci-host/pnv_phb4.c | 1 -
hw/pci-host/pnv_phb4_pec.c | 3 ---
3 files
From: Fabiano Rosas
None of the interrupt setup code touches 'vector', so we can move it
earlier in the function. This will allow us to later move the System
Call Vectored setup that is on the top level into the
POWERPC_EXCP_SYSCALL_VECTORED code block.
This patch also moves the verification for
For Radix translation, the EA range is 64-bits. when EA(2:11) are
nonzero, a segment interrupt should occur.
Signed-off-by: Cédric Le Goater
Reviewed-by: Frederic Barrat
Message-Id: <20211231073122.3183583-1-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/mmu-radix64.h | 1 +
targ
The POWER8 processors with a NVLink logic unit have 4 PHB3 devices per
chip.
Signed-off-by: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20211222063817.1541058-2-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
From: Daniel Henrique Barboza
All pnv-phb3-root-bus buses are being created as 'root-bus'. This
makes it impossible to, for example, add a pnv-phb3-root-port in
a specific root bus, since they all have the same name. By default
the device will be parented by the pnv-phb3 device that precedeced it
Use a QEMU log primitive for errors and trace events for debug.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Reviewed-by: Richard Henderson
Message-Id: <20211222064025.1541490-3-...@kaod.org>
Signed-off-by: Cédric Le Goater
Message-Id: <20220103063441.3424853-4-...@kaod.org>
Signe
The PHB4 reset handler was preparing ground for PHB5 to set
appropriately the device id. We don't need it for the PHB4 since the
device id is already set in the root port complex. PH5 will introduce
its own.
"device-id" property is now useless. It should be removed.
Signed-off-by: Cédric Le Goate
From: Richard Henderson
This is the combination of frozen bit and counter type, on a per
counter basis. So far this is only used by HFLAGS_INSN_CNT, but
will be used more later.
Signed-off-by: Richard Henderson
[danielhb: fixed PMC4 cyc_cnt shift, insn run latch code,
MMCR0_FC handli
From: Daniel Henrique Barboza
This change has the same motivation as the one done for pnv-phb3-root-bus
buses previously. Defaulting every bus to 'root-bus' makes it impossible to
attach
root ports to specific buses and it doesn't allow for custom bus
naming because we're ignoring the 'id' value
On Fri, Dec 31, 2021 at 12:48:56PM +0100, Philippe Mathieu-Daudé wrote:
> +/**
> + * pci_dma_map: Map a physical memory region into a device PCI address space.
Shouldn't this be: "Map device PCI address space range into host virtual
address"?
--
Peter Xu
HiFive Unmatched PDMA supports high/low 32-bit access of 64-bit
register, but QEMU emulation supports low part access now. Enhance QEMU
emulation to support high 32-bit access.
Also, permit 4/8-byte valid access in PDMA as we have verified 32/64-bit
accesses of PDMA registers are supported.
Chan
It's obvious that PDMA supports 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA supports 32-bit access of
both 32/64-bit registers. Thus, we configure 32/64-bit memory access
of PDMA registers as valid in general.
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
Re
Real PDMA supports high 32-bit read/write memory access of 64-bit
register.
The following result is PDMA tested in U-Boot on Unmatched board:
1. Real PDMA allows high 32-bit read/write to 64-bit register.
=> mw.l 0x300 0x0 <= Disclaim channel 0
=> mw.l 0x300 0x1
Hi Bin,
Thanks for the review.
I will fix the commit log and the behavior of writing high 32-bit of RO
registers in v2 patch.
Thanks,
Jim Shu
On Tue, Jan 4, 2022 at 10:55 AM Bin Meng wrote:
> Hi Jim,
>
> On Tue, Dec 28, 2021 at 8:53 AM Jim Shu wrote:
> >
> > Real PDMA support high 32-bit rea
On 2022/1/4 12:27, Ani Sinha wrote:
On Tue, 4 Jan 2022, wangyanan (Y) wrote:
Hi Ani,
Thanks for your review.
On 2022/1/3 20:01, Ani Sinha wrote:
On Mon, 3 Jan 2022, Yanan Wang wrote:
Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory
to update PPTT binary. Also empty bios
On Tue, 4 Jan 2022, wangyanan (Y) wrote:
> Hi Ani,
> Thanks for your review.
>
> On 2022/1/3 20:01, Ani Sinha wrote:
> >
> > On Mon, 3 Jan 2022, Yanan Wang wrote:
> >
> > > Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory
> > > to update PPTT binary. Also empty bios-tables-tes
在 2022/1/4 10:32, Peter Xu 写道:
On Fri, Dec 31, 2021 at 12:36:40AM +0800, Hyman Huang wrote:
+struct {
+DirtyLimitState *states;
+int max_cpus;
+unsigned long *bmap; /* running thread bitmap */
+unsigned long nr;
+QemuThread thread;
+} *dirtylimit_state;
+
+static bool dirt
Hi Richard,
On 1/4/22 10:15, Richard Henderson wrote:
Version 3 was way back in August:
https://lore.kernel.org/qemu-devel/20210818191920.390759-1-richard.hender...@linaro.org/
Quite a few of the patches in there have been merged, but not all.
Based-on: <20211227150127.2659293-1-richard.hende
On Tue, Dec 28, 2021 at 8:53 AM Jim Shu wrote:
>
> It's obvious that PDMA support 64-bit access of 64-bit registers, and
%s/support/supports
> in previous commit, we confirm that PDMA support 32-bit access of both
%s/support/supports
> 32/64-bit registers. Thus, we configure 32/64-bit memory a
Hi Jim,
On Tue, Dec 28, 2021 at 8:53 AM Jim Shu wrote:
>
> Real PDMA support high 32-bit read/write memory access of 64-bit
%s/support/supports
> register.
>
> The following result is PDMA tested in U-Boot on Unmatched board:
>
> 1. Real PDMA is allowed high 32-bit read/write to 64-bit register
Remove qemu_run_machine_init_done_notifiers() since no implementation
and user.
Signed-off-by: Xiaoyao Li
---
include/sysemu/sysemu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 8fae667172ac..b9421e03ffdd 100644
--- a/include/sysemu/
The upper 16 bits of kvm_userspace_memory_region::slot are
address space id. Parse it separately in trace_kvm_set_user_memory().
Signed-off-by: Xiaoyao Li
---
accel/kvm/kvm-all.c| 5 +++--
accel/kvm/trace-events | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/accel/kvm
On Fri, Dec 31, 2021 at 12:36:40AM +0800, Hyman Huang wrote:
> > > +struct {
> > > +DirtyLimitState *states;
> > > +int max_cpus;
> > > +unsigned long *bmap; /* running thread bitmap */
> > > +unsigned long nr;
> > > +QemuThread thread;
> > > +} *dirtylimit_state;
> > > +
> > >
Hi Ani,
Thanks for your review.
On 2022/1/3 20:01, Ani Sinha wrote:
On Mon, 3 Jan 2022, Yanan Wang wrote:
Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory
to update PPTT binary. Also empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expe
Signed-off-by: Richard Henderson
---
tcg/tci.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index e76087ccac..92a7c81674 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -292,11 +292,11 @@ static bool tci_compare64(uint64_t u0, uint64_t
A mostly generic test for unaligned access raising SIGBUS.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tests/tcg/multiarch/sigbus.c | 68
1 file changed, 68 insertions(+)
create mode 100644 tests/tcg/multiarch/sigbus.c
diff --git a/test
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.h | 2 --
tcg/s390x/tcg-target.c.inc | 59 --
2 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index 527ada
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 2 --
tcg/riscv/tcg-target.c.inc | 63 --
2 files changed, 61 insertions(+), 4 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index ef78b99e98..11c9b3e4f4 100644
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 -
tcg/i386/tcg-target.c.inc | 103 --
2 files changed, 98 insertions(+), 7 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index b00a6da29
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 2 -
tcg/ppc/tcg-target.c.inc | 98
2 files changed, 90 insertions(+), 10 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 0943192cde..
Version 3 was way back in August:
https://lore.kernel.org/qemu-devel/20210818191920.390759-1-richard.hender...@linaro.org/
Quite a few of the patches in there have been merged, but not all.
Based-on: <20211227150127.2659293-1-richard.hender...@linaro.org>
There are follow-on patch sets for arm,
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 -
tcg/aarch64/tcg-target.c.inc | 91 +---
2 files changed, 74 insertions(+), 19 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 7a93ac8023..876af589ce 10064
On 2022/1/3 19:32, Andrew Jones wrote:
On Mon, Jan 03, 2022 at 04:46:35PM +0800, Yanan Wang wrote:
Support cluster level in generation of ACPI Processor Properties
Topology Table (PPTT) for ARM virt machines.
Signed-off-by: Yanan Wang
---
hw/arm/virt-acpi-build.c | 15 +++
1 f
Hi Drew,
Thanks for your review.
On 2022/1/3 19:24, Andrew Jones wrote:
On Mon, Jan 03, 2022 at 04:46:32PM +0800, Yanan Wang wrote:
Currently we generate a PPTT table of n-level processor hierarchy
with n-level loops in build_pptt(). It works fine as now there are
only three CPU topology paramet
Hi Drew,
On 2022/1/3 19:30, Andrew Jones wrote:
On Mon, Jan 03, 2022 at 04:46:33PM +0800, Yanan Wang wrote:
We have a generic build_pptt() in hw/acpi/aml-build.c but it's
currently only used in ARM acpi initialization. Now we are going
to support the new CPU cluster parameter which is currently
On Thu, Dec 23, 2021 at 08:30:09PM +0800, Chao Peng wrote:
> When a page fault from the secondary page table while the guest is
> running happens in a memslot with KVM_MEM_PRIVATE, we need go
> different paths for private access and shared access.
>
> - For private access, KVM checks if the page
Hi guys,
Ping...
> -Original Message-
> From: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
> Sent: Saturday, December 11, 2021 10:27 PM
> To: pbonz...@redhat.com; alex.william...@redhat.com; m...@redhat.com;
> mtosa...@redhat.com
> Cc: k...@vger.kernel.org; qemu-devel@nongn
MMCR0 writes will change only MMCR0 bits which are used to calculate
HFLAGS_PMCC0, HFLAGS_PMCC1 and HFLAGS_INSN_CNT hflags. No other machine
register will be changed during this operation. This means that
hreg_compute_hflags() is overkill for what we need to do.
pmu_update_summaries() is already u
On Fri, Dec 24, 2021 at 1:51 PM liweiwei wrote:
>
> Co-authored-by: ardxwe
> Signed-off-by: liweiwei
> Signed-off-by: wangjunqiang
> ---
> roms/SLOF| 2 +-
> target/riscv/cpu.c | 12
> target/riscv/cpu.h | 4
> target/riscv/translate.c | 8 +
From: Richard Henderson
This is the combination of frozen bit and counter type, on a per
counter basis. So far this is only used by HFLAGS_INSN_CNT, but
will be used more later.
Signed-off-by: Richard Henderson
[danielhb: fixed PMC4 cyc_cnt shift, insn run latch code,
MMCR0_FC handli
From: Richard Henderson
Use the cached pmc_ins_cnt value. Unroll the loop over the
different PMC counters. Treat the PMC4 run-latch specially.
Signed-off-by: Richard Henderson
---
target/ppc/power8-pmu.c | 78 ++---
1 file changed, 49 insertions(+), 29 del
From: Richard Henderson
Use the cached pmc_cyc_cnt value in pmu_update_cycles
and pmc_update_overflow_timer. This leaves pmc_get_event
and pmc_is_inactive unused, so remove them.
Signed-off-by: Richard Henderson
---
target/ppc/power8-pmu.c | 107
1 fil
Hi,
This new version implements Richard's suggestions made in the
v2 review.
Changes from v2:
- Patch 1:
* fixed "PMC[1-5]" comment in target/ppc/cpu.h
- Former patch 4: squashed into patch 1
- Patch 4 (former 5):
* use boolean variables instead of uint32_t
* added Richard's r-b
- v2 link:
On Tue, Dec 28, 2021 at 10:54 AM Jim Shu wrote:
>
> It's obvious that PDMA support 64-bit access of 64-bit registers, and
> in previous commit, we confirm that PDMA support 32-bit access of both
> 32/64-bit registers. Thus, we configure 32/64-bit memory access of
> PDMA registers as valid in gener
On Tue, Dec 28, 2021 at 10:54 AM Jim Shu wrote:
>
> Real PDMA support high 32-bit read/write memory access of 64-bit
> register.
>
> The following result is PDMA tested in U-Boot on Unmatched board:
>
> 1. Real PDMA is allowed high 32-bit read/write to 64-bit register.
> => mw.l 0x300 0x0
Le 03/01/2022 à 20:31, Tõnis Tiigi a écrit :
On Mon, Jan 3, 2022 at 10:37 AM Laurent Vivier wrote:
Le 03/01/2022 à 18:07, Tõnis Tiigi a écrit :
Ping Laurent. Any suggestions for the follow-up questions?
On Thu, Dec 23, 2021 at 3:00 PM Tõnis Tiigi wrote:
On Thu, Dec 23, 2021 at 1:03 PM Lau
Move the ILE code into a separate function similarly to what we do for
AIL.
This leaves the excp_model check behind because it will go away when
we split powerpc_excp.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 23 ++-
1 file changed, 14 insertions(+), 9 del
Next patches will split powerpc_excp in multiple family specific
handlers. This patch adds a wrapper to make the transition clearer.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/ppc/excp_helper.c
(I'll alter this to use powerpc_excp_name once it is merged)
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 76
1 file changed, 7 insertions(+), 69 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 4769abfb0
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 63 +++-
1 file changed, 36 insertions(+), 27 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index c7e55800af..002a42261b 100644
--- a/target/ppc/excp_helper.c
+++ b/tar
We currently clear MSR_LE when copying bits from env->msr to
new_msr. However, for CPUs that do not have LPCR_ILE we always set
new_msr[LE] according to env->msr[LE]. And for CPUs that do have ILE
support we need to check LPCR/HID0 anyway, so there's no need to clear
the bit when copying.
Signed-o
AIL only applies for Book3s CPUs, so move it along with ILE. This
moves ILE further down in the file because the AIL function can alter
vector so we cannot move it up.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 20 ++--
1 file changed, 10 insertions(+), 10 deleti
Remove the compile time definition and make the logging be controlled
by the `-d mmu` option in the cmdline.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_he
The ppc_interrupts_little_endian function could be used for interrupts
delivered in Hypervisor mode, so add support for powernv8 and powernv9
to it.
Also drop the comment because it is inaccurate, all CPUs that can run
little endian can have interrupts in little endian. The point is
whether they c
The ppc_interrupts_little_endian function is suitable for determining
the endianness of interrupts for all Book3S CPUs.
(I'm keeping the MSR check for the rest of the CPUs, but it will go
away in the next patch.)
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 21 ++-
These are the follow up cleanups from the RFC that touch the top level
of powerpc_excp. Applies on top of the 1/n series.
Patches 1-2: extract software TLB debug into a function;
Patch 3: group the "unimplemented" messages;
Patches 4-8: move ILE code into a separate function and put ILE and
On 1/3/22 18:38, Richard Henderson wrote:
On 1/3/22 10:53 AM, Daniel Henrique Barboza wrote:
pmu_update_summaries() is not considering the case where the PMU can be
turned off (i.e. stop counting all events) if MMCR0_FC is set,
regardless of the other frozen counter bits state. This use case
On 1/3/22 10:53 AM, Daniel Henrique Barboza wrote:
MMCR0 writes will change only MMCR0 bits which are used to calculate
HFLAGS_PMCC0, HFLAGS_PMCC1 and HFLAGS_INSN_CNT hflags. No other machine
register will be changed during this operation. This means that
hreg_compute_hflags() is overkill for wha
On 1/3/22 10:53 AM, Daniel Henrique Barboza wrote:
pmu_update_summaries() is not considering the case where the PMU can be
turned off (i.e. stop counting all events) if MMCR0_FC is set,
regardless of the other frozen counter bits state. This use case was
covered in the late pmc_get_event(), via t
On 1/3/22 18:20, Cédric Le Goater wrote:
On 1/3/22 19:58, Daniel Henrique Barboza wrote:
On 1/3/22 05:21, Cédric Le Goater wrote:
Hello Daniel,
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
Hi,
This series implements pnv-phb4 user devices for the powernv9 machine.
It also includes a
On 1/3/22 10:53 AM, Daniel Henrique Barboza wrote:
+/* Composite status for PMC[1-5] enabled and counting insns or cycles. */
+uint8_t pmc_ins_cnt;
+uint8_t pmc_cyc_cnt;
I should have updated the comment to 1-6 when I added cyc_cnt.
+sel = extract64(mmcr1, MMCR1_PMC4EVT_EX
On 1/3/22 19:58, Daniel Henrique Barboza wrote:
On 1/3/22 05:21, Cédric Le Goater wrote:
Hello Daniel,
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
Hi,
This series implements pnv-phb4 user devices for the powernv9 machine.
It also includes a couple of pnv-phb3 and pnv-phb3-root-port fi
gitlab.com/rth7680/qemu.git tags/pull-misc-20220103
for you to fetch changes up to 5c23f0c3191907000bab278654570a7d5879822a:
gitlab: Disable check-python-tox (2022-01-03 08:55:55 -0800)
Fix some meson conversion breakage
Dis
On Mon, Jan 3, 2022 at 1:57 PM Philippe Mathieu-Daudé
wrote:
> On 3/1/22 21:45, Brad Smith wrote:
> > FreeBSD: Upgrade to 12.3 release
>
> Maybe some mention like:
>
> '''
> Note, since libasn1 got fixed in 12.3 [*], this commit re-enables GNUTLS.
>
> [*]
> https://gitlab.com/gnutls/libtasn1/-/me
On Mon, Jan 3, 2022 at 1:47 PM Brad Smith wrote:
> FreeBSD: Upgrade to 12.3 release
>
> Signed-off-by: Brad Smith
> Tested-by: Thomas Huth
> ---
> .gitlab-ci.d/cirrus.yml | 5 +
> tests/vm/freebsd| 8 +++-
> 2 files changed, 4 insertions(+), 9 deletions(-)
>
Reviewed-by: Warne
On 3/1/22 21:45, Brad Smith wrote:
FreeBSD: Upgrade to 12.3 release
Maybe some mention like:
'''
Note, since libasn1 got fixed in 12.3 [*], this commit re-enables GNUTLS.
[*]
https://gitlab.com/gnutls/libtasn1/-/merge_requests/71
'''
Signed-off-by: Brad Smith
Tested-by: Thomas Huth
---
On 21/12/2021 07.58, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Add a new dbus-doc directive to import D-Bus interfaces documentation
from the introspection XML. The comments annotations follow the
gtkdoc/kerneldoc style, and should be formatted with reST.
Note: I realize after
FreeBSD: Upgrade to 12.3 release
Signed-off-by: Brad Smith
Tested-by: Thomas Huth
---
.gitlab-ci.d/cirrus.yml | 5 +
tests/vm/freebsd| 8 +++-
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/.gitlab-ci.d/cirrus.yml b/.gitlab-ci.d/cirrus.yml
index d273a9e713..18ded
Hi!
"make html" and "make man" do not work anymore:
$ make help | grep -B1 html
Documentation targets:
html man - Build documentation in specified format
$ make html
GIT ui/keycodemapdb meson tests/fp/berkeley-testfloat-3
tests/fp/berkeley-softfloat-3 dtc capstone slirp
On 2/1/22 22:58, Patrick Venture wrote:
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 9 +
1 file changed, 9 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On Mon, Jan 3, 2022 at 10:37 AM Laurent Vivier wrote:
>
> Le 03/01/2022 à 18:07, Tõnis Tiigi a écrit :
> > Ping Laurent. Any suggestions for the follow-up questions?
> >
> > On Thu, Dec 23, 2021 at 3:00 PM Tõnis Tiigi wrote:
> >>
> >> On Thu, Dec 23, 2021 at 1:03 PM Laurent Vivier wrote:
> >>>
>
On 1/3/22 05:28, Cédric Le Goater wrote:
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
The TYPE_PNV_PHB3_ROOT_BUS name is used as the default bus name when
the dev has no 'id'. However, pnv-phb3-root-bus is a bit too long to be
used as a bus name.
Most common QEMU buses and PCI controlle
On 1/3/22 05:21, Cédric Le Goater wrote:
Hello Daniel,
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
Hi,
This series implements pnv-phb4 user devices for the powernv9 machine.
It also includes a couple of pnv-phb3 and pnv-phb3-root-port fixes that
were also applied for the pnv4 equivale
MMCR0 writes will change only MMCR0 bits which are used to calculate
HFLAGS_PMCC0, HFLAGS_PMCC1 and HFLAGS_INSN_CNT hflags. No other machine
register will be changed during this operation. This means that
hreg_compute_hflags() is overkill for what we need to do.
pmu_update_summaries() is already u
pmu_update_summaries() is not considering the case where the PMU can be
turned off (i.e. stop counting all events) if MMCR0_FC is set,
regardless of the other frozen counter bits state. This use case was
covered in the late pmc_get_event(), via the also gone pmc_is_inactive(),
that would return an
From: Richard Henderson
This is the combination of frozen bit and counter type, on a per
counter basis. So far this is only used by HFLAGS_INSN_CNT, but
will be used more later.
Signed-off-by: Richard Henderson
[danielhb: fixed PMC4 cyc_cnt shift and insn run latch code]
Signed-off-by: Daniel H
From: Richard Henderson
Use the cached pmc_cyc_cnt value in pmu_update_cycles
and pmc_update_overflow_timer. This leaves pmc_get_event
and pmc_is_inactive unused, so remove them.
Signed-off-by: Richard Henderson
---
target/ppc/power8-pmu.c | 107
1 fil
From: Richard Henderson
Use the cached pmc_ins_cnt value. Unroll the loop over the
different PMC counters. Treat the PMC4 run-latch specially.
Signed-off-by: Richard Henderson
---
target/ppc/power8-pmu.c | 78 ++---
1 file changed, 49 insertions(+), 29 del
Hi,
This is the v2 of Richard's work sent in [1]. The initial implementation
presented some issues with the event-based branch kernel tests that I
fixed in this new version. This code is now passing all EBB PPC64
tests, it makes Avocado happy and it's all contained in the C helper.
Last patch is
Le 03/01/2022 à 18:07, Tõnis Tiigi a écrit :
Ping Laurent. Any suggestions for the follow-up questions?
On Thu, Dec 23, 2021 at 3:00 PM Tõnis Tiigi wrote:
On Thu, Dec 23, 2021 at 1:03 PM Laurent Vivier wrote:
Le 23/12/2021 à 07:47, Tonis Tiigi a écrit :
Please copy here what you explain i
On 1/3/22 10:12 AM, Matheus K. Ferst wrote:
On 03/01/2022 14:50, Richard Henderson wrote:
On 1/3/22 8:56 AM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Handle POWERPC_EXCP_TRAP in cpu_loop to deliver SIGTRAP on tw[i]/td[i].
The si_code comes from do_program_check in the kernel s
On 1/3/22 03:46, Cédric Le Goater wrote:
On 12/23/21 21:18, Daniel Henrique Barboza wrote:
Hi,
In this version the tedious repetition was taken away from the
code by using a helper that increments the PMCs based on specified
conditions.
As far as Avocado test goes, the performance is the sa
On 03/01/2022 14:50, Richard Henderson wrote:
On 1/3/22 8:56 AM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Handle POWERPC_EXCP_TRAP in cpu_loop to deliver SIGTRAP on tw[i]/td[i].
The si_code comes from do_program_check in the kernel source file
arch/powerpc/kernel/traps.c
Signe
On 1/3/22 12:07, Alex Bennée wrote:
Daniel Henrique Barboza writes:
On 12/23/21 00:01, Richard Henderson wrote:
In contrast to Daniel's version, the code stays in power8-pmu.c,
but is better organized to not take so much overhead.
Before:
32.97% qemu-system-ppc qemu-system-ppc64
Hi Andrew,
On Mon, 03 Jan 2022 13:46:01 +,
Andrew Jones wrote:
>
> Hi Marc,
>
> On Tue, Dec 28, 2021 at 06:23:47PM +, Marc Zyngier wrote:
> > Add basic support for Pointer Authentication when running a KVM
> > guest and that the host supports it, loosely based on the SVE
> > support.
>
Add basic support for Pointer Authentication when running a KVM
guest and that the host supports it, loosely based on the SVE
support.
Although the feature is enabled by default when the host advertises
it, it is possible to disable it by setting the 'pauth=off' CPU
property. The 'pauth' comment i
On 1/3/22 8:56 AM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Now that linux-user delivers the signal on tw, we can change
signal_save_restore_xer to use SIGTRAP instead of SIGILL.
Suggested-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
tests/tcg/ppc64le/signal_save_res
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