[PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32

From: Khem Raj 5.4 is first stable API as far as rv32 is concerned see [1] [1] https://sourceware.org/git/?p=glibc.git;a=commit;h=7a55dd3fb6d2c307a002a16776be84310b9c8989 Signed-off-by: Khem Raj Reviewed-by: Alistair Francis Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Bin Meng Message-Id:

[PATCH v4 2/3] target/riscv: Fixup setting GVA

From: Alistair Francis In preperation for adding support for the illegal instruction address let's fixup the Hypervisor extension setting GVA logic and improve the variable names. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 21 ++--- 1 file changed, 6 insert

[PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr

From: Jessica Clarke The original BBL boot method had the kernel embedded as an opaque blob that was blindly jumped to, which OpenSBI implemented as fw_payload. OpenSBI then implemented fw_jump, which allows the payload to be loaded elsewhere, but still blindly jumps to a fixed address at which t

[PULL 85/88] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions

From: Frank Chang SEW has the limitation which cannot exceed ELEN. Widening instructions have a destination group with EEW = 2*SEW and narrowing instructions have a source operand with EEW = 2*SEW. Both of the instructions have the limitation of: 2*SEW <= ELEN. Signed-off-by: Frank Chang Acked

[PULL 81/88] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()

From: Frank Chang Add supports of Vector unit-stride mask load/store instructions (vlm.v, vsm.v), which has: evl (effective vector length) = ceil(env->vl / 8). The new instructions operate the same as unmasked byte loads and stores. Add evl parameter to reuse vext_ldst_us(). Signed-off-by:

[PULL 59/88] target/riscv: rvv-1.0: floating-point slide instructions

From: Frank Chang Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-52-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 7 ++ tar

Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores

On Thu, Dec 16, 2021 at 6:18 PM Philippe Mathieu-Daudé wrote: > > On 12/16/21 06:58, Anup Patel wrote: > > On Thu, Dec 16, 2021 at 10:27 AM Alistair Francis > > wrote: > >> > >> From: Alistair Francis > >> > >> Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so > >> let's set th

[PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-58-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 6 -- target/riscv/insn32.decode | 2 -- target/riscv/vector_

[PULL 83/88] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-76-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 ++-- target/riscv/insn32.decode | 4 ++-- target/riscv/vector_h

[PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert

From: Frank Chang Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-65-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 22 - target/riscv/insn32.decode | 15 --- target/riscv/v

[PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-57-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 22 --- target/riscv/insn32.decode | 7 - target/riscv/vector_

[PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns

From: Frank Chang Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-75-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 4 +++ target/riscv/vector_helpe

[PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions

From: Frank Chang log(SEW) truncate vssra.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-56-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- 1 file changed, 2 inserti

[PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-55-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/targ

[PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions

From: Frank Chang Sign-extend vsaddu.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-47-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+),

[PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-66-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/vector_helper.c| 2 +- target/riscv/insn_trans/t

[PULL 68/88] target/riscv: introduce floating-point rounding mode enum

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-61-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/internals.h| 9 + target/riscv/fpu_helper.c | 12 ++-- targe

[PULL 49/88] target/riscv: rvv-1.0: single-width averaging add and subtract instructions

From: Frank Chang Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-42-frank.ch...@sifive.com> Signed-off-by: Alistair Franc

[PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction

From: Frank Chang Implement the floating-point reciprocal square-root estimate to 7 bits instruction. Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-70-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h

[PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-60-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --gi

[PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-53-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +++--- target/r

[PULL 84/88] target/riscv: rvv-1.0: update opivv_vadc_check() comment

From: Frank Chang Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is moved to Section 11.4 in RVV v1.0 spec. Update the comment, no functional changes. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-77-frank.ch...@sifive.com> Signed

[PULL 48/88] target/riscv: rvv-1.0: integer extension instructions

From: Frank Chang Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-41-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/h

[PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11

From: Frank Chang Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-72-frank.ch...@sifive.com> Signed-off-by: Alistair Franc

[PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-59-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_rvv.c.inc | 23 --- 2

[PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions

From: Vineet Gupta The bitmanip extension has now been ratified [1] and upstream tooling (gcc/binutils) support it too, so move them out of experimental and also enable by default (for better test exposure/coverage) [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions Signed-off

[PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-38-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 16

[PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-54-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c| 12 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 12 +--- 2

[PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-73-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.c.inc | 27 +

[PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended

From: Frank Chang For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-35-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- t

[PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-49-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 9 - 1 file changed, 9 deletions(-) diff --git a/target/riscv/vector_helper.c b/

[PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-50-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c| 4 target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 2 files changed, 2 in

[PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction

From: Frank Chang Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-71-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 + ta

[PULL 40/88] target/riscv: rvv-1.0: iota instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-33-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc

[PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-45-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 24 +++--- target/riscv/insn32.decode | 12 +++ targe

[PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions

From: Frank Chang * Sign-extend vmselu.vi and vmsgtu.vi immediate values. * Remove "set tail elements to zeros" as tail elements can be unchanged for either VTA to have undisturbed or agnostic setting. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.2395

[PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-69-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 2

[PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-31-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode |

[PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-39-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/internals.h| 5 t

[PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid

From: Frank Chang If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check and trig

[PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-46-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32

[PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-30-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode |

[PULL 41/88] target/riscv: rvv-1.0: element index instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-34-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --

[PULL 58/88] target/riscv: rvv-1.0: slide instructions

From: Frank Chang * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-51-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_help

[PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-26-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c| 99 ++--- target/riscv/insn_trans/trans_rvv.c.inc | 32

[PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-28-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --

[PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions

From: Frank Chang Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-43-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 6 +++

[PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow

From: Frank Chang * Only do carry-in or borrow-in if is masked (vm=0). * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-44-frank.ch...@sifive.com> Signed-off

[PULL 31/88] target/riscv: rvv-1.0: fault-only-first unit stride load

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-24-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 26 ++--- target/riscv/insn32.decode

[PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation

From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-27-frank.ch...@sifive.com> Signed-off-by: Alistair Francis ---

[PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions

From: Frank Chang * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20211210075704.23951-37-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv

[PULL 47/88] target/riscv: rvv-1.0: whole register move instructions

From: Frank Chang Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-40-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 4

[PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-23-frank.ch...@sifive.com> Signed

[PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-32-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 6 +++--- target/riscv/vector_helper.c

[PULL 29/88] target/riscv: rvv-1.0: index load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-22-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 67 +++ target/riscv/insn32.decode | 21 +++-- targe

[PULL 43/88] target/riscv: rvv-1.0: register gather instructions

From: Frank Chang * Add vrgatherei16.vv instruction. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-36-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 target/riscv/insn32.decode

[PULL 24/88] target/riscv: introduce more imm value modes in translator functions

From: Frank Chang Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW)

[PULL 28/88] target/riscv: rvv-1.0: stride load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-21-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 129 ++-- target/riscv/insn32.decode | 43 ++- target/riscv/v

[PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations

From: Frank Chang As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-13-frank.ch...@sifive.com> Signed-off-by:

[PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-29-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --

[PULL 23/88] target/riscv: rvv-1.0: update check functions

From: Frank Chang Update check functions with RVV 1.0 rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-16-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 715 +--- 1 fil

[PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions

From: Frank Chang Vector AMOs are removed from standard vector extensions. Will be added later as separate Zvamo extension, but will need a different encoding from earlier proposal. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-19-frank.ch...@sifive

[PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status

From: Frank Chang Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-8-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 +- target/riscv/c

[PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-12-frank.ch...@sifive.com> Signed-off-by: Alistair Fran

[PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function

From: Frank Chang * Add fp16 nan-box check generator function, if a 16-bit input is not properly nanboxed, then the input is replaced with the default qnan. * Add do_nanbox() helper function to utilize gen_check_nanbox_X() to generate the NaN-boxed floating-point values based on SEW setting.

[PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions

From: Frank Chang Add the following instructions: * vlre.v * vsr.v Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-25-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 21 target/riscv/in

[PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers

From: Frank Chang * Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. * Remove RVV loose check in fs() predicate function. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-9-f

[PULL 18/88] target/riscv: rvv-1.0: add vlenb register

From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-11-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7

[PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-6-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2

[PULL 27/88] target/riscv: rvv-1.0: configure instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-20-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c| 14 +- target/riscv/insn_trans/trans_rvv.c.

[PULL 17/88] target/riscv: rvv-1.0: add vcsr register

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-10-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c |

[PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL

From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600) and MSTATUS_FS (0x6000) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by:

[PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-4-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h |

[PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-5-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/csr.c

[PULL 08/88] target/riscv: zfh: add Zfhmin cpu property

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-9-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0f808a5b

[PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field

From: Frank Chang Implementations may have a writable misa.v field. Analogous to the way in which the floating-point unit is handled, the mstatus.vs field may exist even if misa.v is clear. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20

[PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-3-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff -

[PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-Id: <20211210075704.23951-2-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 16 ---

[PULL 03/88] target/riscv: zfh: half-precision convert and move

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-id: 20211210074329.5775-4-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/helper.h

[PULL 07/88] target/riscv: zfh: implement zfhmin extension

From: Frank Chang Zfhmin extension is a subset of Zfh extension, consisting only of data transfer and conversion instructions. If enabled, only the following instructions from Zfh extension are included: * flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s * If D extension is present: fcvt.d.h,

[PULL 04/88] target/riscv: zfh: half-precision floating-point compare

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-5-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/helper.h

[PULL 06/88] target/riscv: zfh: add Zfh cpu property

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-7-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8129981

[PULL 02/88] target/riscv: zfh: half-precision computational

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-3-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/helper.h

[PULL 05/88] target/riscv: zfh: half-precision floating-point classify

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-6-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/helper.h

[PULL 01/88] target/riscv: zfh: half-precision load and store

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-id: 20211210074329.5775-2-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 1 + target/riscv/insn3

[PULL 00/88] riscv-to-apply queue

From: Alistair Francis The following changes since commit 212a33d3b0c65ae2583bb1d06cb140cd0890894c: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2021-12-19 16:36:10 -0800) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-ri

Re: [PULL 00/16] Misc patches for 2021-12-20

On 12/19/21 6:16 AM, Paolo Bonzini wrote: The following changes since commit 90978e15bc9a23c208b25bf7ea697a5d0925562b: Merge tag 'trivial-branch-for-7.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2021-12-17 13:15:38 -0800) are available in the Git repository at:

Virtio-GPU Xres and Yres seettings

Hi Team, I am working on a Virtio-GPU device (backend) for one of our customer projects - we are using the Virtio-GPU driver (frontend) to drive our device. Our device code has been written using Qemu virtio-gpu device code as a reference. Our device is setting the resolution to 1024x768 as a resp

Re: [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default

On Thu, Dec 16, 2021 at 12:55 PM Alistair Francis wrote: > > From: Alistair Francis > > Let's enable the Hypervisor extension by default. This doesn't affect > named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the > Hypervisor extensions by default for the virt machine. > > Signed-o

Re: [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental

On Thu, Dec 16, 2021 at 12:55 PM Alistair Francis wrote: > > From: Alistair Francis > > The Hypervisor spec is now frozen, so remove the experimental tag. > > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin M

Re: [RFC] vhost-vdpa-net: add vhost-vdpa-net host device support

On Fri, Dec 17, 2021 at 4:35 PM Stefan Hajnoczi wrote: > > On Fri, Dec 17, 2021 at 12:26:53PM +0800, Jason Wang wrote: > > Dave: You created the VIRTIO vmstate infrastructure in QEMU. Please see > the bottom of this email about moving to a standard VIRTIO device > save/load format defined by the V

Re: [PATCH v2 5/5] hw/input/pckbd: Open-code i8042_setup_a20_line() wrapper

On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote: Since the named GPIO lines are a "public" interface to the device, we can directly call qdev_connect_gpio_out_named(), making it consistent with how the other A20 input source (port92) is wired. Suggested-by: Peter Maydell Signed-off-by: Phil

Re: [PATCH v2 3/5] hw/qdev: Correct qdev_connect_gpio_out_named() documentation

On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote: qdev_connect_gpio_out_named() is described as qdev_connect_gpio_out(), and referring to itself in an endless loop, which is confusing. Fix. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 5 +++-- 1 file changed, 3 inser

Re: [PATCH v2 2/5] hw/qdev: Correct qdev_init_gpio_out_named() documentation

On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote: qdev_init_gpio_out_named() is described as qdev_init_gpio_out(), and referring to itself in an endless loop, which is confusing. Fix. Reported-by: Yanan Wang Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 2 +- 1 file

Re: [PATCH v2 1/5] hw/qdev: Cosmetic around documentation

On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote: Add empty lines to have a clearer distinction between different functions declarations. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 11 +++ 1 file changed, 11 insertions(+) Reviewed-by: Yanan Wang Thanks,

[PATCH 2/2] net/colo-compare.c: Update the default value comments

Make the comments consistent with the REGULAR_PACKET_CHECK_MS. Signed-off-by: Zhang Chen --- net/colo-compare.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/colo-compare.c b/net/colo-compare.c index 216de5a12b..62554b5b3c 100644 --- a/net/colo-compare.c +++ b/net/colo-

[PATCH 1/2] net/colo-compare.c: Optimize compare order for performance

COLO-compare use the glib function g_queue_find_custom to dump another VM's networking packet to compare. But this function always start find from the queue->head(here is the newest packet), It will reduce the success rate of comparison. So this patch reversed the order of the queues for performanc

[PATCH] hw/nvram: at24 return 0xff if 1 byte address

The at24 eeproms are 2 byte devices that return 0xff when they are read from with a partial (1-byte) address written. This distinction was found comparing model behavior to real hardware testing. Tested: `i2ctransfer -f -y 45 w1@85 0 r1` returns 0xff instead of next byte Signed-off-by: Patrick V

Re: [PATCH v2] audio: Add sndio backend

Hi Alexandre, sndio is the native API used by OpenBSD, although it has been ported to other *BSD's and Linux (packages for Ubuntu, Debian, Void, Arch, etc.). Signed-off-by: Brad Smith Signed-off-by: Alexandre Ratchov --- Thank you for the reviews and all the comments. Here's a second diff with

Re: [PATCH] linux-user/signal: Map exit signals in SIGCHLD siginfo_t

Well, the original fix 1c3dfb506ea3 did clearly improve things for me, but it wasn't complete yet. At some point I gave up on finding a minimal reproducer for my remaining problems (futex-related hangs in a complex python+bash app). So, this *may* be the missing piece. Will test, but that take

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