On 16/12/2021 17.38, Richard Henderson wrote:
On 12/16/21 1:44 AM, Thomas Huth wrote:
Hi!
The following changes since commit e630bc7ec9dda656a452ed28cac4d1e9ed605d71:
Merge tag 'pull-block-2021-12-15' of git://repo.or.cz/qemu/armbru into
staging (2021-12-15 12:14:44 -0800)
are availabl
17.12.2021 00:10, John Snow wrote:
On Thu, Dec 16, 2021 at 6:41 AM Vladimir Sementsov-Ogievskiy mailto:vsement...@virtuozzo.com>> wrote:
15.12.2021 22:39, John Snow wrote:
> Now that we are fully switched over to the new QMP library, move it back
> over the old namespace. This is
Hi,
> I have rebased the series and added your acked-by (
> https://gitlab.com/marcandre.lureau/qemu/-/tree/dbus)
>
> The client side is still in development. However, the libvirt series is in
> shape (
> https://patchew.org/Libvirt/20211202142411.1718032-1-marcandre.lur...@redhat.com/),
> wait
Thanks Alex. It seems this patch sets and checks if the destination device is
busy. But how about the data transfers not triggered directly by PMIO/MMIO
handlers? For example:
1. Device A Timer's callback -> Device A MMIO handler
2. Device A BH's callback -> Device A MMIO handler
In these situa
On Thu, Dec 16, 2021 at 06:10:40PM -0500, Annie.li wrote:
> Hello Gerd,
>
> On 12/16/2021 1:11 AM, Gerd Hoffmann wrote:
> >
> > Looking again, the difference is probably the reset handling.
> > pcie_cap_slot_reset() will turn on power (via PCI_EXP_SLTCTL_PCC) in
> > case some device is plugged in
On Tue, Dec 14, 2021 at 1:25 PM Jessica Clarke wrote:
>
> The original BBL boot method had the kernel embedded as an opaque blob
> that was blindly jumped to, which OpenSBI implemented as fw_payload.
> OpenSBI then implemented fw_jump, which allows the payload to be loaded
> elsewhere, but still b
On Sat, Dec 11, 2021 at 2:26 PM Anup Patel wrote:
>
> The AIA specification adds new CSRs for RV32 so that RISC-V hart can
> support 64 local interrupts on both RV32 and RV64.
>
> Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h| 14 +-
> t
On Tue, Dec 14, 2021 at 1:25 PM Jessica Clarke wrote:
>
> The original BBL boot method had the kernel embedded as an opaque blob
> that was blindly jumped to, which OpenSBI implemented as fw_payload.
> OpenSBI then implemented fw_jump, which allows the payload to be loaded
> elsewhere, but still b
On Thu, Dec 16, 2021 at 3:21 PM Vineet Gupta wrote:
>
> The bitmanip extension has now been ratified [1] and upstream tooling
> (gcc/binutils) support it too, so move them out of experimental and also
> enable by default (for better test exposure/coverage)
>
> [1] https://wiki.riscv.org/display/TE
On Thu, Dec 16, 2021 at 5:33 PM Khem Raj wrote:
>
> 5.4 is first stable API as far as rv32 is concerned see [1]
>
> [1]
> https://sourceware.org/git/?p=glibc.git;a=commit;h=7a55dd3fb6d2c307a002a16776be84310b9c8989
>
> Signed-off-by: Khem Raj
> Cc: Palmer Dabbelt
> Cc: Alistair Francis
> Cc: Bi
On Thu, Dec 16, 2021 at 5:10 PM Stefan Hajnoczi wrote:
>
> On Thu, Dec 16, 2021 at 11:01:40AM +0800, Jason Wang wrote:
> > On Wed, Dec 15, 2021 at 6:07 PM Stefan Hajnoczi wrote:
> > >
> > > On Wed, Dec 15, 2021 at 11:18:05AM +0800, Jason Wang wrote:
> > > > On Tue, Dec 14, 2021 at 9:11 PM Stefan
On Sat, Dec 11, 2021 at 2:23 PM Anup Patel wrote:
>
> The AIA hvictl and hviprioX CSRs allow hypervisor to control
> interrupts visible at VS-level. This patch implements AIA hvictl
> and hviprioX CSRs.
>
> Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv
On Thu, Dec 16, 2021 at 3:21 PM Vineet Gupta wrote:
>
> The bitmanip extension has now been ratified [1] and upstream tooling
> (gcc/binutils) support it too, so move them out of experimental and also
> enable by default (for better test exposure/coverage)
>
> [1] https://wiki.riscv.org/display/TE
Here's my shot at fixing dma-reentracy issues. This patch adds a flag to
the DeviceState, which is set/checked when we call an accessor
associated with the device's IO MRs.
The problem, in short, as I understand it: For the vast majority of
cases, we want to prevent a device from accessing it's ow
On 2021/11/23 下午5:09, LIU Zhiwei wrote:
Only the pmp index that be checked by pmp_hart_has_privs can be used
by pmp_get_tlb_size to avoid an error pmp index.
Before modification, we may use an error pmp index. For example,
we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs. If ther
Only the pmp index that be checked by pmp_hart_has_privs can be used
by pmp_get_tlb_size to avoid an error pmp index.
Before modification, we may use an error pmp index. For example,
we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs. If there
is an pmp rule, valid range is [0x4fc, 0x5
On Sat, Dec 11, 2021 at 2:26 PM Anup Patel wrote:
>
> The AIA device emulation (such as AIA IMSIC) should be able to set
> (or provide) AIA ireg read-modify-write callback for each privilege
> level of a RISC-V HART.
>
> Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Alistair
> ---
>
On Sat, Dec 11, 2021 at 2:27 PM Anup Patel wrote:
>
> The AIA spec defines programmable 8-bit priority for each local interrupt
> at M-level, S-level and VS-level so we extend local interrupt processing
> to consider AIA interrupt priorities. The AIA CSRs which help software
> configure local inte
> On Dec 16, 2021, at 5:39 AM, Stefan Hajnoczi wrote:
>
> On Wed, Dec 15, 2021 at 10:35:30AM -0500, Jagannathan Raman wrote:
>> @@ -150,6 +157,38 @@ static void vfu_object_init_ctx(VfuObject *o, Error
>> **errp)
>> +o->pci_dev = PCI_DEVICE(dev);
> ...
>> @@ -190,6 +229,8 @@ static void vf
On 2021/12/17 上午8:37, Alistair Francis wrote:
On Wed, Dec 8, 2021 at 1:23 PM Alistair Francis wrote:
On Tue, Nov 23, 2021 at 7:09 PM LIU Zhiwei wrote:
Only the pmp index that be checked by pmp_hart_has_privs can be used
by pmp_get_tlb_size to avoid an error pmp index.
Before modification,
With qemu.qmp gone, we'll need to install it to the Pipenv so that those
tests pass.
Important; if this still fails, check that you don't have any stale
files in python/qemu/qmp/ which could interfere with this process.
Signed-off-by: John Snow
---
python/Pipfile.lock | 18 +-
1
Create a venv automatically when running iotests and install the QEMU
namespace package to it, which will also pull in qemu.qmp from PyPI.
The venv created will always use the same python binary as the one used
to launch the check process. Assuming that care is taken to run 'check'
with the python
> On Dec 16, 2021, at 4:58 AM, Stefan Hajnoczi wrote:
>
> On Wed, Dec 15, 2021 at 10:35:28AM -0500, Jagannathan Raman wrote:
>> +static void vfu_object_set_socket(Object *obj, Visitor *v, const char *name,
>> + void *opaque, Error **errp)
>> +{
>> +VfuObject
qemu.qmp can be found via the package index now. Direct the user to just
install the package. When utilities from 'qemu' are needed, direct the
user to install the package from that directory instead, which will pull
in the 'qemu.qmp' package as a dependency.
Signed-off-by: John Snow
---
scripts
The text here is slightly different than the text in other forwarder
stubs in this directory, because the only dependency needed here is
outside of the QEMU source tree entirely.
Signed-off-by: John Snow
---
scripts/qmp/qmp-shell | 39 ++-
1 file changed, 34 i
A forthcoming commit that deletes python/qemu/qmp and begins using the
dependency from PyPI instead changes the way older versions of isort
process import priorities. Sticking to isort versions newer than 5.6.0
keep us consistent with the bleeding edge of isort releases.
Signed-off-by: John Snow
The text for each forwarder is largely the same, though the qom-fuse
stub instructs users to install the optional fuse dependency for the
qemu package.
Signed-off-by: John Snow
---
scripts/qmp/qemu-ga-client | 40 -
scripts/qmp/qom-fuse | 40
A forthcoming commit makes use of the 'venv' package inside of
iotests.py, which only has stubs available in the version of typeshed
bundled with mypy 0.780 or greater, which increases our minimum
dependency from 0.770.
Signed-off-by: John Snow
---
python/Pipfile.lock | 64 ++
It's been stubbed out for quite some time and nobody yelped, so out it
goes.
Signed-off-by: John Snow
---
scripts/qmp/qmp | 11 ---
1 file changed, 11 deletions(-)
delete mode 100755 scripts/qmp/qmp
diff --git a/scripts/qmp/qmp b/scripts/qmp/qmp
deleted file mode 100755
index 0f12307c8
Based-on: <20211215193939.3768033-1-js...@redhat.com>
Hi, this series is part of an effort to publish the qemu.qmp package on
PyPI. It is the last of three series to complete this work:
(1) Switch the new Async QMP library in to python/qemu/qmp
(2) Fork python/qemu/qmp out into its own re
> On Dec 16, 2021, at 4:33 AM, Stefan Hajnoczi wrote:
>
> On Wed, Dec 15, 2021 at 10:35:28AM -0500, Jagannathan Raman wrote:
>> diff --git a/qapi/qom.json b/qapi/qom.json
>> index ccd1167808..6001a9b8f0 100644
>> --- a/qapi/qom.json
>> +++ b/qapi/qom.json
>> @@ -703,6 +703,20 @@
>> { 'struct':
On Sat, Dec 11, 2021 at 2:22 PM Anup Patel wrote:
>
> The RISC-V AIA specification extends RISC-V local interrupts and
> introduces new CSRs. This patch adds defines for the new AIA CSRs.
>
> Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_bits.h | 1
On Thu, Dec 16, 2021 at 5:33 PM Khem Raj wrote:
>
> 5.4 is first stable API as far as rv32 is concerned see [1]
>
> [1]
> https://sourceware.org/git/?p=glibc.git;a=commit;h=7a55dd3fb6d2c307a002a16776be84310b9c8989
>
> Signed-off-by: Khem Raj
> Cc: Palmer Dabbelt
> Cc: Alistair Francis
> Cc: Bi
On Wed, Dec 8, 2021 at 1:23 PM Alistair Francis wrote:
>
> On Tue, Nov 23, 2021 at 7:09 PM LIU Zhiwei wrote:
> >
> > Only the pmp index that be checked by pmp_hart_has_privs can be used
> > by pmp_get_tlb_size to avoid an error pmp index.
> >
> > Before modification, we may use an error pmp index
On Fri, Dec 10, 2021 at 3:15 PM Vladimir Sementsov-Ogievskiy <
vsement...@virtuozzo.com> wrote:
> A lot of Optional[] types doesn't make code beautiful.
> test_field_width defaults to 8, but that is never used in the code.
>
> More over, if we want some default behavior for single call of
> test_r
On Thu, Dec 16, 2021 at 5:48 AM Daniel P. Berrangé
wrote:
> On Wed, Dec 15, 2021 at 04:06:27PM -0500, John Snow wrote:
> > Signed-off-by: John Snow
> > ---
> > Makefile | 32
> > 1 file changed, 32 insertions(+)
> >
> > diff --git a/Makefile b/Makefile
> > index
Looks OK at a very quick glance. Very weak ACK from me.
On Thu, Dec 16, 2021 at 7:36 AM Philippe Mathieu-Daudé
wrote:
> This is the continuation of part 1 (dma_memory API):
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg820359.html
>
> This series update the dma_buf API.
>
> Based on "h
Hello Gerd,
On 12/16/2021 1:11 AM, Gerd Hoffmann wrote:
Hi,
Maybe we should just not set DeviceState->hotplugged = true for devices
added in VM_STATE_PRELAUNCH? It's not actual hotplug (i.e. device added
while the system is running) after all ...
Simply not setting "DeviceState->hotplugge
On Thu, Dec 16, 2021 at 6:41 AM Vladimir Sementsov-Ogievskiy <
vsement...@virtuozzo.com> wrote:
> 15.12.2021 22:39, John Snow wrote:
> > Now that we are fully switched over to the new QMP library, move it back
> > over the old namespace. This is being done primarily so that we may
> > upload this
Hi
On Wed, Oct 13, 2021 at 9:23 AM Gerd Hoffmann wrote:
> On Sun, Oct 10, 2021 at 01:08:01AM +0400, marcandre.lur...@redhat.com
> wrote:
> > From: Marc-André Lureau
> >
> > Hi,
> >
> > Both Spice and VNC are relatively complex and inefficient for local-only
> > display/console export.
> >
> > T
If I won't make that change it gives me immediate error as follows:
Taking exception 18 [v7M INVSTATE UsageFault]
...BusFault with BFSR.STKERR
...taking pending nonsecure exception 3
qemu: fatal: Lockup: can't take terminal derived exception (original
exception priority -1)
BR.
Abhijeet.
On Thu,
This change will help us move the mapping of XSCOM regions under the
PHB3 realize routine, which will be necessary for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-3-...@kaod.org>
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
The routine pnv_pec_phb_offset() is a bit complex but it also prepares
ground for PHB5 w
When -nodefaults is supported for PHB4 devices, the pecs array under
the chip will be empty. This will break the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PEC PHB4 devices
instead.
Signed-off-by: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20
From: Daniel Henrique Barboza
Calling pmu_update_cycles() on every PMC read/write operation ensures
that the values being fetched are up to date with the current PMU state.
In theory we can get away by just trapping PMCs reads, but we're going
to trap PMC writes to deal with counter overflow log
From: Daniel Henrique Barboza
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
This change will help us providing support for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-6-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3_pbcq.c | 11 +
On 16/12/2021 18:09, Daniel P. Berrangé wrote:
> On Thu, Dec 16, 2021 at 12:38:34PM +0200, Dov Murik wrote:
>>
>>
>> On 14/12/2021 20:39, Daniel P. Berrangé wrote:
>>> On Tue, Dec 14, 2021 at 01:59:10PM +, Dov Murik wrote:
Add a section explaining how the Guest Owner should calculate th
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20211213120958.24443-5-victor.colo...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode| 4
target/ppc/fpu_he
> On Dec 16, 2021, at 4:55 AM, Stefan Hajnoczi wrote:
>
> On Wed, Dec 15, 2021 at 10:35:29AM -0500, Jagannathan Raman wrote:
>> +static void vfu_object_init_ctx(VfuObject *o, Error **errp)
>> +{
>> +ERRP_GUARD();
>> +
>> +if (o->vfu_ctx || !o->socket || !o->device ||
>> +!p
From: Victor Colombo
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using
vector registers when they should be using VSX ones. This happens
because the instructions are using GEN_VSX_HELPER_R3, which adds 32
to the register numbers, effectively making them vector registers.
This
On Thu, Dec 16, 2021 at 5:58 AM Vladimir Sementsov-Ogievskiy <
vsement...@virtuozzo.com> wrote:
> 15.12.2021 22:39, John Snow wrote:
> > Creating an instance of qemu.aqmp.ExecuteError is too involved here, so
> > just drop the specificity down to a generic AQMPError.
>
> s/AQMPError/QMPError/ ?
>
From: Fabiano Rosas
This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2.
It breaks the --disable-tcg build:
../target/ppc/excp_helper.c:463:29: error: implicit declaration of
function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration]
We should not have TCG code in powerpc_excp
It is currently impossible to find a "ppc405_rom.bin" firmware file or
a full flash image for the PPC405EP evalution board. Even if it should
be technically possible to recreate such an image, it's unlikely that
anyone will do it since the board is obsolete and support in QEMU has
been broken for a
This is not useful and will be in the way for support of user created
PHB4 devices.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-13-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pe
From: Richard Henderson
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 256, but perform the
operation with float64r32_div for consistency.
Use float_flag_invalid_snan instead of recomputing the
snan-ness of the operand.
Signed-off-by: Richard
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribute represents better the logic units of the
POWER9 c
From: Fabiano Rosas
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447 and 7447a)*
We have since 2011 [1] been unable to run OpenBIOS in the 7450s and
have not heard of any other software that is used with those CPUs in
QEMU. A current discussion [2] shows that the 7450 software TLB is
unsuppo
When -nodefaults is supported for PHB3 devices, the phbs array under
the chip will be empty. This will break the XICSFabric handlers, and
all interrupt delivery, and the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PHB3 devices instead.
Signed-off-by: Cédric Le Goater
From: Fabiano Rosas
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448)
The QEMU-side software TLB implementation for the 7450 family of CPUs
is being removed due to lack of known users in the real world. The
last users in the code were removed by the two previous commits.
A b
And check the PEC index using the chip class.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-10-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_p
From: Richard Henderson
Now that vxsqrt and vxsnan are computed directly by softfloat,
we don't need to recompute it. Split out float_invalid_op_sqrt
to be used in several places. This fixes VSX_SQRT, which did
not order its tests correctly to eliminate NaN with sign set.
Signed-off-by: Richar
I made some changes to the code in qemu :
https://github.com/qemu/qemu/blob/stable-6.0/target/arm/cpu.c#L339 . I have
commented out the variable vecbase and directly given the address of my
vector address(not zero) or where they are located in our binary file. Is
that a problem?
BR.
Abhijeet.
On
> On Dec 15, 2021, at 5:04 PM, Beraldo Leal wrote:
>
> On Wed, Dec 15, 2021 at 10:35:26AM -0500, Jagannathan Raman wrote:
>> Specify target VM for exec_command and
>> exec_command_and_wait_for_pattern routines
>>
>> Signed-off-by: Elena Ufimtseva
>> Signed-off-by: John G Johnson
>> Signed-o
From: Daniel Henrique Barboza
This patch starts an IBM Power8+ compatible PMU implementation by adding
the representation of PMU events that we are going to sample,
PMUEventType. This enum represents a Perf event that is being sampled by
a specific counter 'sprn'. Events that aren't available (i.
From: Richard Henderson
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-27-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 21 -
From: Daniel Henrique Barboza
MMCR1 determines the events to be sampled by the PMU. Updating the
counters at every MMCR1 write ensures that we're not sampling more
or less events by looking only at MMCR0 and the PMCs.
It is worth noticing that both the Book3S PowerPC PMU, and this IBM
Power8+ PM
From: Fabiano Rosas
When Altivec support was added to the e6500 kernel in 2012[1], the
QEMU code was not changed, so we don't register the VPU/VPUA
exceptions for the e6500:
qemu: fatal: Raised an exception without defined vector 73
Note that the error message says 73, instead of 32, which is
From: Victor Colombo
Reviewed-by: Richard Henderson
Signed-off-by: Victor Colombo
Message-Id: <20211213120958.24443-3-victor.colo...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 17 +---
target/ppc/translate/vsx-impl.c.inc | 30 +++
From: Richard Henderson
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 32, but perform the
operation with float64r32_div for consistency.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-33-richard.hender...@linaro.org>
Signe
This change will help us providing support for user created PHB4
devices.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-14-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 34 ++-
From: Richard Henderson
Use float64r32_sqrt. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-30-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc
The board information for the 405EP first appeared in commit 04f20795ac81
("Move PowerPC 405 specific definitions into a separate file ...")
An Ethernet address is a 6 byte number. Fix that.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211206103712.1866296-1
Each PEC device of the POWER9 chip has a predefined number of stacks,
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove the
"num-stacks" property.
Reviewed-by: Daniel Henrique Barboza
Reviewed-b
From: Daniel Henrique Barboza
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions (Perf
event PM_INST_CMPL) by counting the amou
QEMU installs a custom U-Boot in-memory descriptor to share board
information with Linux, which means that the QEMU machine was
initially designed to support booting Linux directly without using the
loaded FW. But, it's not that simple because the CPU still starts at
address 0xfffc where nothin
From: Richard Henderson
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-23-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 13 -
1 file
It prepares ground for PHB5 which has different values.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-9-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/p
From: Fabiano Rosas
The exception model id for 601v has been removed without mention
why. I assume it was inadvertent and restore it here.
Fixes: b632a148b6 ("target-ppc: Use QOM method dispatch for MMU fault handling")
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: C
From: Daniel Henrique Barboza
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x8000) a performance monitor alert wi
It is never used.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-5-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.
From: Richard Henderson
Calling helper_frsp directly from other helpers generates
the incorrect retaddr. Split out a helper that takes the
retaddr as a parameter.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-22-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
From: Matheus Ferst
This instruction has VRT and VRB fields instead of T/TX and B/BX.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20211213120958.24443-4-victor.colo...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/translate/vsx-impl.c.inc | 5 ++
From: Fabiano Rosas
The Floating-point Unavailable and Decrementer interrupts are being
registered at the same 0x900 address. The FPU should be at 0x800
instead.
Verified on MPC555, MPC860 and MPC885 user manuals.
Reported-by: BALATON Zoltan
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard H
From: Richard Henderson
We were returning nanval for any instance of invalid being set,
but that is an incorrect for VXCVI. This failure can be seen
in the float_convs tests.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-14-richard.hender...@linaro.org>
Signed-off-by: Cédr
From: Daniel Henrique Barboza
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occur
The maximum number of PHB3 devices per chip can be different depending
on the POWER8 processor model.
Signed-off-by: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20211213132830.108372-4-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3.c | 2 +-
1 fil
These values are computed and updated by U-Boot at startup. Use them
as defaults to improve direct Linux boot.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-13-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_uc.c | 6 +++---
1 file changed, 3 insertions(+),
From: Richard Henderson
When computing the predicate "is this value currently formatted
for single precision", we do not want to round the value according
to the current rounding mode, nor perform a floating-point equality.
We want to see if the N bits that make up single-precision are the
only o
From: Richard Henderson
Use float64r32_{add,sub,div}. Fixes a double-rounding issue with
performing the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-31-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
t
From: Richard Henderson
We only needed one ieee arithmetic operation to raise
exceptions. To convert back to register form, we can
use our simpler non-arithmetic function.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-24-richard.hender...@linaro.org>
Signed-off-by: Cédric
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=100\0"
"fdt_addr_r=180\0"
"ramdisk_addr_r=190\0"
The taihu is one of these boards, the ref405ep is not but we don't
have much information on it and both
This routine is a small helper to cleanup the code. The update of the
flash fields were removed because there are not of any use when booting
from a Linux kernel image. It should be functionally equivalent.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-11-...@kaod.org>
Signe
From: Daniel Henrique Barboza
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x8000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being
From: Richard Henderson
Fixes a bug in which e.g XE enabled causes inexact to be raised
before the writeback to the architectural register.
All of the users of GEN_FLOAT_B either set set_fprf, or are one
of the convert-to-integer instructions that require this behaviour.
Split out the two gen_he
From: Fabiano Rosas
The e600 CPU is a successor of the 7448 and like all the 7450s CPUs,
it has an optional software TLB feature.
We have determined that there is no OS software support for the 7450
software TLB available these days. See the previous commit for more
information.
This patch disa
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211206103712.1866296-4-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc.c| 2 ++
hw/ppc/trace-events | 3 +++
2 files changed, 5 insertions(+)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index e
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211206103712.1866296-8-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 7 +++
hw/ppc/ppc405_boards.c | 16 +++-
2 files changed, 14 insertions(+), 9 deletions(-)
diff
From: Richard Henderson
Now that vxidi, vxzdz, and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-11-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helpe
Adapt the fields offset in the board information for Linux. Since
Linux relies on the CPU frequency value, I wonder how it ever worked.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-15-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_uc.c | 9 +
1 fi
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