5.4 is first stable API as far as rv32 is concerned see [1]
[1]
https://sourceware.org/git/?p=glibc.git;a=commit;h=7a55dd3fb6d2c307a002a16776be84310b9c8989
Signed-off-by: Khem Raj
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Bin Meng
---
linux-user/riscv/target_syscall.h | 3 ++-
1 file chan
..and I've just realized that I left the processor id as C0F instead of C05
again.
I also removed the generic timer as I don't think the A5 has one.
On Thu, Dec 16, 2021 at 12:48 AM Byron Lathi wrote:
> Add support for the Cortex-A5. These changes are based off of the A7 and
> A9 Init functions,
Fails testing:
/home/gitlab-runner/builds/yKcZqVC9/0/qemu-project/qemu/docs/specs/ppc-spapr-hcalls.rst:101:Block
quote ends without a blank line; unexpected unindent.
I didn't see it under :
https://gitlab.com/legoater/qemu/-/pipelines/429852244
Is the job being run by default ?
It's ce
Add support for the Cortex-A5. These changes are based off of the A7 and
A9 Init functions, using the appropriate values from the technical
reference manual for the A5.
Signed-off-by: Byron Lathi
---
target/arm/cpu_tcg.c | 36
1 file changed, 36 insertions(+)
Add the Cortex-A5 to the list of supported CPUs by the virt platform.
Signed-off-by: Byron Lathi
---
docs/system/arm/virt.rst | 1 +
hw/arm/virt.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index 850787495b..2384606ae7 100
Patch 1 adds the Cortex-A5 to the tcg
Patch 2 adds the Cortex-A5 as a supported cpu for the virt machine, and updates
the documentation accordingly.
Byron Lathi (2):
target/arm: Implement Cortex-A5
hw/arm: Add Cortex-A5 to virt device
docs/system/arm/virt.rst | 1 +
hw/arm/virt.c
On Fri, Dec 10, 2021 at 6:00 PM wrote:
>
> From: Frank Chang
>
> This patchset implements the vector extension v1.0 for RISC-V on QEMU.
>
> RVV v1.0 spec is now fronzen for public review:
> https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
>
> The port is available here:
> https://github.co
On Thu, Dec 09, 2021 at 10:08:37PM +, David Woodhouse wrote:
> The check on x86ms->apic_id_limit in pc_machine_done() had two problems.
>
> Firstly, we need KVM to support the X2APIC API in order to allow IRQ
> delivery to APICs >= 255. So we need to call/check kvm_enable_x2apic(),
> which was
On Wed, Dec 15, 2021 at 02:41:32PM +0100, Markus Armbruster wrote:
> Peter Xu writes:
>
> > On Wed, Dec 15, 2021 at 03:56:55PM +0800, Hyman Huang wrote:
> >> > > +{ 'command': 'vcpu-dirty-limit',
> >> > > + 'data': { 'enable': 'bool',
> >> > > +'*cpu-index': 'uint64',
> >> > > +
available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-ppc-20211215
for you to fetch changes up to cdf906d7ea79afb3283b57e3cf1b89f1334f7f2b:
ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices (2021-12-15 08:20
Hi,
> > Maybe we should just not set DeviceState->hotplugged = true for devices
> > added in VM_STATE_PRELAUNCH? It's not actual hotplug (i.e. device added
> > while the system is running) after all ...
> Simply not setting "DeviceState->hotplugged" doesn't work. Devices created
> in
> PHASE_M
On Thu, Dec 16, 2021 at 10:27 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> The Hypervisor spec is now frozen, so remove the experimental tag.
>
> Signed-off-by: Alistair Francis
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> target/riscv/cpu.c | 2 +-
> 1 file
On Thu, Dec 16, 2021 at 10:27 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so
> let's set that as the maximum for the virt board.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435
> Signed-off-by: Alistair
On Thu, Dec 16, 2021 at 10:29 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Let's enable the Hypervisor extension by default. This doesn't affect
> named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
> Hypervisor extensions by default for the virt machine.
>
> Signed-o
On Thu, Dec 16, 2021 at 10:31 AM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> As per the device tree specification let's set the clock-frequency for
> the virt CPUs.
>
> QEMU doesn't really have an exact clock, so let's just 100 as it's a
> nice round number and matches the sifive_u
The bitmanip extension has now been ratified [1] and upstream tooling
(gcc/binutils) support it too, so move them out of experimental and also
enable by default (for better test exposure/coverage)
[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
Signed-off-by: Vineet Gupta
--
From: Alistair Francis
As per the device tree specification let's set the clock-frequency for
the virt CPUs.
QEMU doesn't really have an exact clock, so let's just 100 as it's a
nice round number and matches the sifive_u CLINT_TIMEBASE_FREQ.
Resolves: https://gitlab.com/qemu-project/qemu/-/
From: Alistair Francis
When realising the SoC use error_fatal instead of error_abort as the
process can fail and report useful information to the user.
Currently a user can see this:
$ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display
none -drive if=pflash
QEMU 6.1.
From: Alistair Francis
Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so
let's set that as the maximum for the virt board.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435
Signed-off-by: Alistair Francis
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 inserti
From: Alistair Francis
Let's enable the Hypervisor extension by default. This doesn't affect
named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
Hypervisor extensions by default for the virt machine.
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
1 file changed,
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/intc/sifive_plic.c | 76 +++
1 file changed, 27 insertions(+), 49 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index a9f7a1bfb0..698492ce77 10
From: Alistair Francis
We can remove the original sifive_plic_irqs_pending() function and
instead just use the sifive_plic_claim() function (renamed to
sifive_plic_claimed()) to determine if any interrupts are pending.
This requires move the side effects outside of sifive_plic_claimed(),
but as
From: Alistair Francis
The Hypervisor spec is now frozen, so remove the experimental tag.
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..1edb2771b4 100644
--- a
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/intc/sifive_plic.c | 55 +--
1 file changed, 11 insertions(+), 44 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 698492ce77..44d24b3c59 10
From: Alistair Francis
This is a few patches to cleanup some RISC-V hardware and mark the
Hyperisor extension as non experimental.
v2:
- Add some more fixes
- Address review comments
Alistair Francis (9):
hw/intc: sifive_plic: Add a reset function
hw/intc: sifive_plic: Cleanup the write f
From: Alistair Francis
Signed-off-by: Alistair Francis
---
hw/intc/sifive_plic.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 877e76877c..a9f7a1bfb0 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -
https://github.com/legoater/qemu/ tags/pull-ppc-20211215
for you to fetch changes up to cdf906d7ea79afb3283b57e3cf1b89f1334f7f2b:
ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices (2021-12-15 08:20:37
+0100)
ppc 7.0 queue:
* Gener
On Wed, Dec 15, 2021 at 10:47 PM Philippe Mathieu-Daudé
wrote:
>
> The "Interrupt Cause" register (VMXNET3_REG_ICR) is read-only.
> Write accesses are ignored. Log them with as LOG_GUEST_ERROR
> instead of aborting:
>
> [R +0.239743] writeq 0xe0002031 0x46291a5a55460800
> ERROR:hw/net/vmxnet3.
Ping...
On 2021/11/21 20:24, Yanan Wang wrote:
Hi,
This series introduces the new CPU clusters topology parameter
and enable the support for it on ARM virt machines.
Background and descriptions:
The new Cluster-Aware Scheduling support has landed in Linux 5.16,
which has been proved to benefit
On 2021/12/16 0:48, Philippe Mathieu-Daudé wrote:
Keep the common TYPE_MACHINE class initialization in
machine_base_class_init(), make it abstract, and move
the non-common code to a new class: "smp-generic-valid".
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
tes
Hi Philippe,
On 2021/12/16 0:48, Philippe Mathieu-Daudé wrote:
Avoid modifying the MachineClass internals by adding the
'smp-generic-invalid' machine, which inherits from TYPE_MACHINE.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
tests/unit/test-smp-parse.c | 25
On Thu, Dec 16, 2021 at 4:57 AM Philippe Mathieu-Daudé
wrote:
>
> From: Philippe Mathieu-Daudé
>
> The issue reported by OSS-Fuzz produces the following backtrace:
>
> ==447470==ERROR: AddressSanitizer: heap-buffer-overflow
> READ of size 1 at 0x6152a080 thread T0
> #0 0x71766d47 in
On Wed, Dec 15, 2021 at 6:07 PM Stefan Hajnoczi wrote:
>
> On Wed, Dec 15, 2021 at 11:18:05AM +0800, Jason Wang wrote:
> > On Tue, Dec 14, 2021 at 9:11 PM Stefan Hajnoczi wrote:
> > >
> > > On Tue, Dec 14, 2021 at 10:22:53AM +0800, Jason Wang wrote:
> > > > On Mon, Dec 13, 2021 at 11:14 PM Stefan
On 211216 1011, dhbbb wrote:
> Hello Alex,
> I have found some crashes with qemu-fuzz-i386 (generic-fuzz) such as
> heap-buffer-overflow.But some of the crashes can't reproduce in
> qemu-system-i386(No segment fault).Are these crashes false positives?
Usually, when we can't reproduce bugs in
Hi,
On 2021/12/4 下午5:28, Song Gao wrote:
Based-on:https://patchew.org/QEMU/1637893388-10282-1-git-send-email-gaos...@loongson.cn/
Hi all,
This series only support linux-user emulation.
More about LoongArch at:https://github.com/loongson/
The latest kernel:
*https://github.com/loongson/linux
This adds a GPIO transmitter, a device which takes in the GPIO state of
a GPIO controller and transmits it via chardev.
The purpose of this device is to relay any GPIO changes to external
software that may need to act on them.
To integrate this device into a GPIO controller, the GPIO transmitter
For the GPIO transmitter to properly transmit on pin changes, it must
know the initial state of the GPIO pins on the controller.
Signed-off-by: Joe Komlodi
---
hw/gpio/npcm7xx_gpio.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
inde
For transmitting the GPIO state to the outside world, the GPIO transmitter will
need to know which controller's state has been updated.
To do this, we'll just number each controller at initialization.
Signed-off-by: Joe Komlodi
---
hw/arm/npcm7xx.c | 1 +
hw/gpio/npcm7xx_gpio.c
Hi all,
This series introduces a GPIO transmitter, which allows the transmission
of GPIO controller pin state over chardev, and attaches it to the NPCM7xx
GPIO controller.
The GPIO transmitter takes in a GPIO controller number and a bitfield
containing the GPIO state of that controller, then form
This adds the GPIO transmitter to the NPCM7xx GPIO controller and
transmits packets any time the pin state changes.
Signed-off-by: Joe Komlodi
---
hw/arm/Kconfig | 1 +
hw/arm/npcm7xx.c | 7 +++
hw/gpio/npcm7xx_gpio.c | 14 ++
include/hw/ar
To avoid spamming whoever is connected to the chardev any time a pin state
changes, we'll provide an allowlist so the transmitter only transmits on
state changes the user cares about.
The allowlist is a qdev property that takes in an array of pin numbers
to pay attention to, and maps it to a relat
This tests each NPCM7xx GPIO controller to make sure that when GPIO state is
updated, the controller sends a request to the GPIO transmitter to transmit the
data via chardev.
Along with that, we verify that the data is formatted correctly.
Signed-off-by: Joe Komlodi
---
tests/qtest/google_gpio_t
> -Original Message-
> From: Qemu-devel bounces+chen.zhang=intel@nongnu.org> On Behalf Of Philippe
> Mathieu-Daudé
> Sent: Tuesday, December 14, 2021 6:18 PM
> To: Daniel P. Berrangé
> Cc: Hailiang Zhang ; quint...@redhat.com;
> Wen Congyang ; qemu-devel@nongnu.org;
> dgilb...@redha
On 12/15/21 6:02 AM, Markus Armbruster wrote:
The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2021-12-14 12:46:18 -0800)
are available in the Git repository at:
git://repo.or.cz
On 12/15/21 2:40 AM, Peter Maydell wrote:
From: Jean-Philippe Brucker
Add two test cases for VIOT, one on the q35 machine and the other on
virt. To test complex topologies the q35 test has two PCIe buses that
bypass the IOMMU (and are therefore not described by VIOT), and two
buses that are tra
From: David Hildenbrand
Let's avoid having to manually copy all elements. Copy only the ones
necessary to close the hole and perform the operation in-place without
a second array.
Signed-off-by: David Hildenbrand
Signed-off-by: Raphael Norwitz
---
subprojects/libvhost-user/libvhost-user.c | 3
When VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS support was added to
libvhost-user, no guardrails were added to protect against QEMU
attempting to hot-add too many RAM slots to a VM with a libvhost-user
based backed attached.
This change adds the missing error handling by introducing a check on
the
Hey Stefan, Marc-Andre, MST, David -
As promised here is a series cleaning up error handling in the
libvhost-user memory mapping path. Most of these cleanups are
straightforward and have been discussed on the mailing list in threads
[1] and [2]. Hopefully there is nothing super controversial in th
Today if QEMU (or any other VMM) has sent multiple copies of the same
region to a libvhost-user based backend and then attempts to remove the
region, only one instance of the region will be removed, leaving stale
copies of the region in dev->regions[].
This change resolves this by having vu_rem_me
Signed-off-by: Raphael Norwitz
---
subprojects/libvhost-user/libvhost-user.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/subprojects/libvhost-user/libvhost-user.c
b/subprojects/libvhost-user/libvhost-user.c
index 573212a83b..80ef335254 100644
--- a/subprojects/libvhost-user/libvhos
Signed-off-by: Raphael Norwitz
---
subprojects/libvhost-user/libvhost-user.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/subprojects/libvhost-user/libvhost-user.c
b/subprojects/libvhost-user/libvhost-user.c
index 787f4d2d4f..573212a83b 100644
--- a/subprojects/libvhost-user/libvhos
On Wed, Dec 15, 2021 at 10:35:26AM -0500, Jagannathan Raman wrote:
> Specify target VM for exec_command and
> exec_command_and_wait_for_pattern routines
>
> Signed-off-by: Elena Ufimtseva
> Signed-off-by: John G Johnson
> Signed-off-by: Jagannathan Raman
> ---
> tests/avocado/avocado_qemu/__in
With a Sphinx project auto-generated, configure it to be something a bit
more useful. And pretty.
Signed-off-by: John Snow
---
docs/conf.py | 45 -
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/docs/conf.py b/docs/conf.py
index c7ce779
On 15/12/2021 14:04, Alex Bennée wrote:
As --enable-profiler isn't defended in CI we missed this breakage.
Move the qmp handler into accel/tcg so we have access to the helpers
we need. While we are at it ensure we gate the feature on CONFIG_TCG.
Signed-off-by: Alex Bennée
Suggested-by: Daniel
Add v0.0.1 tag, marking the first public alpha release of the qemu.qmp
package.
---
README.rst | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/README.rst b/README.rst
index bd4a301..e82ac03 100644
--- a/README.rst
+++ b/README.rst
@@ -126,4 +126,7 @@ locally before submitti
Change the configuration for the generated apidoc stubs.
Some of the changes, as a summary:
- Collapse the hierarchy to omit the QEMU namespace page
- Add more meaningful titles to the subpackages
- Prefer source ordering in most places
- Do not index pages that do not define their own symbols (v
Signed-off-by: John Snow
---
Makefile | 5 +
1 file changed, 5 insertions(+)
diff --git a/Makefile b/Makefile
index 81bfca8..029a824 100644
--- a/Makefile
+++ b/Makefile
@@ -103,6 +103,7 @@ check-coverage:
clean:
python3 setup.py clean --all
rm -f pyproject.toml
+ make
The version number will now be generated using the setuptools_scm
package, which pulls the version number from git tags.
As PEP660 is not yet usable with pyproject.toml style packages, we will
be sticking to setup.py style installation for now.
"version = 0.0.0" exists as a fallback in the event
Signed-off-by: John Snow
---
.gitlab-ci.d/index.yml | 2 ++
.gitlab-ci.d/publish.yml | 11 +++
.gitlab-ci.d/python.Dockerfile | 1 +
3 files changed, 14 insertions(+)
create mode 100644 .gitlab-ci.d/publish.yml
diff --git a/.gitlab-ci.d/index.yml b/.gitlab-ci.d/index.yml
Signed-off-by: John Snow
---
.gitlab-ci.d/build.yml | 1 +
.gitlab-ci.d/python.Dockerfile | 2 ++
2 files changed, 3 insertions(+)
diff --git a/.gitlab-ci.d/build.yml b/.gitlab-ci.d/build.yml
index bf2d487..5634173 100644
--- a/.gitlab-ci.d/build.yml
+++ b/.gitlab-ci.d/build.yml
@@ -4,6
Before enabling docs building as a CI step, lingering cross-reference
failures need to be addressed.
Signed-off-by: John Snow
---
qemu/qmp/legacy.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qemu/qmp/legacy.py b/qemu/qmp/legacy.py
index 6c250cd..8e976f9 100644
--- a
This is the result of this command:
sphinx-apidoc --separate \
--no-toc \
--module-first \
--implicit-namespaces \
--full \
--ext-intersphinx \
--ext-coverage \
--ext-viewcode \
-o docs/
FIXME: For testing purposes, this patch is still using my personal
GitLab URLs, which will have to be changed before this is pushed to
production.
Signed-off-by: John Snow
---
.gitlab-ci.d/test.yml | 43 +++
1 file changed, 43 insertions(+)
diff --git a/.
Signed-off-by: John Snow
---
Makefile | 32
1 file changed, 32 insertions(+)
diff --git a/Makefile b/Makefile
index 97d737a..81bfca8 100644
--- a/Makefile
+++ b/Makefile
@@ -110,3 +110,35 @@ distclean: clean
rm -f .coverage .coverage.*
rm -rf html
Signed-off-by: John Snow
---
.gitlab-ci.d/build.yml | 13 +
.gitlab-ci.d/index.yml | 2 ++
2 files changed, 15 insertions(+)
create mode 100644 .gitlab-ci.d/build.yml
diff --git a/.gitlab-ci.d/build.yml b/.gitlab-ci.d/build.yml
new file mode 100644
index 000..6a68408
--- /dev/n
Signed-off-by: John Snow
---
.gitlab-ci.d/test.yml | 16
Makefile | 1 +
avocado.cfg | 7 +++
3 files changed, 24 insertions(+)
diff --git a/.gitlab-ci.d/test.yml b/.gitlab-ci.d/test.yml
index 19e0c37..3b2a142 100644
--- a/.gitlab-ci.d/test.yml
+++ b
The README here will reflect both what is shown on GitLab and on the
PyPI landing page. Update it accordingly.
Signed-off-by: John Snow
---
INDEX.rst | 2 +-
MANIFEST.in | 2 +-
PACKAGE.rst | 43 --
README.rst | 129
se
The name of the package has changed, and the dependencies are different
now as well. Re-do the Pipfile.
This is a little annoying, but Python doesn't offer any tool that
behaves in a manner that gives you the *oldest* but still adequate
versions of dependencies.
So, I'm doing this manually: pin e
Signed-off-by: John Snow
---
setup.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/setup.cfg b/setup.cfg
index 7cd8470..9946875 100644
--- a/setup.cfg
+++ b/setup.cfg
@@ -7,7 +7,7 @@ maintainer = QEMU Project
maintainer_email = qemu-devel@nongnu.org
url = https://www.qem
Now that we've got a Pipfile.lock generated that works, we can remove
the static pins from the Pipfile to allow various dependencies to be
added or removed as necessary when updating our direct dependencies in
the future.
So long as --keep-outdated is always passed to Pipenv, items that aren't
abs
Borrowed with minor modifications from qemu.git.
Signed-off-by: John Snow
---
.gitlab-ci.d/check-dco.py | 98 +++
.gitlab-ci.d/index.yml| 2 +
.gitlab-ci.d/test.yml | 15 ++
3 files changed, 115 insertions(+)
create mode 100755 .gitlab-ci.d/check
Point to this library's URLs instead of the entire project's.
FIXME: In development, the URLs here are jsnow/qemu.qmp. It is intended
that the production version that gets pushed to qemu-project/qemu.qmp
will use URLs that reflect that repository appropriately.
Signed-off-by: John Snow
---
setu
I'm the primary author of this particular component; update the metadata
accordingly.
Signed-off-by: John Snow
---
setup.cfg | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/setup.cfg b/setup.cfg
index bca..7cd8470 100644
--- a/setup.cfg
+++ b/setup.cfg
@@ -1,7 +1,9 @@
The intent is to use README.rst as the new package-level readme that
will be bundled with the source; so move the old "git level readme" over
to INDEX.rst instead, and update it accordingly.
This is primarily here to just document and explain what all the little
bits and pieces of files in the roo
qemu.qmp will be independently versioned, without regard to QMP
version. While the repo is being established here, set the version to
something impossibly low.
Signed-off-by: John Snow
---
VERSION | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/VERSION b/VERSION
index c19f3b8
Heavily copy-pasted from the QEMU source tree, with bits and pieces not
needed for this repository trimmed down.
Signed-off-by: John Snow
---
.gitlab-ci.d/containers.yml| 28
.gitlab-ci.d/index.yml | 8
.gitlab-ci.d/python.Dockerfile | 31 ++
Split python/ from qemu.git, using these commands:
> git subtree split -P python/ -b python-split-v2
> mkdir ~/src/tmp
> cd ~/src/tmp
> git clone --no-local --branch python-split-v2 --single-branch ~/src/qemu
> cd qemu
> git filter-repo --path qemu/machine/ \
--path qem
Hi, this series is part of an effort to publish the qemu.qmp package on
PyPI. It is the second of three series to complete this work:
(1) Switch the new Async QMP library in to python/qemu/qmp
--> (2) Fork python/qemu/qmp out into its own repository,
with updated GitLab CI/CD targets t
Include the qtest reproducer provided by Alexander Bulekov
in https://gitlab.com/qemu-project/qemu/-/issues/451. Without
the previous commit, we get:
$ make check-qtest-i386
...
Running test qtest-i386/fuzz-sdcard-test
==447470==ERROR: AddressSanitizer: heap-buffer-overflow on address
0x6
From: Philippe Mathieu-Daudé
The issue reported by OSS-Fuzz produces the following backtrace:
==447470==ERROR: AddressSanitizer: heap-buffer-overflow
READ of size 1 at 0x6152a080 thread T0
#0 0x71766d47 in sdhci_read_dataport hw/sd/sdhci.c:474:18
#1 0x7175f139 in sdhci_read h
Hi,
This series is an attempt to fix the DMA re-entrancy problem
on the SDHCI device. OSS-Fuzz found it and Alexander generated
a helpful reproducer.
By setting the MemTxAttrs::memory bit before doing DMA transactions,
the flatview API will return MEMTX_BUS_ERROR if the transaction
targets a non-
From: Philippe Mathieu-Daudé
DMA transactions might fail. The DMA API returns a MemTxResult,
indicating such failures. Do not ignore it. On failure, raise
the ADMA error flag and eventually triggering an IRQ (see spec
chapter 1.13.5: "ADMA2 States").
Signed-off-by: Philippe Mathieu-Daudé
---
h
On 12/15/21 21:55, Philippe Mathieu-Daudé wrote:
> Hi,
>
> This series is an attempt to fix the DMA re-entrancy problem
> on the SDHCI device. OSS-Fuzz found it and Alexander generated
> a helpful reproducer.
>
> By setting the MemTxAttrs::memory bit before doing DMA transactions,
> the flatview
Hi,
This series is an attempt to fix the DMA re-entrancy problem
on the SDHCI device. OSS-Fuzz found it and Alexander generated
a helpful reproducer.
By setting the MemTxAttrs::memory bit before doing DMA transactions,
the flatview API will return MEMTX_BUS_ERROR if the transaction
targets a non-
On 15/12/2021 18.14, Richard Henderson wrote:
On 12/14/21 11:33 PM, Thomas Huth wrote:
Hi!
The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2021-12-14 12:46:18 -0800)
are availa
Signed-off-by: Paolo Bonzini
---
configure | 5 -
1 file changed, 5 deletions(-)
diff --git a/configure b/configure
index 48c21775f3..d3aac031a5 100755
--- a/configure
+++ b/configure
@@ -626,7 +626,6 @@ fi
case $targetos in
MINGW32*)
mingw32="yes"
- supported_os="yes"
plugins="no"
From: Yang Zhong
Add the SGXEPCSection list into SGXInfo to show the multiple
SGX EPC sections detailed info, not the total size like before.
This patch can enable numa support for 'info sgx' command and
QMP interfaces. The new interfaces show each EPC section info
in one numa node. Libvirt can u
From: Maxim Levitsky
Use the KVM_GUESTDBG_BLOCKIRQ debug flag if supported.
Signed-off-by: Maxim Levitsky
[Extracted from Maxim's patch into a separate commit. - Paolo]
Signed-off-by: Paolo Bonzini
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <2021110604.20737
Signed-off-by: Paolo Bonzini
Acked-by: Cornelia Huck
Reviewed-by: Alex Bennée
Message-Id: <2021110604.207376-3-pbonz...@redhat.com>
Signed-off-by: Paolo Bonzini
---
include/standard-headers/drm/drm_fourcc.h | 121 +-
include/standard-headers/linux/ethtool.h | 31 +
In Linux 5.16, the padding of struct virtio_gpu_ctrl_hdr has become a
single-byte field followed by a uint8_t[3] array of padding bytes,
and virtio_gpu_ctrl_hdr_bswap does not compile anymore.
Signed-off-by: Paolo Bonzini
Acked-by: Cornelia Huck
Reviewed-by: Alex Bennée
Reviewed-by: Michael S.
From: Evan Miller
Older versions of Mac OS X do not support cp -a. The cp man page indicates
that -a is equivalent to -pPR.
Signed-off-by: Evan Miller
Message-Id: <40635c6e-059a-4146-b1e2-f6376700e...@gmail.com>
[Leave out -R, these are files and not directories. - Paolo]
Signed-off-by: Paolo B
From: Philippe Mathieu-Daudé
If asked for DMA request and no data is available, simply wait
for data to be queued, do not abort. This fixes:
$ cat << EOF | \
qemu-system-i386 -nographic -M q35,accel=qtest -serial none \
-monitor none -qtest stdio -trace lsi* \
-drive if=none,id
From: Yanan Wang
In terms of scope, die-id should mean "the die number within
socket the CPU belongs to" instead of "the die number within
node/board the CPU belongs to". Fix it to avoid confusing
the Doc reader.
Fixes: 176d2cda0d ("i386/cpu: Consolidate die-id validity in smp context")
Signed-o
From: Yang Zhong
The basic SGX did not enable numa for SGX EPC sections, which
result in all EPC sections located in numa node 0. This patch
enable SGX numa function in the guest and the EPC section can
work with RAM as one numa node.
The Guest kernel related log:
[0.009981] ACPI: SRAT: Node
From: Yang Zhong
Add the SGX numa reference command and how to check if
SGX numa is support or not with multiple EPC sections.
Signed-off-by: Yang Zhong
Message-Id: <20211101162009.62161-5-yang.zh...@intel.com>
Signed-off-by: Paolo Bonzini
---
docs/system/i386/sgx.rst | 31 +++
From: Maxim Levitsky
Signed-off-by: Maxim Levitsky
[Extracted from Maxim's patch into a separate commit. - Paolo]
Signed-off-by: Paolo Bonzini
Reviewed-by: Alex Bennée
Message-Id: <2021110604.207376-5-pbonz...@redhat.com>
Signed-off-by: Paolo Bonzini
---
accel/kvm/kvm-all.c | 12 +++
From: Philippe Mathieu-Daudé
Without the previous commit, this test triggers:
$ make check-qtest-x86_64
[...]
Running test qtest-x86_64/fuzz-lsi53c895a-test
qemu-system-x86_64: hw/scsi/lsi53c895a.c:624: lsi_do_dma: Assertion
`s->current' failed.
ERROR qtest-x86_64/fuzz-lsi53c895a-test
From: Maxim Levitsky
handle_query_qemu_sstepbits is reporting NOIRQ and NOTIMER bits
even if they are not supported (as is the case with record/replay).
Instead, store the supported singlestep flags and reject
any unsupported bits in handle_set_qemu_sstep. This removes
the need for the get_sstep
The following changes since commit 50456a6794fbb8dc94a31eb9534e91c586da7add:
Merge tag 'pull-ppc-20211129' of https://github.com/legoater/qemu into
staging (2021-11-29 21:56:06 +0100)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to f
FWIW I Agree.
(Which probably means somethings hiding somewhere :-) )
Cheers
Mark.
> On 15 Dec 2021, at 21:00, Paolo Bonzini wrote:
>
> On 12/14/21 12:48, Markus Armbruster wrote:
>> Let's start with where we (hopefully) agree:
>
> More or less I do agree with this, except for a couple poin
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