On Thu, Dec 02, 2021 at 11:53:25AM +0800, Jason Wang wrote:
> On Thu, Dec 2, 2021 at 4:58 AM David Woodhouse wrote:
> >
> > From: David Woodhouse
> >
> > We should probably check if we were meant to be exposing IR, before
> > letting the guest turn the IRE bit on.
>
> This looks correct, but it'
On Thu, Dec 02, 2021 at 11:49:25AM +0800, Jason Wang wrote:
> On Thu, Dec 2, 2021 at 4:55 AM David Woodhouse wrote:
> >
> > From: David Woodhouse
> >
> > By setting none of the SAGAW bits we can indicate to a guest that DMA
> > translation isn't supported. Tested by booting Windows 10, as well as
On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote:
>
> Get kernel and fdt start address in virt.c, and pass them to KVM
> when cpu reset. In addition, add kvm_riscv.h to place riscv specific
> interface.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
On 12/2/21 9:21 PM, Emilio Cota wrote:
On Thu, Dec 2, 2021 at 4:47 AM Vasilev Oleg wrote:
The mentioned paper[4] also describes other possible improvements.
Some of those are already implemented (such as victim TLB and dynamic
size for TLB), but others are not (e.g. TLB lookup uninlining and
se
On Thu, Dec 02, 2021 at 02:44:42PM +, Peter Maydell wrote:
> On Wed, 1 Dec 2021 at 17:19, Stefan Hajnoczi wrote:
> >
> > Compiler optimizations can cache TLS values across coroutine yield
> > points, resulting in stale values from the previous thread when a
> > coroutine is re-entered by a new
On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote:
>
> Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
> ---
> target/riscv/kvm.c | 141 -
> 1 fi
On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote:
>
> Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
> ---
> target/riscv/kvm.c | 150 -
> 1
Hello Daniel,
On Tue, Nov 23, 2021 at 6:56 AM Daniel P. Berrangé wrote:
>
> On Tue, Nov 23, 2021 at 01:46:44AM -0300, Leonardo Bras Soares Passos wrote:
> > Hello Daniel,
> >
> > On Fri, Nov 12, 2021 at 7:54 AM Daniel P. Berrangé
> > wrote:
> > [...]
> > > > @@ -561,12 +577,15 @@ static ssize_t
Hello Daniel,
On Tue, Nov 23, 2021 at 6:45 AM Daniel P. Berrangé wrote:
>
> On Mon, Nov 22, 2021 at 08:18:09PM -0300, Leonardo Bras Soares Passos wrote:
> > Hello Daniel,
> > Thanks for the feedback!
> >
> > On Fri, Nov 12, 2021 at 7:13 AM Daniel P. Berrangé
> > wrote:
> > >
> > > On Fri, Nov 1
On Thu, Dec 2, 2021 at 4:47 AM Vasilev Oleg wrote:
> The mentioned paper[4] also describes other possible improvements.
> Some of those are already implemented (such as victim TLB and dynamic
> size for TLB), but others are not (e.g. TLB lookup uninlining and
> set-associative TLB layer). Do you t
On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote:
>
> Add target/riscv/kvm.c to place kvm_arch_* function needed by
> kvm/kvm-all.c. Meanwhile, add kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
Looks good to me.
R
On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang wrote:
>
> Add asm-riscv/kvm.h for RISC-V KVM, and update linux/kvm.h
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> linux-headers/asm-riscv/kvm.h | 128
On 12/1/21 8:03 PM, David Hildenbrand wrote:
* It has been passing the tests with various combinations like 64KB
and 4KB page sizes on host and guest, different memory device
backends like normal, transparent huge page and HugeTLB, plus
migration.
Perfect. A note that
The default block size is same as to the THP size, which is either
retrieved from "/sys/kernel/mm/transparent_hugepage/hpage_pmd_size"
or hardcoded to 2MB. There are flaws in both mechanisms and this
intends to fix them up.
* When "/sys/kernel/mm/transparent_hugepage/hpage_pmd_size" is
used
This supports virtio-mem-pci device on "virt" platform, by simply
following the implementation on x86.
* This implements the hotplug handlers to support virtio-mem-pci
device hot-add, while the hot-remove isn't supported as we have
on x86.
* The block size is 512MB on ARM64 instea
This series supports virtio-mem-pci device, by simply following the
implementation on x86. The exception is the block size is 512MB on
ARM64 instead of 128MB on x86, compatible with the memory section
size in linux guest.
The work was done by David Hildenbrand and then Jonathan Cameron. I'm
taking
The 1.15.0 version of SeaBIOS has now been released. For more
information on the release, please see:
http://seabios.org/Releases
New in this release:
* Improved support for USB devices with multiple interfaces.
* Support for USB XHCI devices using direct MMIO access (instead of PCI).
* NVMe i
On 12/2/21 6:06 PM, Halil Pasic wrote:
On Thu, 2 Dec 2021 12:11:38 -0500
Matthew Rosato wrote:
What happens if we migrate a VM from old to new QEMU? Won't the guest be
able to observe the change?
Yes, technically -- But # itself is not really all that important, it
is provided from CLP
From: Hyman Huang(黄勇)
Introduce the third method GLOBAL_DIRTY_LIMIT of dirty
tracking for calculate dirtyrate periodly for dirty restraint.
Implement thread for calculate dirtyrate periodly, which will
be used for dirty restraint.
Add dirtylimit.h to introduce the util function for dirty
limit
From: Hyman Huang(黄勇)
Implement dirtyrate calculation periodically basing on
dirty-ring and throttle vCPU until it reachs the quota
dirty page rate given by user.
Introduce qmp commands "vcpu-dirty-limit", "query-vcpu-dirty-limit"
to enable, disable, query dirty page limit for virtual CPU.
Mean
From: Hyman Huang(黄勇)
Impose dirty restraint on vCPU by kicking it and sleep
as the auto-converge does during migration, but just
kick the specified vCPU instead, not all vCPUs of vm.
Start a thread to track the dirtylimit status and adjust
the throttle pencentage dynamically depend on current
a
From: Hyman Huang(黄勇)
v9:
- rebase on master
- fix the meson directory change, keep it untouched.
v8:
- rebase on master
- polish the error message and remove the "unlikely" compilation syntax
according to the advice given by Markus.
- keep the dirty tracking enabled during "dirtylimit-calc" l
On 12/2/2021 5:54 PM, Vladimir Sementsov-Ogievskiy wrote:
02.12.2021 11:53, Daniel P. Berrangé wrote:
On Thu, Dec 02, 2021 at 01:14:47PM +0800, Rao, Lei wrote:
Sorry, resending with correct indentation and quoting.
On 12/1/2021 10:27 PM, Vladimir Sementsov-Ogievskiy wrote:
01.12.2021 12:48
在 2021/12/3 0:02, Markus Armbruster 写道:
huang...@chinatelecom.cn writes:
From: Hyman Huang(黄勇)
Implement dirtyrate calculation periodically basing on
dirty-ring and throttle vCPU until it reachs the quota
dirty page rate given by user.
Introduce qmp commands set-dirty-limit/cancel-dirty-l
On 11/19/21 05:47, Chao Peng wrote:
From: "Kirill A. Shutemov"
The new seal type provides semantics required for KVM guest private
memory support. A file descriptor with the seal set is going to be used
as source of guest memory in confidential computing environments such as
Intel TDX and AMD S
On 11/19/21 05:47, Chao Peng wrote:
This RFC series try to implement the fd-based KVM guest private memory
proposal described at [1] and an improved 'New Proposal' described at [2].
I generally like this. Thanks!
On Thu, 2 Dec 2021 12:11:38 -0500
Matthew Rosato wrote:
> >
> > What happens if we migrate a VM from old to new QEMU? Won't the guest be
> > able to observe the change?
> >
>
> Yes, technically -- But # itself is not really all that important, it
> is provided from CLP Q PCI FN to be subse
On 02.12.21 18:11, Matthew Rosato wrote:
> On 12/2/21 11:43 AM, David Hildenbrand wrote:
>> On 02.12.21 17:41, Matthew Rosato wrote:
>>> The current default PCI group being used can technically collide with a
>>> real group ID passed from a hostdev. Let's instead use a group ID that
>>> comes
>>>
On 12/2/21 11:11 AM, Cédric Le Goater wrote:
They have been there since 2007 without any board using them, most
were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu-models.h | 19 --
target/ppc/cpu-qom.h | 4 -
target/ppc/cpu-models.c |
On Thu, 2021-12-02 at 11:41 -0500, Matthew Rosato wrote:
> The DTSM is a mask that specifies which I/O Address Translation
> designation
> types are supported. A linux guest today does not look at this field
> but
> could in the future; let's advertise what QEMU actually supports.
>
> Signed-off-
On Thu, 2021-12-02 at 11:41 -0500, Matthew Rosato wrote:
> We may have gotten a measurement update interval from the underlying
> host
> via vfio -- Use it to set the interval via which we update the
> function
> measurement block.
>
> Fixes: 28dc86a072 ("s390x/pci: use a PCI Group structure")
> S
On Thu, 2021-12-02 at 11:41 -0500, Matthew Rosato wrote:
> Instead use the values from clp info, they will either be the hard-
> coded
> values or what came from the host driver via vfio.
>
> Fixes: 9670ee752727 ("s390x/pci: use a PCI Function structure")
> Signed-off-by: Matthew Rosato
Reviewed
On Thu, 2021-12-02 at 11:41 -0500, Matthew Rosato wrote:
> The current default PCI group being used can technically collide with
> a
> real group ID passed from a hostdev. Let's instead use a group ID
> that comes
> from a special pool that is architected to be reserved for simulated
> devices.
>
According to the M68040 Users Manual, section 8.4.3, Four word
stack frame (format 0), includes Illegal Instruction. Use the
correct frame format, which does not use the ADDR argument.
Signed-off-by: Richard Henderson
---
target/m68k/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deleti
Signed-off-by: Richard Henderson
---
target/m68k/cpu.h | 2 ++
linux-user/m68k/cpu_loop.c | 1 +
target/m68k/cpu.c | 1 +
target/m68k/op_helper.c| 2 +-
target/m68k/translate.c| 41 ++
5 files changed, 46 insertions(+), 1 deletion(
Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc,
and the signals and addresses that we expect from them.
Signed-off-by: Richard Henderson
---
tests/tcg/m68k/trap.c | 129 +
tests/tcg/m68k/Makefile.target | 3 +
2 files changed, 13
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index cfe292c929..641f95ff8a 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -55
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), CHK, CHK2 (and others)
are supposed to record the next insn in PC and the
address of the trapping instruction in ADDRESS.
Create a raise_exception_format2 function to centralize recording
of the trapping pc in mm
Errors are not all negative numbers, but only the top 4k.
Signed-off-by: Richard Henderson
---
linux-user/strace.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 2cdbf030ba..f235118fb6 100644
--- a/linux-user/strace.c
+++ b
On 11/23/21 01:14, Christian Borntraeger wrote:
>
> Am 22.11.21 um 23:33 schrieb Collin Walling:
>> DIAGNOSE 0318 is invoked only once during IPL. As such, the
>> diag318 info will only change once initially and during resets.
>> Let's only sync the register to convey the info to KVM if and
>> onl
Replace an if ladder with a switch for clarity.
Signed-off-by: Richard Henderson
---
target/m68k/op_helper.c | 45 +
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 36662de149..71176eb
Use the new function instead of setting up a target_siginfo_t
and calling queue_signal. Fill in the missing PC for SIGTRAP.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 24
1 file changed, 4 insertions(+), 20 deletions(-)
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index e5338b50ad..cfe292c929 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -4916,6 +4916,14 @@ DISAS_
The only value this variable holds is now env->pc.
Signed-off-by: Richard Henderson
---
target/m68k/op_helper.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 71176eb3d8..afbbb8b4ca 100644
--- a/target/m
Rather than adjust the PC in all of the consumers, raise
the exception with the correct PC in the first place.
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 1 -
target/m68k/op_helper.c| 9 -
target/m68k/translate.c| 2 +-
3 files changed, 1 insertion(+), 11 d
Unlike i386, m68k get_thread_area has no arguments.
Signed-off-by: Richard Henderson
---
linux-user/strace.list | 5 +
1 file changed, 5 insertions(+)
diff --git a/linux-user/strace.list b/linux-user/strace.list
index 278596acd1..72e17b1acf 100644
--- a/linux-user/strace.list
+++ b/linux-us
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), Zero Div (and others)
is supposed to record the next insn in PC and the
address of the trapping instruction in ADDRESS.
While the N, Z and V flags are documented to be undefine on DIV0,
the C flag is documented a
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), Trace (and others) is
supposed to record the next insn in PC and the address
of the trapping instruction in ADDRESS.
Create gen_raise_exception_format2 to record the trapping
pc in env->mmu.ar. Update m68k_inter
These are raised by guest instructions, and should not
fall through into the default abort case.
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c
index 396f98bd6c..0de11fb
Supercedes: <20211130103752.72099-1-richard.hender...@linaro.org>
Reviewing v1, Laurent rightly noticed that there were changes
required in m68k_interrupt_all. Matching sysemu, there were
changes needed in the linux-user cpu_loop.
In the process, I found a number of other trap related bugs,
and
Le 02/12/2021 à 20:19, Cédric Le Goater a écrit :
> On 12/2/21 20:17, Thomas Huth wrote:
>> On 02/12/2021 20.14, Cédric Le Goater wrote:
>>> The default addresses to load the kernel, fdt, initrd of AMCC boards
>>> in U-Boot v2015.10 are :
>>>
>>> "kernel_addr_r=100\0"
>>> "fdt_addr_r=
On 02/12/2021 20.14, Cédric Le Goater wrote:
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=100\0"
"fdt_addr_r=180\0"
"ramdisk_addr_r=190\0"
The taihu is one of these boards, the ref405ep is not bu
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=100\0"
"fdt_addr_r=180\0"
"ramdisk_addr_r=190\0"
The taihu is one of these boards, the ref405ep is not but we don't
have much information on it and both
This change exposes ACPI ERST support for x86 guests.
Signed-off-by: Eric DeVolder
---
hw/i386/acpi-build.c | 15 +++
hw/i386/acpi-microvm.c | 15 +++
include/hw/acpi/erst.h | 5 +
3 files changed, 35 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-
They have been there since 2007 without any board using them, most
were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu-models.h | 19 --
target/ppc/cpu-qom.h | 4 -
target/ppc/cpu-models.c | 34 ---
target/ppc/cpu_init.c| 512 --
On 12/2/21 20:17, Thomas Huth wrote:
On 02/12/2021 20.14, Cédric Le Goater wrote:
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=100\0"
"fdt_addr_r=180\0"
"ramdisk_addr_r=190\0"
The taihu is one of these boar
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 6.
Below is the disassembly of tests/data/acpi/pc/ERST.acpierst.
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180508 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
* D
This builds the ACPI ERST table to inform OSPM how to communicate
with the acpi-erst device.
Signed-off-by: Eric DeVolder
---
hw/acpi/erst.c | 241 +
1 file changed, 241 insertions(+)
diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c
index 4304
On 12/1/21 10:17 PM, John Snow wrote:
The following changes since commit 682aa69b1f4dd5f2905a94066fa4c853adc33251:
Update version for v6.2.0-rc3 release (2021-12-01 07:20:06 +0100)
are available in the Git repository at:
https://gitlab.com/jsnow/qemu.git tags/ide-pull-request
for you to
This change introduces the public defintions for ACPI ERST.
Signed-off-by: Eric DeVolder
Reviewed-by: Ani Sinha
---
include/hw/acpi/erst.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/hw/acpi/erst.h
diff --git a/include/hw/acpi/erst.h b/include/hw/acpi
This change implements the test suite checks for the ERST table.
Signed-off-by: Eric DeVolder
---
tests/qtest/bios-tables-test.c | 56 ++
1 file changed, 56 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 2
This change reserves the PCI device_id for the new ACPI ERST
device.
Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
Acked-by: Ani Sinha
---
include/hw/pci/pci.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index e7cdf2d..d3734b9 100644
-
This patchset introduces support for the ACPI Error Record
Serialization Table, ERST.
For background and implementation information, please see
docs/specs/acpi_erst.rst, which is patch 2/10.
Suggested-by: Konrad Wilk
Signed-off-by: Eric DeVolder
---
v9: 2dec2021
- Addressed feedback from Ani
This change provides a qtest that locates and then does a simple
interrogation of the ERST feature within the guest.
Signed-off-by: Eric DeVolder
---
tests/qtest/erst-test.c | 167
tests/qtest/meson.build | 2 +
2 files changed, 169 insertions(+
This implements a PCI device for ACPI ERST. This implements the
non-NVRAM "mode" of operation for ERST as it is supported by
Linux and Windows.
Signed-off-by: Eric DeVolder
---
hw/acpi/Kconfig | 6 +
hw/acpi/erst.c | 836 +++
hw/acpi/m
Information on the implementation of the ACPI ERST support.
Signed-off-by: Eric DeVolder
Acked-by: Ani Sinha
---
docs/specs/acpi_erst.rst | 200 +++
1 file changed, 200 insertions(+)
create mode 100644 docs/specs/acpi_erst.rst
diff --git a/docs/spec
Following the guidelines in tests/qtest/bios-tables-test.c, this
change adds empty placeholder files per step 1 for the new ERST
table, and excludes resulting changed files in bios-tables-test-allowed-diff.h
per step 2.
Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
---
tests/data/acpi/mi
On 02/12/2021 17:14, Cornelia Huck wrote:
On Thu, Dec 02 2021, Alex Bennée wrote:
This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
The check is bogus as it ends up finding itself and falling over.
Signed-off-by: Alex Bennée
Resolves: https://gitlab.com/qemu-project/qemu.git/-/
On 11/30/21 22:17, Jiaxun Yang wrote:
> Two problems caught when I was trying to add CI job for various
> configurations.
>
> Jiaxun Yang (2):
> hw/mips: bootloader: Fix write_ulong
> hw/mips/boston: Fix elf_load error detection
Thanks, queued to mips-fixes.
On 12/2/21 11:51, Jiaxun Yang wrote:
> 在2021年11月30日十一月 下午9:52，Philippe Mathieu-Daudé写道：
>> On 11/30/21 22:17, Jiaxun Yang wrote:
>>> bl_gen_write_ulong uses sd for both 32 and 64 bit CPU,
>>> while sd is illegal on 32 bit CPUs.
>>>
>>> Replace sd with sw on 32bit CPUs.
>>>
>>> Fixes: 3ebbf86 ("hw/m
On 12/2/21 11:42, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 4 ++--
3 files changed, 6 insertions(+), 2 deletions(-)
On 12/2/21 11:42, Cédric Le Goater wrote:
PHB4 devices and PCI devices can now be added to the powernv9 machine
using:
-device pnv-phb4-pec,chip-id=0,index=0
-device nec-usb-xhci,bus=pci.0,addr=0x0
In case of user created devices, a lookup on 'chip-id' is required to
assign the owning
On 12/2/21 17:49, Alex Bennée wrote:
> This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
>
> The check is bogus as it ends up finding itself and falling over.
>
> Signed-off-by: Alex Bennée
> Resolves: https://gitlab.com/qemu-project/qemu.git/-/issues/733
This link gives 404. The co
On 12/2/21 18:27, Daniel Henrique Barboza wrote:
On 12/2/21 11:42, Cédric Le Goater wrote:
All POWER8 machines have a maximum of 3 PHB3 devices. Adapt the
PNV8_CHIP_PHB3_MAX definition for consistency.
I suggest "3 PHB3 devices per chip" for clarity.
Fixed.
Thanks,
C.
Signed-off-by:
* Juan Quintela (quint...@redhat.com) wrote:
> "Dr. David Alan Gilbert" wrote:
> > * Juan Quintela (quint...@redhat.com) wrote:
> >> So we use multifd to transmit zero pages.
> >>
> >> Signed-off-by: Juan Quintela
> >> ---
> >> migration/ram.c | 22 +++---
> >> 1 file changed, 1
On 12/2/21 11:42, Cédric Le Goater wrote:
This is not useful and will be in the way for support of user created
PHB4 devices.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/pci-host/pnv_phb4_pec.c | 6 +-
hw/ppc/pnv.c | 2 --
2 files ch
On 12/2/21 11:42, Cédric Le Goater wrote:
This change will help us providing support for user created PHB4
devices.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/pci-host/pnv_phb4_pec.c | 36
hw/ppc/pnv.c
On 12/2/21 11:42, Cédric Le Goater wrote:
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
Signed-off-by: Cédric Le Goater
---
On 12/2/21 11:42, Cédric Le Goater wrote:
Each PEC devices of the POWER9 chip has a predefined number of stacks,
s/devices/device ?
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove th
On 12/2/21 12:08, Alex Bennée wrote:
> Philippe Mathieu-Daudé writes:
>> On 11/29/21 13:58, Alex Bennée wrote:
>>>
>>> Juro Bystricky writes:
>>>
Fix compiler warnings. The warnings can result in a broken build.
This patch fixes warnings such as:
>>>
>>> Queued to for-6.2/more-misc-fixe
On 12/2/21 11:42, Cédric Le Goater wrote:
Next changes will make use of it.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 2 ++
3 files changed,
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> So we use multifd to transmit zero pages.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> migration/ram.c | 22 +++---
>> 1 file changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/migratio
On 12/2/21 11:42, Cédric Le Goater wrote:
POWER9 processor comes with 3 PHB4 PECs (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribut
On 12/2/21 11:42, Cédric Le Goater wrote:
PHB3s ared SysBus devices and should be allowed to be dynamically
created.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/pci-host/pnv_phb3.c | 9 +
hw/ppc/pnv.c | 2 ++
2 files changed, 11 inse
On 12/2/21 11:42, Cédric Le Goater wrote:
The powernv machine uses the object hierarchy to populate the device
tree and each device should be parented to the chip it belongs to.
This is not the case for user created devices which are parented to
the container "/unattached".
Make sure a PHB3 d
On 12/2/21 11:42, Cédric Le Goater wrote:
PHB3 devices and PCI devices can now be added to the powernv8 machine
using :
-device pnv-phb3,chip-id=0,index=1 \
-device nec-usb-xhci,bus=pci.1,addr=0x0
The 'index' property identifies the PHB3 in the chip. In case of user
created devices, a
On 12/2/21 11:42, Cédric Le Goater wrote:
This requires a link to the chip to add the regions under the XSCOM
address space. This change will help us providing support for user
created PHB3 devices.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
include/hw/pc
On 12/2/21 11:42, Cédric Le Goater wrote:
It is never used.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/pnv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index bd768dcc28ad..988b305398b2 100644
--- a/hw/ppc/pnv.c
On 12/2/21 11:42, Cédric Le Goater wrote:
All POWER8 machines have a maximum of 3 PHB3 devices. Adapt the
PNV8_CHIP_PHB3_MAX definition for consistency.
I suggest "3 PHB3 devices per chip" for clarity.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
includ
On 12/2/21 11:43 AM, David Hildenbrand wrote:
On 02.12.21 17:41, Matthew Rosato wrote:
The current default PCI group being used can technically collide with a
real group ID passed from a hostdev. Let's instead use a group ID that comes
from a special pool that is architected to be reserved for
* Juan Quintela (quint...@redhat.com) wrote:
> So we use multifd to transmit zero pages.
>
> Signed-off-by: Juan Quintela
> ---
> migration/ram.c | 22 +++---
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/migration/ram.c b/migration/ram.c
> index 57efa67f2
On Thu, Dec 02 2021, Alex Bennée wrote:
> This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
>
> The check is bogus as it ends up finding itself and falling over.
>
> Signed-off-by: Alex Bennée
> Resolves: https://gitlab.com/qemu-project/qemu.git/-/issues/733
> ---
> hw/display/vga-i
From: Hyman Huang(黄勇)
Implement dirtyrate calculation periodically basing on
dirty-ring and throttle vCPU until it reachs the quota
dirty page rate given by user.
Introduce qmp commands "vcpu-dirty-limit", "query-vcpu-dirty-limit"
to enable, disable, query dirty page limit for virtual CPU.
Mean
From: Hyman Huang(黄勇)
v8:
- rebase on master
- polish the error message and remove the "unlikely" compilation syntax
according to the advice given by Markus.
- keep the dirty tracking enabled during "dirtylimit-calc" lifecycle
so that the overhead can be reduced according to the advice given
From: Hyman Huang(黄勇)
Introduce the third method GLOBAL_DIRTY_LIMIT of dirty
tracking for calculate dirtyrate periodly for dirty restraint.
Implement thread for calculate dirtyrate periodly, which will
be used for dirty restraint.
Add dirtylimit.h to introduce the util function for dirty
limit
From: Hyman Huang(黄勇)
Impose dirty restraint on vCPU by kicking it and sleep
as the auto-converge does during migration, but just
kick the specified vCPU instead, not all vCPUs of vm.
Start a thread to track the dirtylimit status and adjust
the throttle pencentage dynamically depend on current
a
The code that introduced "virtio-blk: Configure all host notifiers in
a single MR transaction" introduced a second loop variable to perform
cleanup in second loop, but mistakenly still refers to the first
loop variable within the second loop body.
Fixes: d0267da61489 ("virtio-blk: Configure all ho
On Thu, Dec 02, 2021 at 04:49:29PM +, Alex Bennée wrote:
> This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
>
> The check is bogus as it ends up finding itself and falling over.
>
> Signed-off-by: Alex Bennée
> Resolves: https://gitlab.com/qemu-project/qemu.git/-/issues/733
> --
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> "Dr. David Alan Gilbert" wrote:
>> > * Juan Quintela (quint...@redhat.com) wrote:
>> >> "Dr. David Alan Gilbert" wrote:
>> >> > * Juan Quintela (quint...@redhat.com) wrote:
>> >> >> This patch adds counters and sim
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> This implements the zero page dection and handling.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> migration/multifd.c | 33 +++--
>> 1 file changed, 31 insertions(+), 2 deletions(-)
>>
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