On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Update ucontext to implement sigreturn.
>
> Signed-off-by: Stacey Son
> Signed-off-by: Warner Losh
> ---
> bsd-user/arm/target_arch_signal.h | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/bsd-user/arm/target_a
On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Implement get_elf_hwcap to get the first word of hardware capabilities.
>
> Signed-off-by: Klye Evans
> Signed-off-by: Stacey Son
> Signed-off-by: Warner Losh
> ---
> bsd-user/arm/target_arch_elf.h | 72 +-
On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Basic set of defines needed for arm ELF file activation.
>
> Signed-off-by: Stacey Son
> Signed-off-by: Warner Losh
> ---
> bsd-user/arm/target_arch_elf.h | 36 ++
> 1 file changed, 36 insertions(+)
> creat
On Fri, Oct 15, 2021 at 6:41 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/helper.h | 22 -
> target/riscv/insn32.decode | 15 ---
> target/riscv/insn_trans/trans_rvv.c.inc |
On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Move the machine context to the CPU state.
>
> Signed-off-by: Stacey Son
> Signed-off-by: Klye Evans
> Signed-off-by: Warner Losh
> ---
> bsd-user/arm/target_arch_signal.h | 31 +++
> 1 file changed, 31 inserti
On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Implent EXCP_UDEF, EXCP_DEBUG, EXCP_INTERRUPT, EXCP_ATOMIC and
s/Implent/Implement/
> EXCP_YIELD. The first two generate a signal to the emulated
> binary. EXCP_ATOMIC handles atomic operations. The remainder are fancy
> nops.
>
> Signed-of
On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Arm specific user context structures for signal handling and the closely
> related trap frame.
>
> Signed-off-by: Stacey Son
> Signed-off-by: Warner Losh
> ---
> bsd-user/arm/target_arch_signal.h | 38 +++
> 1 f
On Tue, Oct 26, 2021 at 1:01 AM Kyle Evans wrote:
>
> On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
> >
> > Implement target_thread_init (to create a thread) and target_set_upcall
> > (to switch to a thread) for arm.
> >
> > Signed-off-by: Stacey Son
> > Signed-off-by: Klye Evans
> > Sign
On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Implement target_thread_init (to create a thread) and target_set_upcall
> (to switch to a thread) for arm.
>
> Signed-off-by: Stacey Son
> Signed-off-by: Klye Evans
> Signed-off-by: Warner Losh
> ---
> bsd-user/arm/target_arch_thread.h |
On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Various parameters describing the layout of the ARM address space. In
> addition, define routines to get the stack pointer and to set the second
> return value.
>
> Signed-off-by: Stacey Son
> Signed-off-by: Klye Evans
> Signed-off-by: Warn
On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Implement the extended HW capabilities for HWCAP2.
>
> Signed-off-by: Klye Evans
> Signed-off-by: Warner Losh
> ---
> bsd-user/arm/target_arch_elf.h | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/bsd-user/
On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Copy of the signal trampoline code for arm, as well as setup_sigtramp to
> write it to the stack.
>
> Signed-off-by: Stacey Son
> Signed-off-by: Warner Losh
> ---
> bsd-user/arm/target_arch_sigtramp.h | 52 +
>
On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Implement the register copying routines to extract registers from the
> cpu for core dump generation.
>
> Signed-off-by: Stacey Son
> Signed-off-by: Warner Losh
> ---
> bsd-user/arm/target_arch_reg.h | 60 ++
On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
>
> Implement EXCP_PREFETCH_ABORT AND EXCP_DATA_ABORT. Both of these data
> exceptions cause a SIGSEGV.
>
> Signed-off-by: Klye Evans
> Signed-off-by: Olivier Houchard
> Signed-off-by: Stacey Son
> Signed-off-by: Warner Losh
> ---
> bsd-user
John Snow writes:
> On Mon, Oct 25, 2021 at 1:26 AM Markus Armbruster wrote:
>
>> By convention, names starting with "x-" are experimental. The parts
>> of external interfaces so named may be withdrawn or changed
>> incompatibly in future releases.
>>
>> Drawback: promoting something from exper
Hi Alistair,
On Sat, Oct 23, 2021 at 2:17 PM Anup Patel wrote:
>
> The advanced interrupt architecture (AIA) extends the per-HART local
> interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
> and Advanced PLIC (wired interrupt controller).
>
> The latest AIA draft specification
On Wed, Oct 20, 2021 at 7:57 PM Eugenio Perez Martin
wrote:
>
> On Wed, Oct 20, 2021 at 11:03 AM Jason Wang wrote:
> >
> > On Wed, Oct 20, 2021 at 2:52 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Wed, Oct 20, 2021 at 4:07 AM Jason Wang wrote:
> > > >
> > > > On Wed, Oct 20, 2021 at 10:02
On Thu, Oct 21, 2021 at 10:34 PM Eugenio Perez Martin
wrote:
>
> On Thu, Oct 21, 2021 at 10:12 AM Jason Wang wrote:
> >
> > On Thu, Oct 21, 2021 at 3:03 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Thu, Oct 21, 2021 at 4:34 AM Jason Wang wrote:
> > > >
> > > > On Wed, Oct 20, 2021 at 8:07
Now that we have a generic parser smp_parse(), let's add an unit
test for the code. All possible valid/invalid SMP configurations
that the user can specify are covered.
Signed-off-by: Yanan Wang
Reviewed-by: Andrew Jones
---
MAINTAINERS | 1 +
tests/unit/meson.build | 1
We are going to introduce an unit test for the parser smp_parse()
in hw/core/machine.c, but now machine.c is only built in softmmu.
In order to solve the build dependency on the smp parsing code and
avoid building unrelated stuff for the unit tests, move the tested
code from machine.c into a separ
Hi,
This is v3 which introduces an unit test for generic smp_parse.
We have had enough discussions about what kind of SMP configurations
by the user should be considered valid and what should be invalid.
Since we have finished optimizing the SMP parsing code, then this
test normatively listed all
On 2021/10/13 15:41, Yanan Wang wrote:
Now that we have a generic parser smp_parse(), let's add an unit
test for the code. All possible valid/invalid SMP configurations
that the user can specify are covered.
Signed-off-by: Yanan Wang
Reviewed-by: Andrew Jones
---
MAINTAINERS
On 10/25/21 2:16 PM, BALATON Zoltan wrote:
Hello,
Commit abb0cd93494 (accel/tcg: Split out log_cpu_exec) seems to have broken -singlestep -d
in_asm,cpu output with qemu-system-sh4 after a delay slot. Since that commit I get:
pc=0xac80003e sr=0x50f1 pr=0x fpscr=0x00040001
spc=0x000
Add this file, generated from qemu, so there is a reference devicetree
in the U-Boot tree.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/arm/dts/Makefile| 2 +-
arch/arm/dts/qemu-arm64.dts | 381 +++
configs/qemu_arm64_defconfig | 1 +
3
Add these files, generated from qemu, so there is a reference devicetree
in the U-Boot tree.
Split the existing qemu-virt into two, since we need a different
devicetree for 32- and 64-bit machines.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/riscv/dts/Makefile | 2
QEMU currently generates a devicetree for use with U-Boot. Explain how to
obtain it.
Also explain how to merge it to produce a devicetree with the U-Boot
features included.
Signed-off-by: Simon Glass
---
Changes in v5:
- Merge RISC-V and ARM patches since they are similar
doc/board/emulation/
Add this file, generated from qemu, so there is a reference devicetree
in the U-Boot tree.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/arm/dts/Makefile | 2 +
arch/arm/dts/qemu-arm.dts | 402 +
configs/qemu_arm_defconfig | 1 +
3 file
With Ilias' efforts we have dropped OF_PRIOR_STAGE and OF_HOSTFILE so
there are only three ways to obtain a devicetree:
- OF_SEPARATE - the normal way, where the devicetree is built and
appended to U-Boot
- OF_EMBED - for development purposes, the devicetree is embedded in
the EL
Without this option QEMU appears to hang. Add it to avoid confusion.
Signed-off-by: Simon Glass
---
(no changes since v1)
doc/board/emulation/qemu-arm.rst | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.
On 10/25/21 12:13 PM, Alexander Graf wrote:
+/*
+ * We ran into an instruction that traps for data, but is not
+ * hardware predecoded. This should not ever happen for well
+ * behaved guests. Let's try to see if we can somehow rescue
+ * the situation.
+ */
+
+cpu_syn
The empty NUMA nodes, where no memory resides, aren't exposed
through ACPI SRAT table. It's not user preferred behaviour because
the corresponding memory node devices are missed from the guest
kernel as the following example shows, and memory can't be hot
added to these empty NUMA nodes at later po
On Mon, Oct 25, 2021 at 10:18 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 10/25/21 7:07 AM, Stefan Hajnoczi wrote:
> > This is a preview of how we can solve the coroutines TLS problem.
> Coroutines
> > re-entered from another thread sometimes see stale TLS values. This
> happe
On Mon, 25 Oct 2021, Philippe Mathieu-Daudé wrote:
On 10/25/21 23:16, BALATON Zoltan wrote:
Hello,
Commit abb0cd93494 (accel/tcg: Split out log_cpu_exec) seems to have
broken -singlestep -d in_asm,cpu output with qemu-system-sh4 after a
delay slot.
[...]
However I still don't understand how t
On Tue, 26 Oct 2021, John Paul Adrian Glaubitz wrote:
Hi Zoltan!
On 10/23/21 15:22, BALATON Zoltan wrote:
You either need to strip the kernel with "strip vmlinux" or use the image from
arch/sh/
boot/zImage.
I've actually used that kernel but looked at the wrong uncompressed size, it's
indee
On Mon, Oct 25, 2021 at 2:16 PM Bin Meng wrote:
>
> On Mon, Oct 25, 2021 at 12:07 PM Alistair Francis
> wrote:
> >
> > From: Alistair Francis
> >
> > Fixup the PLIC context address to correctly support the threshold and
> > claim register.
> >
> > Fixes: ef63100648 ("hw/riscv: opentitan: Update
On Tue, Oct 26, 2021 at 3:36 AM Alexey Baturo wrote:
>
> Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6b767a4a0b..16fac64806 10064
Hi Zoltan!
On 10/23/21 15:22, BALATON Zoltan wrote:
>> You either need to strip the kernel with "strip vmlinux" or use the image
>> from arch/sh/
>> boot/zImage.
>
> I've actually used that kernel but looked at the wrong uncompressed size,
> it's indeed just
> 9.2MB when stripped so that should
On 10/25/21 23:16, BALATON Zoltan wrote:
> Hello,
>
> Commit abb0cd93494 (accel/tcg: Split out log_cpu_exec) seems to have
> broken -singlestep -d in_asm,cpu output with qemu-system-sh4 after a
> delay slot.
[...]
> However I still don't understand how the delayed branch ends up at
> 0x8c800964 in
Hello,
Commit abb0cd93494 (accel/tcg: Split out log_cpu_exec) seems to have
broken -singlestep -d in_asm,cpu output with qemu-system-sh4 after a delay
slot. Since that commit I get:
pc=0xac80003e sr=0x50f1 pr=0x fpscr=0x00040001
spc=0x ssr=0x gbr=0x vbr=0x0
On Mon, Oct 25, 2021 at 11:47:38AM +0100, Jean-Philippe Brucker wrote:
> Since commit d8fb7d0969d5 ("vl: switch -M parsing to keyval"), machine
> parameter definitions cannot use underscores, because keyval_dashify()
> transforms them to dashes and the parser doesn't find the parameter.
>
> This a
On 10/25/21 21:13, Alexander Graf wrote:
> Apple's Hypervisor.Framework forwards cache operations as MMIO traps
> into user space. For MMIO however, these have no meaning: There is no
> cache attached to them.
>
> So let's filter SYS instructions for DATA exits out and treat them as nops.
>
> Thi
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to leverage the extension. A
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many programmable counters should be implemented b
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Signed-off-by: Atish Patra
---
target/riscv/csr.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv
On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote:
> The code to check command policy can see special feature flag
> 'deprecated' as command flag QCO_DEPRECATED. I want to make feature
> flag 'unstable' visible there as well, so I can add policy for it.
>
> To let me make it visible, add m
On 10/25/21 12:11 PM, Luis Pires wrote:
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
tests/unit/meson.build | 1 +
tests/unit/test-div128.c | 197 +++
2 files changed, 198 insertions(+)
create mode 100644 tests/unit/test-div128.c
I
On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote:
> The generated visitor functions call visit_deprecated_accept() and
> visit_deprecated() when visiting a struct member with special feature
> flag 'deprecated'. This makes the feature flag visible to the actual
> visitors. I want to make
Move the following instructions to decodetree:
ddedpd: DFP Decode DPD To BCD
ddedpdq: DFP Decode DPD To BCD Quad
denbcd: DFP Encode BCD To DPD
denbcdq: DFP Encode BCD To DPD Quad
dscli: DFP Shift Significand Left Immediate
dscliq: DFP Shift Significand Left Immediate Quad
dscri: DFP Shift Si
On 10/25/21 8:47 AM, Philippe Mathieu-Daudé wrote:
On 10/25/21 14:28, Frédéric Pétrot wrote:
Addition of not, xor, div and rem on 128-bit integers, used in particular
within div/rem and csr helpers for computations on 128-bit registers in
the 128-bit riscv target.
Signed-off-by: Frédéric Pétrot
On 10/25/21 5:28 AM, Frédéric Pétrot wrote:
-MO_LEQ = MO_LE | MO_Q,
+MO_LEQ = MO_LE | MO_UQ,
Again, I mentioned that this would require renaming as well...
-MO_BEQ = MO_BE | MO_Q,
+MO_BEQ = MO_BE | MO_UQ,
... and this...
+MO_TEUQ = MO_TE | MO_UQ,
MO_TESW
Move the following instructions to decodetree:
dctdp: DFP Convert To DFP Long
dctqpq: DFP Convert To DFP Extended
drsp:DFP Round To DFP Short
drdpq: DFP Round To DFP Long
dcffix: DFP Convert From Fixed
dcffixq: DFP Convert From Fixed Quad
dctfix: DFP Convert To Fixed
dctfixq: DFP Convert
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Signed-off-by: Atish Patra
---
target/riscv/cpu_helper.c | 26 ++
1 file changed, 26 inserti
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 4
target/riscv/csr.c | 25 +
target/riscv/machine.c | 5 +++--
4
Move the following instructions to decodetree:
dqua: DFP Quantize
dquaq: DFP Quantize Quad
drrnd: DFP Reround
drrndq: DFP Reround Quad
Signed-off-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c | 8 ++---
target/ppc
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as well.
Signed-off-by: A
The latest version of the SBI specification includes a Performance Monitoring
Unit(PMU) extension[1] which allows the supervisor to start/stop/configure
various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level
extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Fil
With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 12 ++
target/riscv/csr.c | 468 ++
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Signed-off-by: Atish Patra
--
mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.
Support mcycle/minstret through generic coun
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Signed-off-by: Atish Patra
---
target/riscv/c
Implement the following PowerISA v3.1 instruction:
dctfixqq: DFP Convert To Fixed Quadword Quad
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c | 52 +
target/ppc/helper.h | 1 +
target/ppc/insn32.deco
On 25.10.21 17:10, Daniel P. Berrangé wrote:
On Mon, Oct 25, 2021 at 04:53:57PM +0200, Alexander Graf wrote:
On 25.10.21 16:47, Daniel P. Berrangé wrote:
On Mon, Oct 25, 2021 at 04:42:22PM +0200, Alexander Graf wrote:
On 25.10.21 16:22, Daniel P. Berrangé wrote:
On Mon, Oct 25, 2021 at 12:1
This will be used to implement PowerPC's dctfixqq.
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
include/libdecnumber/decNumber.h | 2 +
include/libdecnumber/decNumberLocal.h | 2 +-
libdecnumber/decContext.c | 7 +-
libdecnumber/decNumber.c | 95
On Mon, Oct 25, 2021 at 1:26 AM Markus Armbruster wrote:
> New option parameters unstable-input and unstable-output set policy
> for unstable interfaces just like deprecated-input and
> deprecated-output set policy for deprecated interfaces (see commit
> 6dd75472d5 "qemu-options: New -compat to s
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
include/qemu/host-utils.h | 36
1 file changed, 36 insertions(+)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index a3a7ced78d..ca979dc6cc 100644
--- a/include/qemu/host-utils
On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote:
> The code to check policy for handling deprecated input is triplicated.
> Factor it out into compat_policy_input_ok() before I mess with it in
> the next commit.
>
> Signed-off-by: Markus Armbruster
>
(Skipping C-only patches for quick
On Mon, Oct 25, 2021 at 1:26 AM Markus Armbruster wrote:
> The code to check enumeration value policy can see special feature
> flag 'deprecated' in QEnumLookup member flags[value]. I want to make
> feature flag 'unstable' visible there as well, so I can add policy for
> it.
>
> Instead of exten
From: Fernando Valle
Signed-off-by: Fernando Valle
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
target/ppc/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c2fafebd1c..48a484eef6 100644
--- a/target/p
On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote:
> New enum QapiSpecialFeature enumerates the special feature flags.
>
> New helper gen_special_features() returns code to represent a
> collection of special feature flags as a bitset.
>
> The next few commits will put them to use.
>
> Sign
From: Bruno Larsen
Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR.
Signed-off-by: Bruno Larsen
Signed-off-by: Matheus Ferst
Signed-off-by: Fernando Valle
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
Acked-by: David Gibson
---
target/ppc/translate.c
Move the following instructions to decodetree:
dcmpu:DFP Compare Unordered
dcmpuq: DFP Compare Unordered Quad
dcmpo:DFP Compare Ordered
dcmpoq: DFP Compare Ordered Quad
dtstex: DFP Test Exponent
dtstexq: DFP Test Exponent Quad
dtstsf: DFP Test Significance
dtstsfq: DFP Test Signif
Move the following instructions to decodetree:
dquai: DFP Quantize Immediate
dquaiq: DFP Quantize Immediate Quad
drintx: DFP Round to FP Integer With Inexact
drintxq: DFP Round to FP Integer With Inexact Quad
drintn: DFP Round to FP Integer Without Inexact
drintnq: DFP Round to FP Integer With
This will be used to implement PowerPC's dcffixqq.
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
include/libdecnumber/decNumber.h | 2 ++
libdecnumber/decNumber.c | 36
2 files changed, 38 insertions(+)
diff --git a/include/libdecnumber/
Move the following instructions to decodetree:
dadd: DFP Add
daddq: DFP Add Quad
dsub: DFP Subtract
dsubq: DFP Subtract Quad
dmul: DFP Multiply
dmulq: DFP Multiply Quad
ddiv: DFP Divide
ddivq: DFP Divide Quad
diex: DFP Insert Biased Exponent
diexq: DFP Insert Biased Exponent Quad
Signed-off-b
Apple's Hypervisor.Framework forwards cache operations as MMIO traps
into user space. For MMIO however, these have no meaning: There is no
cache attached to them.
So let's filter SYS instructions for DATA exits out and treat them as nops.
This fixes OpenBSD booting as guest.
Signed-off-by: Alexa
Before moving the existing DFP instructions to decodetree, drop the
nip update that shouldn't be done for these instructions.
Signed-off-by: Luis Pires
---
target/ppc/translate/dfp-impl.c.inc | 8
1 file changed, 8 deletions(-)
diff --git a/target/ppc/translate/dfp-impl.c.inc
b/target
Move the following instructions to decodetree:
dtstdc: DFP Test Data Class
dtstdcq: DFP Test Data Class Quad
dtstdg: DFP Test Data Group
dtstdgq: DFP Test Data Group Quad
Signed-off-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
tests/unit/meson.build | 1 +
tests/unit/test-div128.c | 197 +++
2 files changed, 198 insertions(+)
create mode 100644 tests/unit/test-div128.c
diff --git a/tests/unit/meson.build b/tests/unit
In preparation for changing the divu128/divs128 implementations
to allow for quotients larger than 64 bits, move the div-by-zero
and overflow checks to the callers.
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
include/hw/clock.h| 5 +++--
include/qemu/host-utils.h | 36
These will be used to implement new decimal floating point
instructions from Power ISA 3.1.
The remainder is now returned directly by divu128/divs128,
freeing up phigh to receive the high 64 bits of the quotient.
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
include/hw/clock.h
Implement the following PowerISA v3.1 instruction:
dcffixqq: DFP Convert From Fixed Quadword Quad
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c | 12
target/ppc/helper.h | 1 +
target/ppc/insn32.decode|
Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils,
so it can be reused by divu128().
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
include/fpu/softfloat-macros.h | 82 --
include/qemu/host-utils.h | 81 +++
This series moves all existing DFP instructions to decodetree and
implements the 2 new instructions (dcffixqq and dctfixqq) from
Power ISA 3.1.
In order to implement dcffixqq, divu128/divs128 were modified to
support 128-bit quotients (previously, they were limited to 64-bit
quotients), along with
On 10/25/21 5:28 AM, Frédéric Pétrot wrote:
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu
On 25.10.21 19:11, Paolo Bonzini wrote:
On 25/10/21 10:25, Alexander Graf wrote:
HVF has generic memory listener code that adds all RAM regions as HVF
RAM
regions. However, HVF can only handle page aligned, page granule
regions.
So let's ignore regions that are not page aligned and sized. T
On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote:
> Signed-off-by: Markus Armbruster
> ---
> include/qapi/qmp/dispatch.h | 1 -
> monitor/misc.c | 3 +--
> scripts/qapi/commands.py| 5 +
> 3 files changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/include/qapi
On 10/25/21 5:28 AM, Frédéric Pétrot wrote:
Introduction of a gen_logic function for bitwise logic to implement
instructions in which not propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Po
On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote:
> Add special feature 'unstable' everywhere the name starts with 'x-',
> except for InputBarrierProperties member x-origin and
> MemoryBackendProperties member x-use-canonical-path-for-ramblock-id,
> because these two are actually stable.
>
NDNF writes:
> These patches adds the ability to generate files in drcov format.
> Primary goal this scripts is to have coverage
> logfiles thatwork in Lighthouse.
Queued with some fixes to plugins/next, thanks.
--
Alex Bennée
On Mon, Oct 25, 2021 at 1:26 AM Markus Armbruster wrote:
> By convention, names starting with "x-" are experimental. The parts
> of external interfaces so named may be withdrawn or changed
> incompatibly in future releases.
>
> Drawback: promoting something from experimental to stable involves a
From: Richard Henderson
> > A new argument, prem, was added to divu128/divs128 to receive the
> > remainder, freeing up phigh to receive the high 64 bits of the
> > quotient.
> >
> > Signed-off-by: Luis Pires
>
> Why not return the remainder? That would avoid the need for an extra
> argument, a
From: Richard Henderson
> On 9/10/21 4:26 AM, Luis Pires wrote:
> > +&Z22_bf_fra bf fra dm
> > +@Z22_bf_fra .. bf:3 .. fra:5 dm:6 . . &Z22_bf_fra
> > +
> > +%z22_frap 17:4 !function=times_2
> > +@Z22_bf_frap.. bf:3 .. 0 dm:6 . . &Z2
From: Richard Henderson
> > +static void set_dfp128_to_avr(ppc_avr_t *dst, ppc_vsr_t *src) {
> > +dst->VsrD(0) = src->VsrD(0);
> > +dst->VsrD(1) = src->VsrD(1);
> > +}
>
> Given that these two are typedef of one another, I would think this is
> unnecessary and you should just write *dst
* Dr. David Alan Gilbert (git) (dgilb...@redhat.com) wrote:
> From: "Dr. David Alan Gilbert"
>
> Make the '--socket-group=' option fail if the group name is unknown:
>
> ./tools/virtiofsd/virtiofsd --socket-group=zaphod
> vhost socket: unable to find group 'zaphod'
>
> Reported-by: Xiaolin
On 10/25/21 10:36 AM, Alexey Baturo wrote:
+/* User Pointer Masking */
+[CSR_UMTE]={ "umte",pointer_masking, read_umte,write_umte
},
+[CSR_UPMMASK] ={ "upmmask", pointer_masking, read_upmmask,
write_upmmask },
+[CSR_UPMBASE] ={ "upmbase", pointer_maski
* Vivek Goyal (vgo...@redhat.com) wrote:
> On Thu, Oct 14, 2021 at 01:25:54PM +0100, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > Make the '--socket-group=' option fail if the group name is unknown:
> >
> > ./tools/virtiofsd/virtiofsd --socket-group=zaphod
On 10/25/21 11:13 AM, Luis Fernando Fujita Pires wrote:
From: Richard Henderson
static bool fold_eqv(OptContext *ctx, TCGOp *op) {
-return fold_const2(ctx, op);
+if (fold_const2(ctx, op) ||
+fold_xi_to_not(ctx, op, 0)) {
Should be fold_ix_to_not (not fold xi_to_not).
No
From: Richard Henderson
> >> static bool fold_eqv(OptContext *ctx, TCGOp *op) {
> >> -return fold_const2(ctx, op);
> >> +if (fold_const2(ctx, op) ||
> >> +fold_xi_to_not(ctx, op, 0)) {
> >
> > Should be fold_ix_to_not (not fold xi_to_not).
>
> No, because for eqv we expect the
* Vivek Goyal (vgo...@redhat.com) wrote:
> Hi,
>
> Here are the patches to support notification queue and blocking
> posix locks. One of the biggest change since las time has been
> creation of custom thread pool for handling locking requests.
> Thanks to Ioannis for doing most of the work on cus
* Vivek Goyal (vgo...@redhat.com) wrote:
> Right now for xattr remapping, we support types of "prefix", "ok" or "bad".
> Type "bad" returns -EPERM on setxattr and hides xattr in listxattr. For
> getxattr, mapping code returns -EPERM but getxattr code converts it to
> -ENODATA.
>
> I need a new se
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