On 11/08/2021 13.08, Peter Maydell wrote:
On Wed, 11 Aug 2021 at 11:00, Thomas Huth wrote:
The vhost-user-blk-test currently hangs if QTEST_QEMU_STORAGE_DAEMON_BINARY
points to a non-existing binary. Let's improve this situation by checking
for the availability of the binary first, so we can f
The fp5280g2-bmc is supported by OpenBMC, It's
based on the following device tree
https://github.com/openbmc/linux/blob/dev-5.10/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
Signed-off-by: John Wang
---
hw/arm/aspeed.c | 74 +
1 file changed,
On 13/10/2021 19.00, Paolo Bonzini wrote:
On 13/10/21 13:27, Thomas Huth wrote:
+def fixup_options(options):
+ # Meson <= 0.60 does not include the choices in array options, fix
that up
+ for opt in options:
+ if opt["name"] == "trace_backends":
+ opt["choices"] = [
+
On 13/10/2021 21.50, Eric Auger wrote:
Add the framework to test the virtio-iommu-pci device
and tests exercising the attach/detach, map/unmap API.
Signed-off-by: Eric Auger
---
...
+/**
+ * send_map - Send a map command to the device
+ * @domain: domain the new binding is attached to
+ * @v
On Thu, Oct 14, 2021 at 5:30 AM Jason Wang wrote:
>
> On Tue, Oct 12, 2021 at 10:07 PM Eugenio Pérez wrote:
> >
> > Check vdpa device range before updating memory regions so we don't add
> > any outside of it, and report the invalid change if any.
> >
> > Signed-off-by: Eugenio Pérez
> > ---
> >
On 2021/10/14 上午4:50, Richard Henderson wrote:
We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less. Use a switch and explicitly
bound both SEW and SEQ for all cases.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Zhiwei
---
target/riscv/insn_trans/
On 2021/10/14 上午4:50, Richard Henderson wrote:
Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Zhiwei
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 inse
On Wed, Oct 13, 2021 at 11:51:24AM +0200, David Hildenbrand wrote:
> On 13.10.21 11:48, Stefan Hajnoczi wrote:
> > On Tue, Oct 12, 2021 at 08:38:32PM +0200, David Hildenbrand wrote:
> > > We end up not closing the file descriptor, resulting in leaking one
> > > file descriptor for each VHOST_USER_R
On Wed, Oct 13, 2021 at 10:40:46AM +0100, Stefan Hajnoczi wrote:
> On Mon, Oct 11, 2021 at 10:10:47PM +0200, David Hildenbrand wrote:
> > We end up not copying the mmap_addr of all existing regions, resulting
> > in a SEGFAULT once we actually try to map/access anything within our
> > memory region
The vhost-user-blk-test qtest has been hanging intermittently for a
while. The root cause is not yet fully understood, but the hang is
impacting enough users that it is important to merge a workaround for
it.
The race which causes the hang occurs early on in vhost-user setup,
where a vhost-user me
On Tue, Oct 12, 2021 at 10:07 PM Eugenio Pérez wrote:
>
> Check vdpa device range before updating memory regions so we don't add
> any outside of it, and report the invalid change if any.
>
> Signed-off-by: Eugenio Pérez
> ---
> include/hw/virtio/vhost-vdpa.h | 2 ++
> hw/virtio/vhost-vdpa.c
On 10/13/21 3:51 PM, Stefan Berger wrote:
Clarify the command line parameters for vTPM migration acros the network
fro the case of shared storage and non-shared storage.
Please ignore in favor of v2.
Clarify the command line parameters for swtpm migration across the network
for the case of shared storage and non-shared storage.
Signed-off-by: Stefan Berger
---
docs/specs/tpm.rst | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst
inde
在 2021/10/8 下午9:34, Kevin Wolf 写道:
vhost-vdpa works only with specific devices. At startup, it second
guesses what the command line option handling will do and error out if
it thinks a non-virtio device will attach to them.
This second guessing is not only ugly, it can lead to wrong error
mess
在 2021/10/8 下午9:34, Kevin Wolf 写道:
vhost-user works only with specific devices. At startup, it second
guesses what the command line option handling will do and error out if
it thinks a non-virtio device will attach to them.
This second guessing is not only ugly, it can lead to wrong error
mess
在 2021/10/8 下午9:34, Kevin Wolf 写道:
Some network backends (vhost-user and vhost-vdpa) work only with
specific devices. At startup, they second guess what the command line
option handling will do and error out if they think a non-virtio device
will attach to them.
This second guessing is not onl
From: Keno Fischer
Signed-off-by: Keno Fischer
Signed-off-by: Will Cohen
---
hw/9pfs/9p.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c
index 97dc8b246f..3fc43cb482 100644
--- a/hw/9pfs/9p.c
+++ b/hw/9pfs/9p.c
@@ -3927,6 +3927,14 @@ out_nofid:
v9f
From: Keno Fischer
Signed-off-by: Keno Fischer
Signed-off-by: Michael Roitzsch
---
fsdev/meson.build | 1 +
meson.build | 17 ++---
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/fsdev/meson.build b/fsdev/meson.build
index adf57cc43e..b632b66348 100644
--- a
From: Keno Fischer
Darwin does not support mknodat. However, to avoid race conditions
with later setting the permissions, we must avoid using mknod on
the full path instead. We could try to fchdir, but that would cause
problems if multiple threads try to call mknodat at the same time.
However, lu
From: Keno Fischer
On darwin `fgetxattr` takes two extra optional arguments,
and the l* variants are not defined (in favor of an extra
flag to the regular variants.
Signed-off-by: Keno Fischer
Reviewed-by: Greg Kurz
---
hw/9pfs/9p-local.c | 12
hw/9pfs/9p-util.h | 17 +++
From: Keno Fischer
Darwin doesn't have either of these flags. Darwin does have
F_NOCACHE, which is similar to O_DIRECT, but has different
enough semantics that other projects don't generally map
them automatically. In any case, we don't support O_DIRECT
on Linux at the moment either.
Signed-off-
From: Keno Fischer
On darwin d_seekoff exists, but is optional and does not seem to
be commonly used by file systems. Use `telldir` instead to obtain
the seek offset.
Signed-off-by: Keno Fischer
Signed-off-by: Michael Roitzsch
---
hw/9pfs/9p-synth.c | 2 ++
hw/9pfs/9p.c | 33 ++
From: Keno Fischer
- Guard Linux only headers.
- Add qemu/statfs.h header to abstract over the which
headers are needed for struct statfs
- Define `ENOATTR` only if not only defined
(it's defined in system headers on Darwin).
Signed-off-by: Keno Fischer
---
fsdev/file-op-9p.h| 2
From: Keno Fischer
This function is new in Mac OS 10.13. Provide a fallback implementation
when building against older SDKs. The complication in the definition comes
having to separately handle the used SDK version and the target OS version.
- If the SDK version is too low (__MAC_10_13 not defin
This is a continuation of a patch series adding 9p server support for Darwin,
originally submitted by Keno Fischer in mid-2018
(https://lists.nongnu.org/archive/html/qemu-devel/2018-06/msg04643.html). In
some sense, this could be considered [PATCH v4] of that process, but I assume
that the multi-ye
This is a continuation of a patch series adding 9p server support for Darwin,
originally submitted by Keno Fischer in mid-2018
(https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg04643.html).
It has since been updated and rebased for NixOS by Michael Roitzsch
(https://github.com/NixOS/nixpkg
From: Keno Fischer
Signed-off-by: Keno Fischer
---
hw/9pfs/9p-proxy.c | 17 ++---
hw/9pfs/9p-synth.c | 2 ++
hw/9pfs/9p.c | 16 ++--
3 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/hw/9pfs/9p-proxy.c b/hw/9pfs/9p-proxy.c
index 09bd9f1464..be1546c1b
This is a continuation of a patch series adding 9p server support for Darwin,
originally submitted by Keno Fischer in mid-2018
(https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg04643.html).
It has since been updated and rebased for NixOS by Michael Roitzsch
(https://github.com/NixOS/nixpkg
From: Keno Fischer
This implements the darwin equivalent of the functions that were
moved to 9p-util(-linux) earlier in this series in the new
9p-util-darwin file.
Signed-off-by: Keno Fischer
Signed-off-by: Michael Roitzsch
---
hw/9pfs/9p-util-darwin.c | 64 +++
Use vfio_msi_disable_common to simplify the error handling
in vfio_msi_enable.
Signed-off-by: Longpeng(Mike)
---
hw/vfio/pci.c | 16 ++--
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index a4985c0..aeeb6cd 100644
--- a/hw/vfio/pci.c
+++
From: Keno Fischer
The current file only has the Linux versions of these functions.
Rename the file accordingly and update the Makefile to only build
it on Linux. A Darwin version of these will follow later in the
series.
Signed-off-by: Keno Fischer
Signed-off-by: Michael Roitzsch
---
hw/9pfs
Hi guys,
In vfio migration resume phase, the cost would increase if the
vfio device has more unmasked vectors. We try to optimize it in
this series.
You can see the commit message in PATCH 6 for details.
Patch 1-3 are simple cleanups and fixup.
Patch 4-5 are the preparations for the optimizat
In migration resume phase, all unmasked msix vectors need to be
setup when loading the VF state. However, the setup operation would
take longer if the VM has more VFs and each VF has more unmasked
vectors.
The hot spot is kvm_irqchip_commit_routes, it'll scan and update
all irqfds that are already
Extract a common helper that add MSI route for specific vector
but does not commit immediately.
Signed-off-by: Longpeng(Mike)
---
accel/kvm/kvm-all.c | 15 +--
include/sysemu/kvm.h | 6 ++
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/acc
It's unnecessary to test against the specific return value of
VFIO_DEVICE_SET_IRQS, since any positive return is an error
indicating the number of vectors we should retry with.
Signed-off-by: Longpeng(Mike)
---
hw/vfio/pci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
Commit ecebe53fe993 ("vfio: Avoid disabling and enabling vectors
repeatedly in VFIO migration") avoids inefficiently disabling and
enabling vectors repeatedly and lets the unmasked vectors be enabled
one by one.
But we want to batch multiple routes and defer the commit, and only
commit once outsid
Move re-enabling INTX out, and the callers should decide to
re-enable it or not.
Signed-off-by: Longpeng(Mike)
---
hw/vfio/pci.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index c1fba40..a4985c0 100644
--- a/hw/vfio/pci.c
On 10/13/21 2:56 PM, Philippe Mathieu-Daudé wrote:
While for the DEXTR_S.H opcode:
"The shift argument is provided in the instruction."
For the DEXTRV_S.H opcode we have:
"The five least-significant bits of register rs provide the
shift argument, interpreted as a five-bit unsigned in
On 10/10/21 9:20 PM, WANG Xuerui wrote:
+++ b/tcg/mips/tcg-target-sa32.h
@@ -1 +1,9 @@
+/*
+ * Do not set TCG_TARGET_SIGNED_ADDR32 for mips32;
+ * TCG expects this to only be set for 64-bit hosts.
+ */
+#ifdef __mips64
+#define TCG_TARGET_SIGNED_ADDR32 1
+#else
#define TCG_TARGET_SIGNED_ADDR32
AQMP likes to be very chatty about errors it encounters. In general,
this is good because it allows us to get good diagnostic information for
otherwise complex async failures.
For example, during a failed QMP connection attempt, we might see:
+ERROR:qemu.aqmp.qmp_client.qemub-2536319:Negotiation
The scary message interferes with the iotests output. Coincidentally, if
iotests works by removing this, then it's good evidence that we don't
really need to scare people away from using it.
Signed-off-by: John Snow
Acked-by: Hanna Reitz
---
python/qemu/aqmp/__init__.py | 12
1 fil
Swap out the synchronous QEMUMonitorProtocol from qemu.qmp with the sync
wrapper from qemu.aqmp instead.
Add an escape hatch in the form of the environment variable
QEMU_PYTHON_LEGACY_QMP which allows you to cajole QEMUMachine into using
the old implementation, proving that both implementations wo
GitLab: https://gitlab.com/jsnow/qemu/-/commits/python-aqmp-iotest-wrapper
CI: https://gitlab.com/jsnow/qemu/-/pipelines/387972757
Hiya,
This series continues where the last two AQMP series left off and adds a
synchronous 'legacy' wrapper around the new AQMP interface, then drops
it straight into
This is a wrapper around the async QMPClient that mimics the old,
synchronous QEMUMonitorProtocol class. It is designed to be
interchangeable with the old implementation.
It does not, however, attempt to mimic Exception compatibility.
Signed-off-by: John Snow
Acked-by: Hanna Reitz
---
python/q
(But continue to support the old ones for now, too.)
There are very few cases of any user of QEMUMachine or a subclass
thereof relying on a QMP Exception type. If you'd like to check for
yourself, you want to grep for all of the derivatives of QMPError,
excluding 'AQMPError' and its derivatives. T
While for the DEXTR_S.H opcode:
"The shift argument is provided in the instruction."
For the DEXTRV_S.H opcode we have:
"The five least-significant bits of register rs provide the
shift argument, interpreted as a five-bit unsigned integer;
the remaining bits in rs are ignored."
While
Wait for the destination VM to close itself instead of racing to shut it
down first, which produces different error log messages from AQMP
depending on precisely when we tried to shut it down.
(For example: We may try to issue 'quit' immediately prior to the target
VM closing its QMP socket, which
If we spy on the QMP commands instead, we don't need callers to remember
to pass it. Seems like a fair trade-off.
The one slightly weird bit is overloading this instance variable for
wait(), where we use it to mean "don't issue the qmp 'quit'
command". This means that wait() will "fail" if the QEM
To use the AQMP backend, Machine just needs to be a little more diligent
about what happens when closing a QMP connection. The operation is no
longer a freebie in the async world; it may return errors encountered in
the async bottom half on incoming message receipt, etc.
(AQMP's disconnect, ultima
From: Nicholas Piggin
This implements a machine check injection framework and defines a
'mce' monitor command for ppc.
Signed-off-by: Nicholas Piggin
[ clg: - moved definition under "hw/ppc/mce.h"
- renamed to PPCMceInjection
- simplified injection call in hmp_mce
- QMP sup
From: Nicholas Piggin
This implements mce injection for pnv.
Signed-off-by: Nicholas Piggin
[ clg: - simplified injection and moved code under pnv_core.c
- removed superfluous cpu_synchronize_state()
- clear previous setting in SPR_SRR1 ]
Message-Id: <20200325144147.221875-6-npig.
From: Nicholas Piggin
This implements mce injection for spapr.
(qemu) mce 0 0x20 0x80 0xdeadbeef 1
Disabling lock debugging due to kernel taint
MCE: CPU0: machine check (Severe) Host SLB Multihit DAR: deadbeef
[Recovered]
MCE: CPU0: machine check (Severe) Host SLB Mul
Hello,
This is a rework of Nick's patchset [*] adding mce injection for spapr
and pnv.
Thanks,
C.
[*]
https://lore.kernel.org/qemu-devel/20200325144147.221875-1-npig...@gmail.com/
Changes :
- moved definition under "hw/ppc/mce.h"
- renamed to PPCMceInjection
- simplified injection call i
On Wed, Oct 13, 2021 at 03:10:38PM +0200, Damien Hedde wrote:
> > > @@ -691,7 +703,13 @@ DeviceState *qdev_device_add(QemuOpts *opts, Error
> > > **errp)
> > > }
> > > }
> > > -qdev_set_id(dev, g_strdup(qemu_opts_id(opts)));
> > > +/*
> > > + * set dev's parent and regi
This allows the programmer's switch to be triggered via the monitor for
debugging
purposes. Since the CPU level 7 interrupt is level-triggered, use a timer to
hold
the NMI active for 100ms before releasing it again.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 47 ++
Explicitly wire up the remaining IRQs in classic mode to enable the use of
g_assert_not_reached() in the default case to detect any unexpected IRQs.
Add a comment explaining the IRQ routing differences in A/UX mode based
upon the comments in NetBSD (also noting that at least A/UX 3.0.1 still
uses
This enables the GLUE logic to change its CPU level IRQ routing depending upon
whether the hardware has been configured for A/UX mode.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 81c3
Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating
whether the hardware is configured for A/UX mode.
Signed-off-by: Mark Cave-Ayland
---
hw/misc/mac_via.c | 18 ++
hw/misc/trace-events | 1 +
include/hw/misc/mac_via.h | 1 +
3 files chan
When the hardware is operating in classic mode the SONIC on-board Ethernet IRQ
is
routed to nubus IRQ 9 instead of directly to the CPU at level 3. This does not
affect the framebuffer which although it exists in slot 9, has its own
dedicated IRQ on the Quadra 800 hardware.
Signed-off-by: Mark Cav
On a Quadra 800 machine Linux sets via_alt_mapping to 1 and clears port B bit 6
to
ensure that the VIA1 IRQ is delivered at level 6 rather than level 1. Even
though
QEMU doesn't yet emulate this behaviour, Linux still installs the VIA1 level 1
IRQ
handler regardless of the value of via_alt_mappi
In order to allow dynamic routing of IRQs to different IRQ levels on the CPU
depending upon port B bit 6, use GLUE IRQ numbers and map them to the the
corresponding CPU IRQ level accordingly.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 32
1 file changed
According to both Linux and NetBSD, port B bit 6 is used on the Quadra 800 to
configure the GLUE logic in A/UX mode. Whilst the name VIA1B_vMystery isn't
particularly descriptive, the patch leaves this to ensure that the constants
in mac_via.c remain in sync with Linux's mac_via.h.
Signed-off-by:
This patchset contains a set of GLUE updates to enable switching between
so-called A/UX mode and classic mode which is required to allow the q800
machine to boot both Linux/NetBSD and MacOS.
Patch 1 updates the comment for the VIA1B_vMystery bit indicating that
VIA1 port B bit 6 is used to switch
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.
Reviewed-by: LIU Zhiwei
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvb.c.inc | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
On 10/11/21 3:28 AM, Alex Bennée wrote:
+if (TARGET_LONG_BITS == 64) {
+return 3; /* LSL #0 */
+} else if (signed_addr32) {
+return 6; /* SXTW */
+} else {
+return 2; /* UXTW */
+}
+}
If this is is going to be a magic number we pass into our code
generati
The multiply high-part instructions require a separate
implementation for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 16 +++
target/riscv/insn_trans/trans_rvm.c.inc | 26 +++
In preparation for RV128, consider more than just "w" for
operand size modification. This will be used for the "d"
insns from RV128 as well.
Rename oper_len to get_olen to better match get_xlen.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 71 -
Most shift instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 31 +
target/riscv/insn_trans/trans_rvb.c.inc | 92 ++---
target/ris
In preparation for RV128, replace a simple predicate
with a more versatile test.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c | 32 +---
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.
The count zeros instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 16
target/riscv/insn_trans/trans_rvb.c.inc | 33 -
2
Begin adding support for switching XLEN at runtime. Extract the
effective XLEN from MISA and MSTATUS and store for use during translation.
Signed-off-by: Richard Henderson
---
v2: Force SXL and UXL to valid values.
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu.c| 8
Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/targe
We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less. Use a switch and explicitly
bound both SEW and SEQ for all cases.
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 26 +
1 file changed, 14 insertions(+), 12 d
Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.
Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.
Signed-off-by: Rich
Move the function to cpu_helper.c, as it is large and growing.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu.h| 47 ++-
target/riscv/cpu_helper.c | 46 +
Move the MXL_RV* defines to enumerators.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu_bits.h | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187
The hw representation of misa.mxl is at the high bits of the
misa csr. Representing this in the same way inside QEMU
results in overly complex code trying to check that field.
Signed-off-by: Richard Henderson
---
v2: Reset misa.mxl.
---
target/riscv/cpu.h | 15 +++
linux-user/elflo
This is a partial patch set attempting to set things in the
right direction for both the UXL and RV128 patch sets.
Changes for v2:
* Set mxl/sxl/uxl at reset.
* Set sxl/uxl in write_mstatus.
r~
Richard Henderson (13):
target/riscv: Move cpu_get_tb_cpu_state out of line
target/riscv: Cr
On Mon, 11 Oct 2021 at 15:19, Gabriel L. Somlo wrote:
> Given *this* conversation, it might be worth someone's effort to try
> that approach again. IMO it's really the most efficient: have an
> already existing applesmc driver in the hypervisor's kernel expose the
> desired key values (it's whole
On 10/13/21 11:41 AM, Philipp Tomsich wrote:
The earlier implementation fell into a corner case for bytes that were
0x01, giving a wrong result (but not affecting our application test
cases for strings, as an ASCII value 0x01 is rare in those...).
This changes the algorithm to:
1. Mask out the
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211013
for you to fetch changes up to 76e366e728549b3324cc2dee6745d6a4f1af18e6:
tcg: Canonicalize alignment flags in MemOp (2021-10-13 09:14:35 -0700)
Use MO_128 for 16-byte ato
On Wed, 2021-10-13 at 16:50 +0100, Alex Bennée wrote:
> Maxim Levitsky writes:
>
> > Signed-off-by: Maxim Levitsky
> > ---
> > accel/kvm/kvm-all.c | 25 ++
> > gdbstub.c| 60
> > include/sysemu/kvm.h | 13 ++
> >
Clarify the command line parameters for vTPM migration acros the network
fro the case of shared storage and non-shared storage.
Signed-off-by: Stefan Berger
---
docs/specs/tpm.rst | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst
index
Add the framework to test the virtio-iommu-pci device
and tests exercising the attach/detach, map/unmap API.
Signed-off-by: Eric Auger
---
This applies on top of jean-Philippe's
[PATCH v4 00/11] virtio-iommu: Add ACPI support
branch can be found at:
https://github.com/eauger/qemu.git
branch qte
Remove the non transitional name for virtio iommu. Like other
devices introduced after 1.0 spec, the virtio-iommu does
not need it.
Signed-off-by: Eric Auger
Reported-by: Andrea Bolognani
Reviewed-by: Cornelia Huck
---
hw/virtio/virtio-iommu-pci.c | 1 -
1 file changed, 1 deletion(-)
diff --g
Drop base_name and turn generic_name into
"virtio-iommu-pci". This is more in line with
other modern-only devices.
Signed-off-by: Eric Auger
Suggested-by: Cornelia Huck
Reviewed-by: Cornelia Huck
---
hw/virtio/virtio-iommu-pci.c | 3 +--
include/hw/virtio/virtio-iommu.h | 2 +-
2 files cha
This small series removes the non transitional name, drop the base_name
and change the generic_name into "virtio-iommu-pci".
History:
v2 -> v3:
- fixed duplicate in commit msg
- added Connie's R-b
v1 -> v2:
- drop the base_name and change the generic_name into "virtio-iommu-pci"
(Connie)
E
ping
On Wed, Sep 29, 2021 at 2:40 PM Konstantin Kostiuk
wrote:
> ping
>
> On Tue, Sep 14, 2021 at 3:14 PM Kostiantyn Kostiuk
> wrote:
>
>> Windows Server 2016, 2019, 2022 are based on Windows 10 and
>> have the same major and minor versions. So, the only way to
>> detect the proper version is t
On Wed, Oct 13, 2021 at 8:41 PM Philipp Tomsich
wrote:
>
> The earlier implementation fell into a corner case for bytes that were
> 0x01, giving a wrong result (but not affecting our application test
> cases for strings, as an ASCII value 0x01 is rare in those...).
>
> This changes the algorithm t
* David Hildenbrand (da...@redhat.com) wrote:
> Based-on: 20211011175346.15499-1-da...@redhat.com
>
> A virtio-mem device is represented by a single large RAM memory region
> backed by a single large mmap.
>
> Right now, we map that complete memory region into guest physical addres
> space, resul
As qemu guidelines:
Unless a pointer is used to modify the pointed-to storage, give it the
"const" attribute.
In the particular case of iova_tree_find it allows to enforce what is
requested by its comment, since the compiler would shout in case of
modifying or freeing the const-qualified returned
Some guidelines misses I found while working on Shadow Virtqueue, that
uses these functions at this moment.
v2:
* Add a missed const in iova_tree_find_address.
Eugenio Pérez (1):
util: Make some iova_tree parameters const
include/qemu/iova-tree.h | 8
hw/i386/intel_iommu.c| 2 +
On Wed, Oct 13, 2021 at 12:21 AM Philippe Mathieu-Daudé
wrote:
>
> On 10/12/21 17:50, Eugenio Pérez wrote:
> > As qemu guidelines:
> > Unless a pointer is used to modify the pointed-to storage, give it the
> > "const" attribute.
> >
> > In the particular case of iova_tree_find it allows to enforce
https://gitlab.com/rth7680/qemu.git tags/pull-axp-20211013
for you to fetch changes up to 5ffcb33426aaa2906daea2eee7a5195662a6580f:
target/alpha: Reorg integer memory operations (2021-10-13 09:18:23 -0700)
Cleanup alpha memory op
Having observed e.g. al8+leq in dumps, canonicalize to al+leq.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index b1cfd36f29..61b492d89f 100644
--- a/tc
The earlier implementation fell into a corner case for bytes that were
0x01, giving a wrong result (but not affecting our application test
cases for strings, as an ASCII value 0x01 is rare in those...).
This changes the algorithm to:
1. Mask out the high-bit of each bytes (so that each byte is <=
The helper_*_mmu functions were the only thing available
when this code was written. This could have been adjusted
when we added cpu_*_mmuidx_ra, but now we can most easily
use the newest set of interfaces.
Cc: qemu-...@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Hender
The helper_*_mmu functions were the only thing available
when this code was written. This could have been adjusted
when we added cpu_*_mmuidx_ra, but now we can most easily
use the newest set of interfaces.
Reviewed-by: David Hildenbrand
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richar
These functions are much closer to the softmmu helper
functions, in that they take the complete MemOpIdx,
and from that they may enforce required alignment.
The previous cpu_ldst.h functions did not have alignment info,
and so did not enforce it. Retain this by adding MO_UNALN to
the MemOp that w
We should not have been using the helper_ret_* set of
functions, as they are supposed to be private to tcg.
Nor should we have been using the plain cpu_*_data set
of functions, as they do not handle unwinding properly.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tar
1 - 100 of 317 matches
Mail list logo
