Re: [PATCH] memory: remove incorrect RCU comment for address_space_read()

On 09/09/21 16:10, Stefan Hajnoczi wrote: Although the doc comment says "Called within RCU critical section" the address_space_read() function takes the RCU read lock itself. There is no need for the caller to hold an RCU read lock. Cc: Paolo Bonzini Fixes: b2a44fcad74f1cc7a6786d38eba7db12ab235

Re: [PATCH v3 21/30] target/ppc: Introduce PowerPCCPUClass::has_work()

On 9/3/21 11:11 PM, Philippe Mathieu-Daudé wrote: > On 9/3/21 10:42 PM, Richard Henderson wrote: >> On 9/3/21 2:50 AM, David Gibson wrote: >>> On Thu, Sep 02, 2021 at 06:15:34PM +0200, Philippe Mathieu-Daudé wrote: Each POWER cpu has its own has_work() implementation. Instead of overloadi

Re: [PATCH RFC server v2 01/11] vfio-user: build library

On Fri, Sep 10, 2021 at 05:20:09PM +0200, Philippe Mathieu-Daudé wrote: > On 8/27/21 7:53 PM, Jagannathan Raman wrote: > > add the libvfio-user library as a submodule. build it as a cmake > > subproject. > > > > Signed-off-by: Elena Ufimtseva > > Signed-off-by: John G Johnson > > Signed-off-by:

Re: [PULL 6/7] tests/tcg: skip the signals test for hppa/s390x for now

On Fri, Jun 25, 2021 at 11:21 AM Alex Bennée wrote: > > There are fixes currently in flight but as this is getting in the way > of a green CI we might as well skip for now. For reference the fix > series are: > > linux-user: Move signal trampolines to new page > 20210616011209.1446045-1-richar

Re: tcg: pointer size warning on x32 arch

On 9/11/21 11:06 PM, Philippe Mathieu-Daudé wrote: > On 9/11/21 7:50 PM, Michael Tokarev wrote: >> Hi. >> >> The following warning is reported by the C compiler when compiling >> tcg code on x32 architecture: >> >> In file included from ../../tcg/tcg.c:429: >> tcg/i386/tcg-target.c.inc: In function

Re: tcg: pointer size warning on x32 arch

On 9/11/21 7:50 PM, Michael Tokarev wrote: > Hi. > > The following warning is reported by the C compiler when compiling > tcg code on x32 architecture: > > In file included from ../../tcg/tcg.c:429: > tcg/i386/tcg-target.c.inc: In function ‘tcg_out_movi_int’: > tcg/i386/tcg-target.c.inc:959:30: w

tcg: pointer size warning on x32 arch

Hi. The following warning is reported by the C compiler when compiling tcg code on x32 architecture: In file included from ../../tcg/tcg.c:429: tcg/i386/tcg-target.c.inc: In function ‘tcg_out_movi_int’: tcg/i386/tcg-target.c.inc:959:30: warning: cast to pointer from integer of different size [-

[PATCH v2] linux-user: Correct host errno for IP[V6]_RECVERR socket options

Host errno must be converted to target errno in IP_RECVERR and IPV6_RECVERR socket options. Fixes: ee1ac3a1822 ("linux-user: Add sockopts for IPv6") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/602 Reported-by: Conrad Meyer Signed-off-by: Philippe Mathieu-Daudé --- v2: Corrected patch

[PATCH v3 18/24] target/riscv: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.h| 2 +- target/riscv/cpu.c| 2 +- target/riscv/cpu_helper.c | 5 - 3 files cha

[PATCH v3 24/24] user: Remove cpu_get_pic_interrupt() stubs

cpu_get_pic_interrupt() is now unreachable from user-mode, delete the unnecessary stubs. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.h | 2 +- bsd-user/i386/target_arch_cpu.c | 5 - bsd-user/x86_64/targ

[PATCH v3 16/24] target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/openrisc/cpu.h | 5 +++-- target/openrisc/cpu.c | 2 +- target/openrisc/interrupt.c | 2 -- target/openrisc/meson.build

[PATCH v3 22/24] target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/cpu.h| 4 ++-- target/xtensa/cpu.c| 2 +- target/xtensa/exc_helper.c | 7 ++- 3 files changed, 5 insertio

[PATCH v3 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu

All targets call TCGCPUOps::cpu_exec_interrupt() from sysemu code. Move its declaration to restrict it to system emulation. Extend the code guarded. Restrict the static inlined need_replay_interrupt() method to avoid a "defined but not used" warning. Reviewed-by: Richard Henderson Signed-off-by:

[PATCH v3 21/24] target/rx: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/rx/cpu.h| 2 ++ target/rx/cpu.c| 2 +- target/rx/helper.c | 4 3 files changed, 7 insertions(+), 1 deletion(-) diff --

[PATCH v3 19/24] target/sh4: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/cpu.h| 4 ++-- target/sh4/cpu.c| 2 +- target/sh4/helper.c | 9 ++--- 3 files changed, 5 insertions(+), 10 deletions

[PATCH v3 15/24] target/nios2: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/nios2/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 5

[PATCH v3 13/24] target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.h| 2 ++ target/microblaze/cpu.c| 2 +- target/microblaze/helper.c | 13 ++--- 3 files changed, 5 i

[PATCH v3 20/24] target/sparc: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index da6

[PATCH v3 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder

Following the logic of commit 30493a030ff ("i386: split seg_helper into user-only and sysemu parts"), move x86_cpu_exec_interrupt() under sysemu/seg_helper.c. Reviewed-by: Richard Henderson Reviewed-By: Warner Losh Signed-off-by: Philippe Mathieu-Daudé --- target/i386/tcg/seg_helper.c|

[PATCH v3 09/24] target/hppa: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/cpu.h| 4 ++-- target/hppa/cpu.c| 2 +- target/hppa/int_helper.c | 7 ++- 3 files changed, 5 insertions(+),

[PATCH v3 12/24] target/m68k: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/m68k/cpu.h | 2 ++ target/m68k/cpu.c | 2 +- target/m68k/op_helper.c | 16 +++- 3 files changed, 6 inserti

[PATCH v3 17/24] target/ppc: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Acked-by: David Gibson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/cpu.h | 4 ++-- target/ppc/cpu_init.c| 2 +- target/ppc/excp_helper.c | 21 +++

[PATCH v3 08/24] target/cris: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/cris/cpu.h| 2 +- target/cris/cpu.c| 4 ++-- target/cris/helper.c | 17 ++--- 3 files changed, 5 insertions(+)

[PATCH v3 07/24] target/arm: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 3 +-- target/arm/cpu.c | 7 +-- target/arm/cpu_tcg.c | 6 +++--- 3 files changed, 9 insertions(+), 7 deleti

[PATCH v3 06/24] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.h| 2 +- target/alpha/cpu.c| 2 +- target/alpha/helper.c | 5 ++--- 3 files changed, 4 insertions(+), 5 deletions(

[PATCH v3 14/24] target/mips: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/tcg-internal.h | 5 +++-- target/mips/cpu.c | 2 +- target/mips/tcg/exception.c | 18 -

[PATCH v3 05/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt

do_interrupt() is sysemu specific. However due to some X86 specific hack, it is also used in user-mode emulation, which is why it couldn't be restricted to CONFIG_SOFTMMU (see the comment around added in commit 78271684719: "cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"). Keep th

[PATCH v3 02/24] target/i386: Restrict sysemu-only fpu_helper helpers

Restrict some sysemu-only fpu_helper helpers (see commit 83a3d9c7402: "i386: separate fpu_helper sysemu-only parts"). Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targe

[PATCH v3 04/24] target/xtensa: Restrict do_transaction_failed() to sysemu

The do_transaction_failed() is restricted to system emulation since commit cbc183d2d9f ("cpu: move cc->transaction_failed to tcg_ops"). Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/cpu.h | 2 ++ 1 file changed, 2 insertions(+)

[PATCH v3 10/24] target/i386: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/tcg/helper-tcg.h | 2 ++ target/i386/tcg/seg_helper.c | 10 ++ target/i386/tcg/tcg-cpu.c| 2 +- 3 files changed,

[PATCH v3 03/24] target/i386: Simplify TARGET_X86_64 #ifdef'ry

Merge two TARGET_X86_64 consecutive blocks. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/tcg/seg_helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_h

[PATCH v3 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition

Commit f1c671f96cb ("target/avr: Introduce basic CPU class object") added to target/avr/cpu.h: #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" #endif Remove the CONFIG_USER_ONLY definition introduced by mistake in commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.

[PATCH v3 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu

[Series fully reviewed] Hi, The TCGCPUOps::cpu_exec_interrupt() handler is specific to system emulation. This series remove it from user-mode. To do so we have to deal with a x86-hack first, then we restrict each target handler (one target at a time) and finally we restrict the prototype, simplif

Re: simple serial device emulation

On Sat, 11 Sep 2021 at 17:24, Peter Maydell wrote: > On Fri, 10 Sept 2021 at 22:51, Philippe Mathieu-Daudé > wrote: > > > > On 9/10/21 9:35 PM, Hinko Kocevar wrote: > > > I have an emulated MMIO area holding couple of registers that deal with > > > serial UART. Very simple access to the Tx and R

Re: [PULL 00/42] bsd-user updates to run hello world

On Fri, 10 Sept 2021 at 21:32, wrote: > > From: Warner Losh > > The following changes since commit a61c30b8c8c3c8619847cfaa289233cc696f5689: > > Merge remote-tracking branch 'remotes/mjt/tags/patch-fetch' into staging > (2021-09-07 10:15:48 +0100) > > are available in the Git repository at: >

[PATCH] docs/system/riscv: sifive_u: Update U-Boot instructions

In U-Boot v2021.07 release, there were 2 major changes for the SiFive Unleashed board support: - Board config name was changed from sifive_fu540_defconfig to sifive_unleashed_defconfig - The generic binman tool was used to generate the FIT image (combination of U-Boot proper, DTB and OpenSBI f

Re: simple serial device emulation

On Fri, 10 Sept 2021 at 22:51, Philippe Mathieu-Daudé wrote: > > On 9/10/21 9:35 PM, Hinko Kocevar wrote: > > I have an emulated MMIO area holding couple of registers that deal with > > serial UART. Very simple access to the Tx and Rx registers from the > > userspace point of view involves polling

Re: Implementing isochronous transfers in hw/hcd-ohci.c

> On Sep 11, 2021, at 5:46 AM, Howard Spoelstra wrote: > > > > On Fri, Sep 10, 2021 at 9:23 PM Programmingkid > wrote: > > > > On Sep 10, 2021, at 7:51 AM, BALATON Zoltan wrote: > > > > On Fri, 10 Sep 2021, Howard Spoelstra wrote: > >> On Fri, Sep 10, 2021 at 7:07 AM Gerd Hoffmann wro

Re: [PATCH 3/4] hw/dma: sifive_pdma: allow non-multiple transaction size transactions

On Fri, Sep 10, 2021 at 1:56 PM wrote: > > From: Green Wan > > Real PDMA is able to deal with non-multiple transaction size transactions. > > The following result is PDMA tested in U-boot on Unmatched board: %s/U-boot/U-Boot > > => mw.l 0x300 0x0 <= Disclaim channel 0 >

Re: [PATCH 4/4] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer

On Fri, Sep 10, 2021 at 1:59 PM wrote: > > From: Frank Chang > > Real PDMA doesn't set Control.error if there are 0 bytes to be nits: 0 byte Please fix the commit title as well > transferred. The DMA transfer is still success. > > The following result is PDMA tested in U-boot on Unmatched board

Re: [PATCH 2/4] hw/dma: sifive_pdma: claim bit must be set before DMA transactions

On Fri, Sep 10, 2021 at 1:58 PM wrote: > > From: Frank Chang > > Real PDMA must have Control.claim bit to be set before > Control.run bit is set to start any DMA transactions. > Otherwise nothing will be transferred. > > The following result is PDMA tested in U-boot on Unmatched board: %s/U-boot

Re: [PATCH 1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set

On Sat, Sep 11, 2021 at 9:12 PM Bin Meng wrote: > > On Sat, Sep 11, 2021 at 8:37 PM Bin Meng wrote: > > > > On Fri, Sep 10, 2021 at 1:56 PM wrote: > > > > > > From: Frank Chang > > > > > > Setting Control.claim clears all of the chanel's Next registers. > > > This is effective only when Control

[PATCH v11 10/16] target/riscv: Reassign instructions to the Zbb-extension

This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis

[PATCH v11 09/16] target/riscv: Add instructions of the Zbc-extension

The following instructions are part of Zbc: - clmul - clmulh - clmulr Note that these instructions were already defined in the pre-0.93 and the 0.93 draft-B proposals, but had not been omitted in the earlier addition of draft-B to QEmu. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Hend

[PATCH v11 16/16] disas/riscv: Add Zb[abcs] instructions

With the addition of Zb[abcs], we also need to add disassembler support for these new instructions. Signed-off-by: Philipp Tomsich Acked-by: Alistair Francis --- (no changes since v2) Changes in v2: - Fix missing ';' from last-minute whitespace cleanups. disas/riscv.c | 157

[PATCH v11 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh

The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a zext.h instruction is provided (built on pack/packh from pre-0.93 draft-B) is available. This commit adds zext.h and removes the pack* instructions. Note that the encodings for zext.h are different between RV32 and RV64, which

[PATCH v11 12/16] target/riscv: Add a REQUIRE_32BIT macro

With the changes to Zb[abcs], there's some encodings that are different in RV64 and RV32 (e.g., for rev8 and zext.h). For these, we'll need a helper macro allowing us to select on RV32, as well. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed

[PATCH v11 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)

The Zb[abcs] ratification package does not include the proposed shift-one instructions. There currently is no clear plan to whether these (or variants of them) will be ratified as Zbo (or a different extension) or what the timeframe for such a decision could be. Signed-off-by: Philipp Tomsich Rev

[PATCH v11 08/16] target/riscv: Reassign instructions to the Zbs-extension

The following instructions are part of Zbs: - b{set,clr,ext,inv} - b{set,clr,ext,inv}i Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Acked-by: Bin Meng --- (no changes since v3) Changes in v3: - The changes to the Zbs instructions (i.e. the REQ

[PATCH v11 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0

The Zb[abcs] extensions have complete public review and are nearing ratifications. These individual extensions are one part of what was previously though of as the "BitManip" (B) extension, leaving the final details of future Zb* extensions open as they will undergo further public discourse. Thi

[PATCH v11 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci

The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a orc.b instruction (equivalent to the orc.b pseudo-instruction built on gorci from pre-0.93 draft-B) is available, mainly targeting string-processing workloads. This commit adds the new orc.b instruction and removed gorc/gorci. Sign

[PATCH v11 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties

The bitmanipulation ISA extensions will be ratified as individual small extension packages instead of a large B-extension. The first new instructions through the door (these have completed public review) are Zb[abcs]. This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for these in tar

[PATCH v11 15/16] target/riscv: Remove RVB (replaced by Zb[abcs])

With everything classified as Zb[abcs] and pre-0.93 draft-B instructions that are not part of Zb[abcs] removed, we can remove the remaining support code for RVB. Note that RVB has been retired for good and misa.B will neither mean 'some' or 'all of' Zb*: https://lists.riscv.org/g/tech-bitmanip/m

[PATCH v11 13/16] target/riscv: Add rev8 instruction, removing grev/grevi

The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a rev8 instruction (equivalent to the rev8 pseudo-instruction built on grevi from pre-0.93 draft-B) is available. This commit adds the new rev8 instruction and removes grev/grevi. Note that there is no W-form of this instruction (bot

[PATCH v11 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)

Assume clzw being executed on a register that is not sign-extended, such as for the following sequence that uses (1ULL << 63) | 392 as the operand to clzw: bseti a2, zero, 63 addia2, a2, 392 clzwa3, a2 The correct result of clzw would be 23, but the current impleme

[PATCH v11 06/16] target/riscv: Remove the W-form instructions from Zbs

Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form instructions for Zbs (single-bit instructions). Remove them. Note that these instructions had already been removed for the 0.93 version of the draft-B extention and have not been present in the binutils patches circulating in

[PATCH v11 01/16] target/riscv: Introduce temporary in gen_add_uw()

Following the recent changes in translate.c, gen_add_uw() causes failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these regressions by introducing a temporary. Signed-off-by: Philipp Tomsich Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*") Reviewed-by: Alistair Franc

[PATCH v11 05/16] target/riscv: Reassign instructions to the Zba-extension

The following instructions are part of Zba: - add.uw (RV64 only) - sh[123]add (RV32 and RV64) - sh[123]add.uw (RV64-only) - slli.uw (RV64-only) Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Acked-by: Bin Meng --- (no changes since v10) Change

[PATCH v11 02/16] target/riscv: fix clzw implementation to operate on arg1

The refactored gen_clzw() uses ret as its argument, instead of arg1. Fix it. Signed-off-by: Philipp Tomsich Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary") Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- (no changes since v10) Changes

Re: [Bug 1914117] Short files returned via FTP on Qemu with various architectures and OSes

I tested Qemu 6.1 (MacOS using brew to install) with guest OS NetBSD/i386. The bind distribution file downloaded fine by FTP. Libslurp has a workaround for MacOS and it looks like its gone in. I think this one can be closed. Sorry for the delay Kind regards Chris > On 25 Aug 2021, at 08:18, Thom

Re: [PATCH 1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set

On Sat, Sep 11, 2021 at 8:37 PM Bin Meng wrote: > > On Fri, Sep 10, 2021 at 1:56 PM wrote: > > > > From: Frank Chang > > > > Setting Control.claim clears all of the chanel's Next registers. > > This is effective only when Control.claim is set from 0 to 1. > > > > Signed-off-by: Frank Chang > >

Re: [PULL v4 00/43] (Mostly) x86 changes for 2021-09-06

Yes this is not anymore the tag I had posted... I was working on the review comments. Paolo Il sab 11 set 2021, 15:00 Peter Maydell ha scritto: > On Wed, 8 Sept 2021 at 11:07, Paolo Bonzini wrote: > > > > The following changes since commit > f9128631fbeb40a55f7bc145397981c963d40909: > > > >

Re: [PULL v4 00/43] (Mostly) x86 changes for 2021-09-06

On Wed, 8 Sept 2021 at 11:07, Paolo Bonzini wrote: > > The following changes since commit f9128631fbeb40a55f7bc145397981c963d40909: > > Merge remote-tracking branch > 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-09-07 > 13:24:43 +0100) > > are available in the Git repos

Re: [PATCH 1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set

On Fri, Sep 10, 2021 at 1:56 PM wrote: > > From: Frank Chang > > Setting Control.claim clears all of the chanel's Next registers. > This is effective only when Control.claim is set from 0 to 1. > > Signed-off-by: Frank Chang > Tested-by: Max Hsu > --- > hw/dma/sifive_pdma.c | 15 ++

[PATCH v2 1/2] tests: add migrate-during-backup

Add a simple test which tries to run migration during backup. bdrv_inactivate_all() should fail. But due to bug (see next commit with fix) it doesn't, nodes are inactivated and continued backup crashes on assertion "assert(!(bs->open_flags & BDRV_O_INACTIVE));" in bdrv_co_write_req_prepare(). Sign

[PATCH v2 2/2] block: bdrv_inactivate_recurse(): check for permissions and fix crash

We must not inactivate child when parent has write permissions on it. Calling .bdrv_inactivate() doesn't help: actually only qcow2 has this handler and it is used to flush caches, not for permission manipulations. So, let's simply check cumulative parent permissions before inactivating the node.

[PATCH v2 0/2] fix crash if try to migrate during backup

v2: 01: check that migration fails 02: Add Hanna's r-b Vladimir Sementsov-Ogievskiy (2): tests: add migrate-during-backup block: bdrv_inactivate_recurse(): check for permissions and fix crash block.c | 8 ++ .../qemu-iotests/tests/migrate-during-backup

Re: [PATCH] hw/i386/acpi-build: Fix a typo

On Sat, Sep 11, 2021 at 15:24 Ani Sinha wrote: > > > On Sat, Sep 11, 2021 at 13:56 Philippe Mathieu-Daudé > wrote: > >> On 9/11/21 3:33 AM, Ani Sinha wrote: >> > On Sat, Sep 11, 2021 at 1:03 AM Philippe Mathieu-Daudé >> > mailto:phi...@redhat.com>> wrote: >> > >> > On 9/10/21 8:54 PM, Volker

Re: [PATCH] hw/i386/acpi-build: Fix a typo

On Sat, Sep 11, 2021 at 13:56 Philippe Mathieu-Daudé wrote: > On 9/11/21 3:33 AM, Ani Sinha wrote: > > On Sat, Sep 11, 2021 at 1:03 AM Philippe Mathieu-Daudé > > mailto:phi...@redhat.com>> wrote: > > > > On 9/10/21 8:54 PM, Volker Rümelin wrote: > > >> Fix 'hotplugabble' -> 'hotpluggabble

Re: Implementing isochronous transfers in hw/hcd-ohci.c

On Fri, Sep 10, 2021 at 9:23 PM Programmingkid wrote: > > > > On Sep 10, 2021, at 7:51 AM, BALATON Zoltan wrote: > > > > On Fri, 10 Sep 2021, Howard Spoelstra wrote: > >> On Fri, Sep 10, 2021 at 7:07 AM Gerd Hoffmann > wrote: > >> > >>> On Thu, Sep 09, 2021 at 05:06:17PM -0400, Programmingkid w

Re: [qemu-web PATCH] Fix link to Windows page in Wiki

Am 11.09.21 um 10:43 schrieb Howard Spoelstra: Perhaps it would be better to fix configure for the MSYS2 case so the flags or the renaming are not required? Currently MSys2 packages qemu successfully for 3 different toolchains: MINGW64: msvcrt / libstdc++ UCRT64: ucrt / libstdc++ CLANG64: u

Re: [qemu-web PATCH] Fix link to Windows page in Wiki

On 11/09/2021 10:17, Helge Konetzka wrote: Am 11.09.21 um 11:03 schrieb Mark Cave-Ayland: So the question is: what has changed? I find it hard to believe that MSYS2/MingW64 is configured out-of-the-box to break a standard "./configure && make" build incantation. On my last attempt to buil

Re: [qemu-web PATCH] Fix link to Windows page in Wiki

Am 11.09.21 um 11:03 schrieb Mark Cave-Ayland: So the question is: what has changed? I find it hard to believe that MSYS2/MingW64 is configured out-of-the-box to break a standard "./configure && make" build incantation. On my last attempt to build qemu without --cross-prefix=x86_64-w64-min

Re: [qemu-web PATCH] Fix link to Windows page in Wiki

On 11/09/2021 10:03, Mark Cave-Ayland wrote: So the question is: what has changed? I find it hard to believe that MSYS2/MingW64 is configured out-of-the-box to break a standard "./configure && make" build incantation. Also it is worth pointing out that neither the copying/renaming of binaries

Re: [qemu-web PATCH] Fix link to Windows page in Wiki

Il sab 11 set 2021, 10:43 Howard Spoelstra ha scritto: > I wrote those instructions as I obviously could not find a better way to > get Qemu to cross-compile using MSYS2 in Windows. > But if you are using MSYS2, why do you need cross compilation and --cross-prefix at all? When you look at confi

Re: [qemu-web PATCH] Fix link to Windows page in Wiki

On 11/09/2021 09:43, Howard Spoelstra wrote: On Sat, Sep 11, 2021 at 8:29 AM Helge Konetzka > wrote: Am 10.09.21 um 17:44 schrieb Paolo Bonzini: > On 25/08/21 18:43, Helge Konetzka wrote: >> Furthermore I would like to propose to change the instructions f

Re: [qemu-web PATCH] Fix link to Windows page in Wiki

On Sat, Sep 11, 2021 at 8:29 AM Helge Konetzka wrote: > Am 10.09.21 um 17:44 schrieb Paolo Bonzini: > > On 25/08/21 18:43, Helge Konetzka wrote: > >> Furthermore I would like to propose to change the instructions for > >> Native builds with MSYS2 on Wiki Windows page. > >> > >> Please remove the

Re: [PATCH] hw/i386/acpi-build: Fix a typo

On 9/11/21 3:33 AM, Ani Sinha wrote: > On Sat, Sep 11, 2021 at 1:03 AM Philippe Mathieu-Daudé > mailto:phi...@redhat.com>> wrote: > > On 9/10/21 8:54 PM, Volker Rümelin wrote: > >> Fix 'hotplugabble' -> 'hotpluggabble' typo. > > > > I'm convinced that the correct spelling is hotplu

[PATCH v2] hw/i386/acpi-build: Fix a typo

Fix 'hotplugabble' -> 'hotpluggable' typo. Reviewed-by: Ani Sinha Signed-off-by: Philippe Mathieu-Daudé --- v1 still had a typo =) (Volker Rümelin) --- hw/i386/acpi-build.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c inde