Re: [PATCH 09/12] mac_via: remove mac_via device

Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit : > Remove the mac_via device and wire up both q800 VIA1 and VIA2 directly for the > m68k q800 machine. > > Signed-off-by: Mark Cave-Ayland > --- > hw/m68k/q800.c| 34 + > hw/misc/mac_via.c | 78 +++--

Re: [PATCH 11/12] mac_via: rename VIA2_IRQ_SLOT_BIT to VIA2_IRQ_NUBUS_BIT

Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit : > Also improve the alignment of the shifted constants. > > Signed-off-by: Mark Cave-Ayland > --- > include/hw/misc/mac_via.h | 22 +++--- > 1 file changed, 11 insertions(+), 11 deletions(-) > Reviewed-by: Laurent Vivier

Re: [PATCH 07/12] mac_via: move VIA1 reset logic from mac_via_reset() to mos6522_q800_via1_reset()

Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit : > After this change mac_via_reset() is now empty and can be removed. > > Signed-off-by: Mark Cave-Ayland > --- > hw/misc/mac_via.c | 22 -- > 1 file changed, 8 insertions(+), 14 deletions(-) Reviewed-by: Laurent Vivier

Re: [PATCH 08/12] mac_via: move VIA1 realize logic from mac_via_realize() to mos6522_q800_via1_realize()

Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit : > Signed-off-by: Mark Cave-Ayland > --- > hw/misc/mac_via.c | 86 --- > 1 file changed, 44 insertions(+), 42 deletions(-) > Reviewed-by: Laurent Vivier

Re: [PATCH 10/12] mac_via: remove explicit viaN prefix from VIA IRQ gpios

Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit : > Now that q800 VIA1 and VIA2 are completely separate devices there is no need > to > add a specific device prefix to ensure that the IRQ lines remain separate. > > Signed-off-by: Mark Cave-Ayland > --- > hw/m68k/q800.c| 10 -- > hw/

Re: [PATCH 0/5] qapi: Another round of minor fixes and cleanups

Hi On Wed, Sep 8, 2021 at 8:54 AM Markus Armbruster wrote: > Markus Armbruster (5): > qapi: Fix a botched type annotation > qapi: Drop Indentation.__bool__() > qapi: Bury some unused code in class Indentation > tests/qapi-schema: Cover 'not' condition with empty argument > qapi: Fix bo

Re: [PATCH 06/12] mac_via: move q800 VIA1 timer variables to q800 VIA1 VMStateDescription

Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit : > These variables are already present in MOS6522Q800VIA1State and so it is just > the VMStateDescription move that is needed. > > With this change the mac_via VMStateDescription is now empty and can be > removed > completely. > > Signed-off-by: M

Re: [PATCH 05/12] mac_via: move ADB variables to MOS6522Q800VIA1State

Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit : > The ADB is accessed using clock and data pins on q800 VIA1 port B and so can > be > moved to MOS6522Q800VIA1State. > > Signed-off-by: Mark Cave-Ayland > --- > hw/m68k/q800.c| 6 +- > hw/misc/mac_via.c | 169 ++

Re: [PATCH v2 2/3] target/riscv: Implement the stval/mtval illegal instruction

On 9/8/21 6:54 AM, Alistair Francis wrote: @@ -967,6 +967,16 @@ void riscv_cpu_do_interrupt(CPUState *cs) write_tval = true; tval = env->badaddr; break; +case RISCV_EXCP_ILLEGAL_INST: +if (riscv_feature(env, RISCV_FEATURE_MTVAL_INST))

Re: [PATCH 04/12] mac_via: move PRAM/RTC variables to MOS6522Q800VIA1State

Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit : > The PRAM/RTC is accessed using clock and data pins on q800 VIA1 port B and so > can be moved to MOS6522Q800VIA1State. > > Signed-off-by: Mark Cave-Ayland > --- > hw/misc/mac_via.c | 135 +++--- > include/

Re: [PATCH 03/12] mac_via: move PRAM contents and block backend to MOS6522Q800VIA1State

Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit : > The PRAM contents are accessed using clock and data pins on q800 VIA1 port B > and so can be moved to MOS6522Q800VIA1State. > > Signed-off-by: Mark Cave-Ayland > --- > hw/misc/mac_via.c | 59 --- > in

Re: [PATCH 02/12] mac_via: move last_b variable into q800 VIA1 VMStateDescription

Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit : > This variable is already present in MOS6522Q800VIA1State and can be moved > immediately into the q800 VIA1 VMStateDescription. > > Signed-off-by: Mark Cave-Ayland > --- > hw/misc/mac_via.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)

Re: [PATCH 01/12] mac_via: introduce new VMStateDescription for q800 VIA1 and VIA2

Le 30/08/2021 à 12:24, Mark Cave-Ayland a écrit : > Move the parent mos6522 objects from vmstate_mac_via into the new > VMStateDescription > structures to begin the process of splitting MacVIAState into separate VIA1 > and > VIA2 devices. > > Signed-off-by: Mark Cave-Ayland > --- > hw/misc/mac

Re: [PATCH] hw/i386/acpi-build: adjust q35 IO addr range for acpi pci hotplug

On Wed, 8 Sep 2021 09:41:39 +0530 Ani Sinha wrote: > Change caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods to > Q35") > selects an IO address range for acpi based PCI hotplug for q35 arbitrarily. It > starts at address 0x0cc4 and ends at 0x0cdb. It was assumed that this addre

Re: [PATCH v6 09/12] target/hexagon: import parser for idef-parser

On 9/7/21 8:08 PM, Taylor Simpson wrote: diff --git a/target/hexagon/idef-parser/parser-helpers.h b/target/hexagon/idef-parser/parser-helpers.h +#define OUT_IMPL(c, locp, x)\ +_Generic(*x,\ +char: str_print, \

Re: [PATCH] hw/ssi: imx_spi: Improve chip select handling

On Wed, Sep 8, 2021 at 2:29 PM Bin Meng wrote: > > On Sun, Sep 5, 2021 at 10:08 AM Guenter Roeck wrote: > > > > On 9/4/21 4:19 PM, Philippe Mathieu-Daudé wrote: > > > On 9/5/21 1:06 AM, Bin Meng wrote: > > >> On Sun, Sep 5, 2021 at 1:13 AM Guenter Roeck wrote: > > >>> > > >>> On 9/2/21 12:29 PM,

Re: [PATCH] hw/ssi: imx_spi: Improve chip select handling

On Sun, Sep 5, 2021 at 10:08 AM Guenter Roeck wrote: > > On 9/4/21 4:19 PM, Philippe Mathieu-Daudé wrote: > > On 9/5/21 1:06 AM, Bin Meng wrote: > >> On Sun, Sep 5, 2021 at 1:13 AM Guenter Roeck wrote: > >>> > >>> On 9/2/21 12:29 PM, Peter Maydell wrote: > On Thu, 2 Sept 2021 at 17:09, Guent

Re: [PATCH v2 1/3] target/riscv: Set the opcode in DisasContext

On 9/8/21 6:54 AM, Alistair Francis wrote: From: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/translate.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e356fc6c46..25670be435 10

Re: [PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

On Tue, Aug 31, 2021 at 7:07 PM Anup Patel wrote: > > The RISC-V ACLINT is more modular and backward compatible with > original SiFive CLINT so instead of duplicating the original > SiFive CLINT implementation we upgrade the current SiFive CLINT > implementation to RISC-V ACLINT implementation. >

Re: [PATCH] fuzz: fix unbound variable in build.sh

On 07/09/21 13:08, Alexander Bulekov wrote: -if [ "$GITLAB_CI" != "true" ]; then +if [ -z ${GITLAB_CI+x} ]; then I would slightly prefer to have "${GITLAB_CI+x}", since "test" in general doesn't like parameters that go away: $ [ = abc ] bash: [: =: unary operator expected What you wrote

Re: [qemu-web RFC] CONTRIBUTING.md: Mention maintainers

On 07/09/21 15:40, Thomas Huth wrote: we should maybe have a pointer to the information on https://www.qemu.org/contribute/ instead? Yes - right now contribute/ links to the old blog post for "Improve the web site", but I guess it couuld just go to https://gitlab.com/qemu-project/qemu-web/-/m

Re: [PATCH v4 00/33] Qemu SGX virtualization

On 07/09/21 11:51, Yang Zhong wrote: Paolo, I have moved hmp and qmp codes to target/i386/monitor.c and also fixed the issue with test tool(tests/qtest/test-hmp). This issue is caused by 'machine none' test in the hmp, the previous patches only covered qmp test in 'machine none' w

Re: [PATCH] qemu-thread: avoid false positive in pthread_cleanup_push

On 07/09/21 16:20, Richard Henderson wrote: On 9/7/21 2:51 PM, Paolo Bonzini wrote: +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstringop-overflow"   pthread_cleanup_push(qemu_thread_atexit_notify, NULL); +#pragma GCC diagnostic pop I had a patch for this that didn't qui

Re: [PATCH v2 3/3] target/riscv: Set mtval and stval support

On Wed, Sep 8, 2021 at 12:55 PM Alistair Francis wrote: > > From: Alistair Francis > > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.h | 1 + > target/riscv/cpu.c | 6 +- > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >

Re: [PATCH v2 2/3] target/riscv: Implement the stval/mtval illegal instruction

On Wed, Sep 8, 2021 at 12:54 PM Alistair Francis wrote: > > From: Alistair Francis > > The stval and mtval registers can optionally contain the faulting > instruction on an illegal instruction exception. This patch adds support > for setting the stval and mtval registers based on the CPU feature.

Re: [PATCH] fuzz: fix unbound variable in build.sh

On 07/09/2021 14.51, Alexander Bulekov wrote: On 210907 1432, Thomas Huth wrote: On 07/09/2021 13.08, Alexander Bulekov wrote: /src/build.sh: line 76: GITLAB_CI: unbound variable Fix that. Signed-off-by: Alexander Bulekov --- This change is in preparation to revert: 7602748c ("qemu: manually

Re: [PATCH] meson: look up cp and dtrace with find_program()

On 07/09/21 21:06, Marc-André Lureau wrote: Hi On Tue, Sep 7, 2021 at 9:27 PM Paolo Bonzini > wrote: Avoid that meson prints a "Program xyz found" test once per custom_target. Signed-off-by: Paolo Bonzini mailto:pbonz...@redhat.com>> Reviewed-by: Marc

Re: [PATCH] fw_cfg: add etc/msr_feature_control

On 07/09/21 20:19, Philippe Mathieu-Daudé wrote: Fixes: 217f1b4a721 ("target-i386: Publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg") Yes, thanks. Paolo

Re: [PATCH] ebpf: only include in system emulators

On 08/09/21 05:08, Jason Wang wrote: 在 2021/9/7 下午6:45, Paolo Bonzini 写道: eBPF files are being included in system emulators, which is useless I think it should work since it's an independent feature. The current use case is to offload the RSS from Qemu to kernel TAP. Sorry, I meant "user

Re: [PATCH v2 1/3] target/riscv: Set the opcode in DisasContext

On Wed, Sep 8, 2021 at 12:54 PM Alistair Francis wrote: > > From: Alistair Francis > > Signed-off-by: Alistair Francis > --- > target/riscv/translate.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > Reviewed-by: Bin Meng

Re: [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs])

On Sun, Sep 5, 2021 at 4:53 AM Philipp Tomsich wrote: > > With everything classified as Zb[abcs] and pre-0.93 draft-B > instructions that are not part of Zb[abcs] removed, we can remove the > remaining support code for RVB. > > Note that RVB has been retired for good and misa.B will neither mean >

Re: [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro

On Sun, Sep 5, 2021 at 4:47 AM Philipp Tomsich wrote: > > With the changes to Zb[abcs], there's some encodings that are > different in RV64 and RV32 (e.g., for rev8 and zext.h). For these, > we'll need a helper macro allowing us to select on RV32, as well. > > Signed-off-by: Philipp Tomsich > Rev

Re: [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension

On Sun, Sep 5, 2021 at 4:38 AM Philipp Tomsich wrote: > > This reassigns the instructions that are part of Zbb into it, with the > notable exceptions of the instructions (rev8, zext.w and orc.b) that > changed due to gorci, grevi and pack not being part of Zb[abcs]. > > Signed-off-by: Philipp Toms

Re: [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension

On Sun, Sep 5, 2021 at 4:38 AM Philipp Tomsich wrote: > > The following instructions are part of Zba: > - add.uw (RV64 only) > - sh[123]add (RV32 and RV64) > - sh[123]add.uw (RV64-only) > - slli.uw (RV64-only) > > Signed-off-by: Philipp Tomsich > Reviewed-by: Richard Henderson > Reviewed-by:

Re: [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension

On Sun, Sep 5, 2021 at 4:43 AM Philipp Tomsich wrote: > > The following instructions are part of Zbs: > - b{set,clr,ext,inv} > - b{set,clr,ext,inv}i > > Signed-off-by: Philipp Tomsich > Reviewed-by: Richard Henderson > Reviewed-by: Alistair Francis > --- > > (no changes since v3) > > Changes

Re: [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)

On Sun, Sep 5, 2021 at 4:40 AM Philipp Tomsich wrote: > > The Zb[abcs] ratification package does not include the proposed > shift-one instructions. There currently is no clear plan to whether > these (or variants of them) will be ratified as Zbo (or a different > extension) or what the timeframe f

Re: [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs

On Sun, Sep 5, 2021 at 4:49 AM Philipp Tomsich wrote: > > Zbs 1.0.0 (just as the 0.93 draft-B before) does no provide for W-form does not > instructions for Zbs (single-bit instructions). Remove them. > > Note that these instructions had already been removed for the 0.93 > version of the draft-

Re: [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties

On Sun, Sep 5, 2021 at 4:35 AM Philipp Tomsich wrote: > > The bitmanipulation ISA extensions will be ratified as individual > small extension packages instead of a large B-extension. The first > new instructions through the door (these have completed public review) > are Zb[abcs]. > > This adds n

Re: [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1

On Sun, Sep 5, 2021 at 4:35 AM Philipp Tomsich wrote: > > The refactored gen_clzw() uses ret as its argument, instead of arg1. > Fix it. > > Signed-off-by: Philipp Tomsich > --- > > Changes in v10: > - New patch, fixing regressions discovered with x264_r. > > target/riscv/insn_trans/trans_rvb.c.

Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw()

On Sun, Sep 5, 2021 at 4:40 AM Philipp Tomsich wrote: > > Following the recent changes in translate.c, gen_add_uw() causes > failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these > regressions by introducing a temporary. > > Signed-off-by: Philipp Tomsich > --- > > Changes in v10: > -

[PATCH v2 2/3] target/riscv: Implement the stval/mtval illegal instruction

From: Alistair Francis The stval and mtval registers can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval and mtval registers based on the CPU feature. Signed-off-by: Alistair Francis --- target/riscv/cpu.h|

[PATCH v2 3/3] target/riscv: Set mtval and stval support

From: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 6 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d11db1f031..5b0bbf2fca 100644 --- a/target/riscv/cpu.h +++ b/target/ris

[PATCH 0/5] qapi: Another round of minor fixes and cleanups

Markus Armbruster (5): qapi: Fix a botched type annotation qapi: Drop Indentation.__bool__() qapi: Bury some unused code in class Indentation tests/qapi-schema: Cover 'not' condition with empty argument qapi: Fix bogus error for 'if': { 'not': '' } scripts/qapi/common.py| 19

[PATCH v2 1/3] target/riscv: Set the opcode in DisasContext

From: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/translate.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e356fc6c46..25670be435 100644 --- a/target/riscv/translate.c +++ b/targe

[PATCH 1/5] qapi: Fix a botched type annotation

Mypy is unhappy: $ mypy --config-file=scripts/qapi/mypy.ini `git-ls-files scripts/qapi/\*py` scripts/qapi/common.py:208: error: Function is missing a return type annotation scripts/qapi/common.py:227: error: Returning Any from function declared to return "str" Messed up in commit cc

[PATCH 2/5] qapi: Drop Indentation.__bool__()

Intentation.__bool__() is not worth its keep: it has just one user, which can just as well check .__str__() instead. Signed-off-by: Markus Armbruster --- scripts/qapi/common.py | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/scripts/qapi/common.py b/scripts/qapi/comm

[PATCH 5/5] qapi: Fix bogus error for 'if': { 'not': '' }

Signed-off-by: Markus Armbruster --- scripts/qapi/expr.py | 21 + tests/qapi-schema/bad-if-not.err | 2 +- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/scripts/qapi/expr.py b/scripts/qapi/expr.py index b62f0a3640..ad3732c7f0 100644 --- a/scripts

[PATCH v2 0/3] RISC-V: Populate mtval and stval

From: Alistair Francis Populate mtval and stval when taking an illegal instruction exception if the features are set for the CPU. Alistair Francis (3): target/riscv: Set the opcode in DisasContext target/riscv: Implement the stval/mtval illegal instruction target/riscv: Set mtval and st

[PATCH 4/5] tests/qapi-schema: Cover 'not' condition with empty argument

We flag this, but the error message is bogus: bad-if-not.json:2: 'if' condition [] of struct is useless The next commit will fix it. Signed-off-by: Markus Armbruster --- tests/qapi-schema/bad-if-not.err | 2 ++ tests/qapi-schema/bad-if-not.json | 3 +++ tests/qapi-schema/bad-if-not.out |

[PATCH 3/5] qapi: Bury some unused code in class Indentation

.__int__() has never been used. Drop it. .decrease() raises ArithmeticError when asked to decrease indentation level below zero. Nothing catches it. It's a programming error. Dumb down to assert. Signed-off-by: Markus Armbruster --- scripts/qapi/common.py | 7 +-- 1 file changed, 1 inser

Re: [PATCH] hw/i386/acpi-build: adjust q35 IO addr range for acpi pci hotplug

On Wed, 8 Sep 2021, Ani Sinha wrote: > Change caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods to > Q35") > selects an IO address range for acpi based PCI hotplug for q35 arbitrarily. It > starts at address 0x0cc4 and ends at 0x0cdb. It was assumed that this address > range wa

[PATCH] hw/i386/acpi-build: adjust q35 IO addr range for acpi pci hotplug

Change caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35") selects an IO address range for acpi based PCI hotplug for q35 arbitrarily. It starts at address 0x0cc4 and ends at 0x0cdb. It was assumed that this address range was free and available. However, upon more testing, i

Re: [PATCH 4/5] ebpf_rss_helper: Added helper for eBPF RSS.

On Tue, Sep 7, 2021 at 6:40 PM Yuri Benditovich wrote: > > On Wed, Sep 1, 2021 at 9:42 AM Jason Wang wrote: > > > > > > 在 2021/8/31 上午1:07, Yuri Benditovich 写道: > > > On Fri, Aug 20, 2021 at 6:41 AM Jason Wang wrote: > > >> > > >> 在 2021/7/13 下午11:37, Andrew Melnychenko 写道: > > >>> Helper progra

Re: [PATCH v2 1/2] hw/timer: Add SiFive PWM support

On Fri, Sep 3, 2021 at 7:25 AM Alistair Francis wrote: > > From: Alistair Francis > > This is the initial commit of the SiFive PWM timer. This is used by > guest software are a timer and is included in the SiFive FU540 SoC. "guest software are a time .. This does not read right. > > Signed-off

Re: [PATCH v2 2/2] sifive_u: Connect the SiFive PWM device

On Fri, Sep 3, 2021 at 7:25 AM Alistair Francis wrote: > > From: Alistair Francis > > Connect the SiFive PWM device and expose it via the device tree. > > Signed-off-by: Alistair Francis > --- > include/hw/riscv/sifive_u.h | 14 +- > hw/riscv/sifive_u.c | 55

Re: [PATCH v1 3/3] migration: multifd: Enable zerocopy

On Wed, Sep 8, 2021 at 11:24 AM Peter Xu wrote: > > On Wed, Sep 08, 2021 at 10:59:57AM +0800, Jason Wang wrote: > > On Wed, Sep 8, 2021 at 2:32 AM Peter Xu wrote: > > > > > > On Thu, Sep 02, 2021 at 04:22:55AM -0300, Leonardo Bras Soares Passos > > > wrote: > > > > > I don't think it is valid to

Re: [PATCH v1 3/3] migration: multifd: Enable zerocopy

On Wed, Sep 08, 2021 at 10:59:57AM +0800, Jason Wang wrote: > On Wed, Sep 8, 2021 at 2:32 AM Peter Xu wrote: > > > > On Thu, Sep 02, 2021 at 04:22:55AM -0300, Leonardo Bras Soares Passos wrote: > > > > I don't think it is valid to unconditionally enable this feature due to > > > > the > > > > res

Re: [PATCH v5 3/4] spapr_numa.c: base FORM2 NUMA affinity support

On Tue, Sep 07, 2021 at 07:07:41AM -0300, Daniel Henrique Barboza wrote: 65;6402;1c> > > On 9/6/21 10:02 PM, David Gibson wrote: > > On Mon, Sep 06, 2021 at 09:25:26PM -0300, Daniel Henrique Barboza wrote: > > > The main feature of FORM2 affinity support is the separation of NUMA > > > distances

Re: [PATCH] ebpf: only include in system emulators

在 2021/9/7 下午6:45, Paolo Bonzini 写道: eBPF files are being included in system emulators, which is useless I think it should work since it's an independent feature. The current use case is to offload the RSS from Qemu to kernel TAP. and also breaks compilation because ebpf/trace-events

Re: [PATCH v1 3/3] migration: multifd: Enable zerocopy

On Wed, Sep 8, 2021 at 2:32 AM Peter Xu wrote: > > On Thu, Sep 02, 2021 at 04:22:55AM -0300, Leonardo Bras Soares Passos wrote: > > > I don't think it is valid to unconditionally enable this feature due to > > > the > > > resource usage implications > > > > > > https://www.kernel.org/doc/html/v5.

Re: Application of QEMUTimer in short timing.

thank you for your reply.I understand. Also I want to know how to make a delay in qemu. For example, when I send a UART data, there is a certain time interval from setting the register to when the data is sent. Most of this time does not affect the simulation effect, but some guest firmware will e

Re: [PATCH v5 1/4] spapr: move NUMA associativity init to machine reset

On Tue, Sep 07, 2021 at 09:10:13AM +0200, Greg Kurz wrote: > On Tue, 7 Sep 2021 10:37:27 +1000 > David Gibson wrote: > > > On Mon, Sep 06, 2021 at 09:25:24PM -0300, Daniel Henrique Barboza wrote: > > > At this moment we only support one form of NUMA affinity, FORM1. This > > > allows us to init t

Re: arm: Launching EFI-enabled arm32 Linux

On Wed, 8 Sep 2021 01:25:04 +0200 Adam Lackorzynski wrote: Hi Adam, > On Mon Sep 06, 2021 at 16:34:03 +0100, Andre Przywara wrote: > > On Sat, 4 Sep 2021 21:26:45 +0200 > > Adam Lackorzynski wrote: > > > > Hi Adam, > > > > > while trying to launch an EFI-enabled arm32 Linux binary (zImage)

[PATCH 2/4] hw/sd: add nuvoton MMC

From: Shengtan Mao Signed-off-by: Shengtan Mao Reviewed-by: Hao Wu Reviewed-by: Chris Rauer Reviewed-by: Tyrone Ting --- hw/arm/npcm7xx.c | 12 +++- hw/sd/meson.build | 1 + hw/sd/npcm7xx_sdhci.c | 131 ++ include/hw/arm/npc

[PATCH 4/4] tests/qtest: add qtests for npcm7xx sdhci

From: Shengtan Mao Signed-off-by: Shengtan Mao Reviewed-by: Hao Wu Reviewed-by: Chris Rauer Reviewed-by: Tyrone Ting --- tests/qtest/meson.build | 1 + tests/qtest/npcm7xx_sdhci-test.c | 201 +++ 2 files changed, 202 insertions(+) create mode 100644 te

[PATCH 0/4] hw/arm: Add MMC device for NPCM7XX boards

This patch set implements the Nuvoton MMC device for NPCM7XX boards. The MMC device is compatible with the SDHCI interface in QEMU. It allows the user to attach an SD card image to it. Shengtan Mao (4): tests/qtest/libqos: add SDHCI commands hw/sd: add nuvoton MMC hw/arm: Attach MMC to quan

[PATCH 1/4] tests/qtest/libqos: add SDHCI commands

From: Shengtan Mao Signed-off-by: Shengtan Mao Reviewed-by: Hao Wu Reviewed-by: Chris Rauer Reviewed-by: Tyrone Ting --- tests/qtest/libqos/meson.build | 1 + tests/qtest/libqos/sdhci-cmd.c | 116 + tests/qtest/libqos/sdhci-cmd.h | 70

[PATCH 3/4] hw/arm: Attach MMC to quanta-gbs-bmc

From: Shengtan Mao Signed-off-by: Shengtan Mao Reviewed-by: Hao Wu Reviewed-by: Tyrone Ting --- hw/arm/npcm7xx_boards.c | 21 + 1 file changed, 21 insertions(+) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index e5a3243995..7205483280 100644 --- a/hw/arm

Re: arm: Launching EFI-enabled arm32 Linux

Hi Andre, On Mon Sep 06, 2021 at 16:34:03 +0100, Andre Przywara wrote: > On Sat, 4 Sep 2021 21:26:45 +0200 > Adam Lackorzynski wrote: > > Hi Adam, > > > while trying to launch an EFI-enabled arm32 Linux binary (zImage) I > > noticed I get an undefined instruction exception on the first > > inst

Re: [PATCH v3 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines

On Mon, Aug 30, 2021 at 3:36 PM Alistair Francis wrote: > > From: Alistair Francis > > Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V > CPU GPIO lines to set the timer MIP bits. > > Signed-off-by: Alistair Francis > Reviewed-by: Philippe Mathieu-Daudé > Reviewed-by: Ri

[PATCH v2] hw/arm: Add support for kudo-bmc board.

kudo-bmc is a board supported by OpenBMC. https://github.com/openbmc/openbmc/tree/master/meta-fii/meta-kudo Since v1: - hyphenated Cortex-A9 Tested: Booted kudo firmware. Signed-off-by: Chris Rauer --- docs/system/arm/nuvoton.rst | 1 + hw/arm/npcm7xx_boards.c | 34

[PULL 42/42] bsd-user: Update mapping to handle reserved and starting conditions

From: Warner Losh Update the reserved base based on what platform we're on, as well as the start of the mmap range. Update routines that find va ranges to interact with the reserved ranges as well as properly align the mapping (this is especially important for targets whose page size does not mat

[PULL 38/42] bsd-user: Refactor load_elf_sections and is_target_elf_binary

From: Warner Losh Factor out load_elf_sections and is_target_elf_binary out of load_elf_interp. Signed-off-by: Mikaël Urankar Signed-off-by: Stacey Son Signed-off-by: Warner Losh Reviewed-by: Kyle Evans --- bsd-user/elfload.c | 344 + 1 file chang

[PULL 36/42] bsd-user: add stubbed out core dump support

From: Warner Losh Add a stubbed-out version of the bsd-user fork's core dump support. This allows elfload.c to be almost the same between what's upstream and what's in qemu-project upstream w/o the burden of reviewing the core dump support. Signed-off-by: Stacey Son Signed-off-by: Warner Losh

[PULL 34/42] bsd-user: Add target_arch_reg to describe a target's register set

From: Warner Losh target_reg_t is the normal register. target_fpreg_t is the floating point registers. target_copy_regs copies the registers out of CPU context for things like core dumps. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/i386/ta

[PULL 40/42] bsd-user: Implement interlock for atomic operations

From: Warner Losh Implement the internlock in fork_start() and fork_end() to properly cope with atomic operations and to safely keep state for parent and child processes. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/main.c | 24

[PULL 39/42] bsd-user: move gemu_log to later in the file

From: Warner Losh Signed-off-by: Warner Losh Acked-by: Richard Henderson Reviewed-by: Kyle Evans --- bsd-user/main.c | 17 + 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/bsd-user/main.c b/bsd-user/main.c index 71fd9d5aba..768f4ee41e 100644 --- a/bsd-user/main.

[PULL 33/42] bsd-user: update debugging in mmap.c

From: Warner Losh Update the debugging code for new features and different targets. Signed-off-by: Mikaël Urankar Signed-off-by: Sean Bruno Signed-off-by: Kyle Evans Signed-off-by: Warner Losh Acked-by: Richard Henderson Reviewed-by: Kyle Evans --- bsd-user/mmap.c | 55 +++

Re: [PATCH v2] Prevent vhost-user-blk-test hang

On Mon, Sep 06, 2021 at 01:25:20PM +, Raphael Norwitz wrote: > In the vhost-user-blk-test, as of now there is nothing stoping > vhost-user-blk in QEMU writing to the socket right after forking off the > storage daemon before it has a chance to come up properly, leaving the > test hanging foreve

[PULL 26/42] bsd-user: *BSD specific siginfo defintions

From: Warner Losh Add FreeBSD, NetBSD and OpenBSD values for the various signal info types and defines to decode different signals to discover more information about the specific signal types. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Acked-by: Richard Henderson Reviewed-by: Kyle E

[PULL 35/42] bsd-user: Add target_os_user.h to capture the user/kernel structures

From: Warner Losh This file evolved over the years to capture the user/kernel interfaces, including those that changed over time. Signed-off-by: Stacey Son Signed-off-by: Michal Meloun Signed-off-by: Warner Losh Acked-by: Richard Henderson Reviewed-by: Kyle Evans --- bsd-user/freebsd/targe

[PULL 41/42] bsd-user: Add '-0 argv0' option to bsd-user/main.c

From: Colin Percival Previously it was impossible to emulate a program with a file name different from its argv[0]. With this change, you can run qemu -0 fakename realname args which runs the program "realname" with an argv of "fakename args". Signed-off-by: Colin Percival Signed-off-by: W

[PULL 27/42] bsd-user: Implement --seed and initialize random state

From: Warner Losh Copy --seed implementation (translated from linux-user's newer command line scheme to the older one bsd-user still uses). Initialize the randomness with the glib if a specific seed is specified or use the qcrypto library if not. Signed-off-by: Warner Losh Reviewed-by: Richard

[PULL 37/42] bsd-user: elfload.c style catch up patch

From: Warner Losh Various style fixes to elfload.c that were too painful to make earlier in this series. Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/elfload.c | 208 ++--- 1 file changed, 104 insertions(+), 104 deletions(-) d

[PULL 32/42] bsd-user: Rewrite target system call definintion glue

From: Warner Losh Rewrite target definnitions to interface with the FreeBSD system calls. This covers basic types (time_t, iovec, umtx_time, timespec, timeval, rusage, rwusage) and basic defines (mmap, rusage). Also included are FreeBSD version-specific variations. Signed-off-by: Stacey Son Sig

[PULL 24/42] bsd-user: Create target specific vmparam.h

From: Warner Losh Target specific values for vm parameters and details. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/freebsd/target_os_vmparam.h | 38 ++ bsd-user/i386/target_arch_vmparam.h | 46 ++

[PULL 31/42] bsd-user: Remove dead #ifdefs from elfload.c

From: Warner Losh LOW_ELF_STACK doesn't exist on FreeBSD and likely never will. Remove it. Likewise, remove an #if 0 block that's not useful Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/elfload.c | 20 1 file changed, 20 deletions(-) diff --git

[PULL 22/42] bsd-user: Include more things in qemu.h

From: Warner Losh Include more header files to match bsd-user fork. Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/qemu.h | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 5e4cbb40d4..55d71130bb 100644 ---

[PULL 30/42] bsd-user: elf cleanup

From: Warner Losh Move OS-dependent defines into target_os_elf.h. Move the architectural dependent stuff into target_arch_elf.h. Adjust elfload.c to use target_create_elf_tables instead of create_elf_tables. Signed-off-by: Warner Losh Signed-off-by: Stacey Son Signed-off-by: Kyle Evans Signed

[PULL 28/42] bsd-user: Move stack initializtion into a per-os file.

From: Warner Losh Move all of the stack initialization into target_os_stack.h. Each BSD sets up processes a little differently. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/freebsd/target_os_stack.h | 181 + bsd-

[PULL 29/42] bsd-user: Add architecture specific signal tramp code

From: Warner Losh Add a stubbed out version of setup_sigtramp. This is not yet used for x86, but is used for other architectures. This will be connected in future commits. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/i386/target_arch_sigtra

[PULL 16/42] bsd-user: add host-os.h

From: Warner Losh Host OS specific bits for this implementation go in this file. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/freebsd/host-os.h | 23 +++ bsd-user/netbsd/host-os.h | 23 +++ bsd-user/

[PULL 20/42] bsd-user: Move per-cpu code into target_arch_cpu.h

From: Warner Losh Move cpu_loop() into target_cpu_loop(), and put that in target_arch_cpu.h for each architecture. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/i386/target_arch_cpu.c | 1 + bsd-user/i386/target_arch_cpu.h | 209 ++

[PULL 21/42] bsd-user: pull in target_arch_thread.h update target_arch_elf.h

From: Warner Losh Update target_arch_elf.h to remove thread_init. Move its contents to target_arch_thread.h and rename to target_thread_init(). Update elfload.c to call it. Create thread_os_thread.h to hold the os specific parts of the thread and threat manipulation routines. Currently, it just i

[PULL 23/42] bsd-user: define max args in terms of pages

From: Warner Losh For 32-bit platforms, pass in up to 256k of args. For 64-bit, bump that to 512k. Signed-off-by: Kyle Evans Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/qemu.h | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/bsd-

[PULL 25/42] bsd-user: Add system independent stack, data and text limiting

From: Warner Losh Eliminate the x86 specific stack stuff in favor of more generic control over the process size: target_maxtsiz max text size target_dfldsiz initial data size limit target_maxdsiz max data size target_dflssiz initial stack size limit target_maxssiz max sta

[PULL 11/42] bsd-user: Eliminate elf personality

From: Warner Losh The linux kernel supports a number of different ELF binaries. The Linux userland emulator inheritted some of that. And we inheritted it from there. However, for BSD there's only one kind of ELF file supported per platform, so there's no need to cope with historical quirks. Simpl

[PULL 14/42] bsd-user: elfload: simplify bswap a bit.

From: Warner Losh Reduce the number of ifdefs by always calling the swapping routine, but making them empty when swapping isn't needed. Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/elfload.c | 97 ++ 1 file changed, 47 inse

[PULL 17/42] bsd-user: Include host-os.h from main

From: Warner Losh Include host-os.h from main.c to pick up the default OS to emulate. Set that default in main(). Signed-off-by: Stacey Son Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/freebsd/host-os.h | 2 ++ bsd-user/main.c| 4 +++- bsd-user/netbsd/h

[PULL 19/42] bsd-user: start to move target CPU functions to target_arch*

From: Warner Losh Move the CPU functions into target_arch_cpu.c that are unique to each CPU. These are defined in target_arch.h. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/i386/target_arch.h | 31 + bsd-user/i386/target_

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