We extend virt machine to emulate ACLINT devices only when "aclint=on"
parameter is passed along with machine name in QEMU command-line.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
docs/system/riscv/virt.rst | 10
hw/riscv/virt.c| 113 +++
The RISC-V ACLINT is more modular and backward compatible with
original SiFive CLINT so instead of duplicating the original
SiFive CLINT implementation we upgrade the current SiFive CLINT
implementation to RISC-V ACLINT implementation.
Signed-off-by: Anup Patel
---
hw/intc/riscv_aclint.c
We re-factor and break the FDT generation into smaller functions
so that it is easier to modify FDT generation for different
configurations of virt machine.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/riscv/virt.c | 521 ++---
We will be upgrading SiFive CLINT implementation into RISC-V ACLINT
implementation so let's first rename the sources.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/intc/Kconfig| 2 +-
hw/intc/meson.build
The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement
over the SiFive CLINT but also maintains backward compatibility with
the SiFive CLINT.
Latest RISC-V ACLINT specification (will be frozen soon) can be found at:
https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
After timecmp is modified, the value is converted into nanosecond,
and pass to timer_mod. However, timer_mod perceives the value as
a signed integer. An example that goes wrong is as follows:
OpenSBI v0.9 initializes the cold boot hart's timecmp to
0x_. timer_mod then interpret
On Wed, 25 Aug 2021, Mark Cave-Ayland wrote:
> On 24/08/2021 11:09, Finn Thain wrote:
>
> > mos6522_read() and mos6522_write() may call various functions to determine
> > timer irq state, timer counter value and QEMUTimer deadline. All called
> > functions must use the same value for the present
On Tue, 24 Aug 2021, Philippe Mathieu-Daudé wrote:
> On 8/24/21 12:09 PM, Finn Thain wrote:
> > mos6522_read() and mos6522_write() may call various functions to determine
> > timer irq state, timer counter value and QEMUTimer deadline. All called
> > functions must use the same value for the pre
On Wed, 25 Aug 2021, Mark Cave-Ayland wrote:
> On 24/08/2021 11:09, Finn Thain wrote:
>
> > Signed-off-by: Finn Thain
> > ---
> > hw/misc/mos6522.c | 19 ---
> > include/hw/misc/mos6522.h | 3 +++
> > 2 files changed, 15 insertions(+), 7 deletions(-)
> >
> > diff --
On Sat, 28 Aug 2021, Andrew Randrianasulu wrote:
Hello and sorry for possible interruption.
I was browsing various projects and found Bochs 2.7 was released on August,
1 2021 [0] together with vgabios 0.8a
http://www.nongnu.org/vgabios/
"2021-06-03 vruppert Version 0.8a of the LGPL'd VGABios w
Hello and sorry for possible interruption.
I was browsing various projects and found Bochs 2.7 was released on August,
1 2021 [0] together with vgabios 0.8a
http://www.nongnu.org/vgabios/
"2021-06-03 vruppert Version 0.8a of the LGPL'd VGABios with Voodoo Banshee
for Bochs and Cirrus support for
After timecmp is modified, the value is converted into nanosecond,
and pass to timer_mod. However, timer_mod perceives the value as
a signed integer. An example that goes wrong is as follows:
OpenSBI v0.9 initializes the cold boot hart's timecmp to
0x_. timer_mod then interpret
Actually yes! I should have included a link to it:
https://github.com/facebook/openbmc-uboot/blob/openbmc/helium/v2019.04/arch/arm/dts/aspeed-bmc-facebook-fuji.dts
From: Cédric Le Goater
Date: Saturday, August 28, 2021 at 1:28 AM
To: Peter Delevoryas
Cc: j...@jms.id.au , qemu-devel@nongnu.org
I think I’m a little confused on this part. What I meant by “most machines just
use UART5” was that most DTS’s use “stdout-path=&uart5”, but fuji uses
“stdout-path=&uart1”. I do see that SCU510 includes a bit related to UART, but
it’s for disabling booting from UART1 and UART5. I just care about
Oh, thanks, I’ll remove this part!
From: Cédric Le Goater
Date: Saturday, August 28, 2021 at 1:15 AM
To: Peter Delevoryas
Cc: j...@jms.id.au , qemu-devel@nongnu.org
, qemu-...@nongnu.org
Subject: Re: [PATCH 4/5] hw/arm/aspeed: Fix AST2600_CLK_SEL3 address
On 8/27/21 11:04 PM, p...@fb.com wrote
On Fri, 27 Aug 2021 at 08:09, David Gibson wrote:
>
> The following changes since commit f214d8e0150766c31172e16ef4b17674f549d852:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20210826' into staging (2021-08-26
> 18:03:57 +0100)
>
> are available in the Git reposit
[ ... ]
> OpenBSD probably uses XIVE in a different way than Linux though.
If it is running under the skiboot firmware (Like on the Talos
system), it is necessarily using an OPAL interface, either the
P8 legacy interface (on top of XIVE HW) or the XIVE native
interface.
https://github.
On Fri, 27 Aug 2021 at 15:49, Changbin Du wrote:
>
> On Tue, Aug 24, 2021 at 10:11:14AM +0100, Peter Maydell wrote:
> > On Tue, 24 Aug 2021 at 00:05, Changbin Du wrote:
> > >
> > > On Mon, Aug 23, 2021 at 04:30:05PM +0100, Peter Maydell wrote:
> > > > changes to be more capable of handling dynami
Sunil Muthuswamy writes:
> Signed-off-by: Sunil Muthuswamy
Too late; the pull request has been merged already.
Moreover, Signed-off-by means you contributed to this patch or helped
merging it. See
https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-
On 8/27/21 11:04 PM, p...@fb.com wrote:
> From: Peter Delevoryas
>
> Fuji uses the AST2600, so it's very similar to `ast2600-evb`, but it has
> a few slight differences, such as using UART1 for the serial console.
Do we have a public DTS for this board ?
Thanks,
C.
>
> Signed-off-by: Peter
Hello Peter,
On 8/27/21 11:04 PM, p...@fb.com wrote:
> From: Peter Delevoryas
>
> The AST2500 uses different logic than the AST2600 for getting IRQ's.
> This adds a virtual `get_irq` function to the Aspeed SOC class, so that
> the shared initialization code in `hw/arm/aspeed.c` can retrieve IRQ'
On 8/27/21 11:04 PM, p...@fb.com wrote:
> From: Peter Delevoryas
>
> This change replaces the UART serial device initialization code with machine
> configuration data, making it so that we have a single code path for console
> UART initialization, but allowing different machines to use different
On 8/27/21 11:04 PM, p...@fb.com wrote:
> From: Peter Delevoryas
>
> UART5 is typically used as the default debug UART on the AST2600, but
> UART1 is also designed to be a debug UART. All the AST2600 UART's have
> semi-configurable clock rates through registers in the System Control
> Unit (SCU),
On 8/27/21 11:04 PM, p...@fb.com wrote:
> From: Peter Delevoryas
>
> This register address is not actually used anywhere, and the datasheet
> specifies that it's zero-initialized by default anyways, but the address
> is incorrect. This just corrects the address.
>
> Fixes: e09cf36321f6 ("hw: asp
On Fri, Aug 27, 2021 at 11:15:26PM +0200, BALATON Zoltan wrote:
> On Fri, 27 Aug 2021, John Arbuckle wrote:
> > I was having a problem with missing video resolutions in my Mac OS 9 VM.
> > When I
> > ran QEMU it gave no indication as to why these resolutions were missing. I
> > found
> > out that
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