On Thu, Aug 19, 2021 at 1:22 PM Tong Ho wrote:
>
> Add unimplemented APU mmio region to xlnx-zynqmp for booting
> bare-metal guests built with standalone bsp published at:
>
> https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit
>
> Signed-off-by: Tong Ho
Ac
On Thu, Aug 19, 2021 at 1:20 PM Tong Ho wrote:
>
> Add unimplemented APU mmio region to xlnx-versal for booting
> bare-metal guests built with standalone bsp published at:
>
> https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit
>
> Signed-off-by: Tong Ho
Ac
On Wed, Aug 18, 2021 at 7:23 AM Richard Henderson
wrote:
>
> Split out gen_mulh and gen_mulhu and use the common helper.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvm.c.inc | 40 +++--
> 1 file change
On Wed, Aug 18, 2021 at 7:21 AM Richard Henderson
wrote:
>
> Use ctx->w and the enhanced gen_arith function.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c| 42 -
> target/riscv/insn_trans/t
On Wed, Aug 18, 2021 at 7:23 AM Richard Henderson
wrote:
>
> Most arithmetic does not require extending the inputs.
> Exceptions include division, comparison and minmax.
>
> Begin using ctx->w, which allows elimination of gen_addw,
> gen_subw, gen_mulw.
>
> Signed-off-by: Richard Henderson
Revie
On Wed, Aug 18, 2021 at 7:23 AM Richard Henderson
wrote:
>
> Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force
> tcg globals into temps, returning a constant 0 for $zero as source and
> a new temp for $zero as destination.
>
> Introduce ctx->w for simplifying word operations,
On Wed, Aug 18, 2021 at 5:29 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 36 +
> 1 file changed, 19 insertions(+), 17 deletions(-)
>
Reviewed-by: Bin Meng
On Wed, Aug 18, 2021 at 7:21 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c| 58 -
> target/riscv/insn_trans/trans_rva.c.inc | 18
> target/riscv/insn_tr
On Wed, Aug 18, 2021 at 5:26 AM Richard Henderson
wrote:
>
> Narrow the scope of t0 in trans_jalr.
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 25 ++---
> 1 file changed, 10 insertions(+), 15 deletions(-)
>
Reviewed-by: Bin Meng
On Thu, Aug 19, 2021 at 6:14 AM Richard Henderson
wrote:
>
> There is nothing target specific about this. The implementation
> is host specific, but the declaration is 100% common.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> include/exec/exec-all.h |
On Thu, Aug 19, 2021 at 5:45 AM Richard Henderson
wrote:
>
> We're about to move this out of tcg.h, so rename it
> as we did when moving MemOp.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> accel/tcg/atomic_template
On Thu, Aug 19, 2021 at 5:41 AM Richard Henderson
wrote:
>
> We have lacked expressive support for memory sizes larger
> than 64-bits for a while. Fixing that requires adjustment
> to several points where we used this for array indexing,
> and two places that develop -Wswitch warnings after the c
On Thu, Aug 19, 2021 at 5:23 AM Richard Henderson
wrote:
>
> While we may have had some thought of allowing system-mode
> to return from this hook, we have no guests that require this.
>
> Reviewed-by: Alex Bennée
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewe
On Tue, Aug 17, 2021 at 1:25 PM Yifei Jiang wrote:
>
> Use char-fe to handle console sbi call, which implement early
> console io while apply 'earlycon=sbi' into kernel parameters.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> ---
> target/riscv/kvm.c | 42 ++
On Wed, Aug 18, 2021 at 5:26 AM Richard Henderson
wrote:
>
> These operations are greatly simplified by ctx->w, which allows
> us to fold gen_shiftw into gen_shift. Split gen_shifti into
> gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}.
>
> Signed-off-by: Richard Henderson
> ---
> t
`muldiv64` would overflow in cases where the final 96-bit value does not
fit in a `uint64_t`. This would result in small values that cause an
interrupt to be triggered much sooner than intended.
The overflow can be detected in most cases by checking if the new value is
smaller than the previous va
> I think this will be more clear once I get the patch posted (which I haven't
> started
> writing yet). I'll try to get it posted by tomorrow evening though, since I
> have
> vacation on Friday.
While Andrew is working on the patch in a hurry,
I'm sorry, I'll be on vacation for a while startin
This implements the Xilinx ZynqMP eFuse, an one-time
field-programmable non-volatile storage device. There is
only one such device in the Xilinx ZynqMP product family.
The command argument:
-drive if=pflash,index=N,...
Can be used to optionally connect the storage array to a
backend storage, su
This series implements the Xilinx eFUSE and BBRAM devices for
the Versal and ZynqMP product families.
Furthermore, both new devices are connected to the xlnx-versal-virt
board and the xlnx-zcu102 board.
See changes in docs/system/arm/xlnx-versal-virt.rst for detail.
Tong Ho (9):
docs/system/ar
This implements the Xilinx Versal eFuse, an one-time
field-programmable non-volatile storage device. There is
only one such device in the Xilinx Versal product family.
The command argument:
-drive if=pflash,index=N,...
Can be used to optionally connect the storage array to a
backend storage, su
This device is present in Versal and ZynqMP product
families to store a 256-bit encryption key.
Co-authored-by: Edgar E. Iglesias
Co-authored-by: Sai Pavan Boddu
Signed-off-by: Edgar E. Iglesias
Signed-off-by: Sai Pavan Boddu
Signed-off-by: Tong Ho
---
hw/nvram/Kconfig | 4 +
Add BBRAM and eFUSE usage to the Xilinx Versal Virt board
document.
Signed-off-by: Tong Ho
---
docs/system/arm/xlnx-versal-virt.rst | 49
1 file changed, 49 insertions(+)
diff --git a/docs/system/arm/xlnx-versal-virt.rst
b/docs/system/arm/xlnx-versal-virt.rst
index
Connect the support for ZynqMP eFUSE one-time field-programmable
bit array.
Signed-off-by: Tong Ho
---
hw/arm/xlnx-zynqmp.c | 29 +
include/hw/arm/xlnx-zynqmp.h | 3 +++
2 files changed, 32 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp
Connect the support for Versal eFUSE one-time field-programmable
bit array.
Signed-off-by: Tong Ho
---
hw/arm/xlnx-versal-virt.c| 36 +
hw/arm/xlnx-versal.c | 39
include/hw/arm/xlnx-versal.h | 12 +++
3 fil
This introduces the QOM for Xilinx eFuse, an one-time
field-programmable storage bit array.
The actual mmio interface to the array varies by device
families and will be provided in different change-sets.
Co-authored-by: Edgar E. Iglesias
Co-authored-by: Sai Pavan Boddu
Signed-off-by: Edgar E.
Connect the support for Versal Battery-Backed RAM (BBRAM)
Signed-off-by: Tong Ho
---
hw/arm/xlnx-versal-virt.c| 21 +
hw/arm/xlnx-versal.c | 18 ++
include/hw/arm/xlnx-versal.h | 5 +
3 files changed, 44 insertions(+)
diff --git a/hw/arm/xlnx
Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM)
Signed-off-by: Tong Ho
---
hw/arm/xlnx-zynqmp.c | 21 +
include/hw/arm/xlnx-zynqmp.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 3597e8db4d.
Put both sanity-check of the input SMP configuration and sanity-check
of the output SMP configuration uniformly in the generic parser. Then
machine_set_smp() will become cleaner, also all the invalid scenarios
can be tested only by calling the parser.
Signed-off-by: Yanan Wang
Reviewed-by: Andrew
Now we have a generic smp parser for all arches, and there will
not be any other arch specific ones, so let's remove the callback
from MachineClass and call the parser directly.
Signed-off-by: Yanan Wang
Reviewed-by: Andrew Jones
---
hw/core/machine.c | 3 +--
include/hw/boards.h | 5 -
2
Add a QEMU unit test for the parsing of given SMP configuration.
Since all the parsing logic is in generic function smp_parse(),
this test passes different SMP configurations to the function
and compare the parsing result with what is expected.
In the test, all possible collections of the topology
Now we have a common structure SMPCompatProps used to store information
about SMP compatibility stuff, so we can also move smp_prefer_sockets
there for cleaner code.
No functional change intended.
Signed-off-by: Yanan Wang
Acked-by: David Gibson
Reviewed-by: Andrew Jones
---
hw/arm/virt.c
Add unimplemented APU mmio region to xlnx-zynqmp for booting
bare-metal guests built with standalone bsp published at:
https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit
Signed-off-by: Tong Ho
---
hw/arm/xlnx-zynqmp.c | 32 +
Now that all the possible topology parameters are integrated in struct
CpuTopology, tweak the order of topology members to be "cpus/sockets/
dies/cores/threads/maxcpus" for readability and consistency. We also
tweak the comment by adding explanation of dies parameter.
Signed-off-by: Yanan Wang
Re
Currently the only difference between smp_parse and pc_smp_parse
is the support of dies parameter and the related error reporting.
With some arch compat variables like "bool dies_supported", we can
make smp_parse generic enough for all arches and the PC specific
one can be removed.
Making smp_pars
Add unimplemented APU mmio region to xlnx-versal for booting
bare-metal guests built with standalone bsp published at:
https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit
Signed-off-by: Tong Ho
---
hw/arm/xlnx-versal.c | 2 ++
include/hw/arm/xlnx-ve
This series adds the APU mmio region as an unimplemented device
to each of two Xilinx SoC to support booting guests built with
the standalone bsp published at:
https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit
Tong Ho (2):
hw/arm/xlnx-versal: Add unimplem
In the real SMP hardware topology world, it's much more likely that
we have high cores-per-socket counts and few sockets totally. While
the current preference of sockets over cores in smp parsing results
in a virtual cpu topology with low cores-per-sockets counts and a
large number of sockets, whic
Add 6.2 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Yanan Wang
Acked-by: David Gibson
Reviewed-by: Andrew Jones
Reviewed-by: Cornelia Huck
Reviewed-by: Pankaj Gupta
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c
We are going to introduce an unit test for the parser smp_parse()
in hw/core/machine.c, but now machine.c is only built in softmmu.
In order to solve the build dependency on the smp parsing code and
avoid building unrelated stuff for the unit tests, move the related
code from machine.c into a new
There are two places describing the same thing about deprecation
of invalid topologies of -smp CLI, so remove the duplicated one.
Signed-off-by: Yanan Wang
---
docs/about/removed-features.rst | 21 -
1 file changed, 4 insertions(+), 17 deletions(-)
diff --git a/docs/about/re
We are currently using maxcpus to calculate the omitted sockets
but using cpus to calculate the omitted cores/threads. This makes
cmdlines like:
-smp cpus=8,maxcpus=16
-smp cpus=8,cores=4,maxcpus=16
-smp cpus=8,threads=2,maxcpus=16
work fine but the ones like:
-smp cpus=8,sockets=2,maxcpus=
In the SMP configuration, we should either provide a topology
parameter with a reasonable value (greater than zero) or just
omit it and QEMU will compute the missing value.
The users shouldn't provide a configuration with any parameter
of it specified as zero (e.g. -smp 8,sockets=0) which could
po
In the sanity-check of smp_cpus and max_cpus against mc in function
machine_set_smp(), we are now using ms->smp.max_cpus for the check
but using current_machine->smp.max_cpus in the error message.
Tweak this by uniformly using the local ms.
Signed-off-by: Yanan Wang
Reviewed-by: Andrew Jones
Rev
To pave the way for the functional improvement in later patches,
make some refactor/cleanup for the smp parsers, including using
local maxcpus instead of ms->smp.max_cpus in the calculation,
defaulting dies to 0 initially like other members, cleanup the
sanity check for dies.
We actually also fix
We have two requirements for a valid SMP configuration:
the product of "sockets * cores * threads" must represent all the
possible cpus, i.e., max_cpus, and then must include the initially
present cpus, i.e., smp_cpus.
So we only need to ensure 1) "sockets * cores * threads == maxcpus"
at first an
Rebased on upstream v6.1.0-rc4 with two more patches added.
This series introduces some fixes and improvement for the SMP parsing.
Behavior of specifying a CPU topology parameter as zero was implicitly
allowed but undocumented before, while now it's explicitly deprecated.
maxcpus is now uniformly
Currently we directly calculate the omitted cpus based on the given
incomplete collection of parameters. This makes some cmdlines like:
-smp maxcpus=16
-smp sockets=2,maxcpus=16
-smp sockets=2,dies=2,maxcpus=16
-smp sockets=2,cores=4,maxcpus=16
not work. We should probably set the value of
On Wed, Aug 18, 2021 at 5:18 AM Richard Henderson
wrote:
>
> Move these helpers near their use by the trans_*
> functions within insn_trans/trans_rvm.c.inc.
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/translate.c| 112
> target/riscv/insn_tr
On Wed, Aug 18, 2021 at 5:21 AM Richard Henderson
wrote:
>
> Move these helpers near their use by the trans_*
> functions within insn_trans/trans_rvb.c.inc.
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/translate.c| 233 ---
> target/riscv/insn_tra
On Wed, Aug 18, 2021 at 5:23 AM Richard Henderson
wrote:
>
> Split out gen_mulh and gen_mulhu and use the common helper.
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/insn_trans/trans_rvm.c.inc | 40 +++--
> 1 file changed, 18 insertions(+), 22 deletions(-)
>
Rev
On Wed, Aug 18, 2021 at 5:20 AM Richard Henderson
wrote:
>
> Use ctx->w and the enhanced gen_arith function.
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/translate.c| 42 -
> target/riscv/insn_trans/trans_rvm.c.inc | 16 +-
> 2 files c
On Wed, Aug 18, 2021 at 5:23 AM Richard Henderson
wrote:
>
> Most arithmetic does not require extending the inputs.
> Exceptions include division, comparison and minmax.
>
> Begin using ctx->w, which allows elimination of gen_addw,
> gen_subw, gen_mulw.
>
> Signed-off-by: Richard Henderson
> ---
On 8/18/21 12:58 AM, Bin Meng wrote:
+TCGv temp[4];
Why is 4? Is it enough? Perhaps a comment here is needed here?
It's a round number that will cover three operands plus an extra for address
computation.
r~
When COLO use only one vnet_hdr_support parameter between
COLO network filter(filter-mirror, filter-redirector or
filter-rewriter and colo-compare, packet will not be parsed
correctly. Acquire network driver related to COLO, if it is
nirtio-net, check vnet_hdr_support flag of COLO network filter
an
On 8/18/21 12:58 AM, Bin Meng wrote:
+static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
+{
+if (reg_num != 0) {
+if (ctx->w) {
+tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
What about zero extension?
All of the RV64 word instructions sign-extend the result.
On 8/18/21 10:32 AM, Philipp Tomsich wrote:
The ratification package for Zb[abcs] does not contain all instructions
that have been added to QEmu and don't define misa.B for these: the
individual extensions are now Zba, Zbb, Zbc and Zbs.
Some of the instructions that had previously been added and
On Tue, Aug 17, 2021 at 6:00 PM Bin Meng wrote:
>
> On Tue, Aug 17, 2021 at 2:38 AM David Hoppenbrouwers
> wrote:
> >
> > `next` is an `uint64_t` value, but `timer_mod` takes an `int64_t`. This
> > resulted in high values such as `UINT64_MAX` being converted to `-1`,
> > which caused an immediat
I will provide a v3 to restore bisectability,
On Thu, 19 Aug 2021 at 00:39, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 8/18/21 10:32 AM, Philipp Tomsich wrote:
> > +++ b/target/riscv/cpu.h
> > @@ -67,7 +67,6 @@
> > #define RVS RV('S')
> > #define RVU RV('U')
> > #define R
On 8/18/21 10:32 AM, Philipp Tomsich wrote:
+++ b/target/riscv/cpu.h
@@ -67,7 +67,6 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
-#define RVB RV('B')
This patch does not compile by itself, because RVB is still used in
insn_trans/trans_rvb.c.inc.
r~
On 8/18/21 11:55 AM, Philippe Mathieu-Daudé wrote:
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.
We can remove one use of the T
On 8/18/21 11:55 AM, Philippe Mathieu-Daudé wrote:
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.
We can remove another use of t
On 8/18/21 11:55 AM, Philippe Mathieu-Daudé wrote:
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
As a first step, inline the GET_OFFSET() macro, calling
cpu_is_bigendian() to get the 'direction' of the offset.
Signed-off-by: Philippe Mathieu-Dau
On 8/18/21 11:31 AM, Philippe Mathieu-Daudé wrote:
I think you should drop
get_offset() entirely and replace it with
int dir = cpu_is_bigendian(env) ? 1 : -1;
stb(env, arg2 + 1 * dir, data);
stb(env, arg2 + 2 * dir, data);
Alternately, bite the bullet and split the function(
On 8/18/21 10:19 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/region.c | 91
> 1 file changed, 91 deletions(-)
Yay!
Reviewed-by: Philippe Mathieu-Daudé
On 8/18/21 10:19 PM, Richard Henderson wrote:
> Only use indirect jumps. Finish weaning away from the
> unique alignment requirements for code_gen_buffer.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/mips/tcg-target.h | 12 +---
> tcg/mips/tcg-target.c.inc | 23 +
On 8/18/21 10:19 PM, Richard Henderson wrote:
> No functional change; just moving the saved reserved regs to the end.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/mips/tcg-target.c.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tcg/mips/tcg-target.c.inc b/tcg/m
On 8/18/21 10:19 PM, Richard Henderson wrote:
> No functional change; just moving the saved reserved regs to the end.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/mips/tcg-target.h | 2 +-
> tcg/mips/tcg-target.c.inc | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-
Sorry, use Huacai's newer email .
On Thu, Aug 19, 2021 at 12:07 AM Philippe Mathieu-Daudé wrote:
>
> Cc'ing Jiaxun & Huacai.
>
> On 8/18/21 10:19 PM, Richard Henderson wrote:
> > Based-on: <20210818191920.390759-1-richard.hender...@linaro.org>
> > ("[PATCH v3 00/66] Unaligned access for user-only
Cc'ing Jiaxun & Huacai.
On 8/18/21 10:19 PM, Richard Henderson wrote:
> Based-on: <20210818191920.390759-1-richard.hender...@linaro.org>
> ("[PATCH v3 00/66] Unaligned access for user-only")
>
> Important points:
> * Support unaligned accesses.
> * Drop requirement for 256MB alignment of code
On 8/18/21 11:29 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/arm/tcg-target.c.inc | 65 +---
> 1 file changed, 35 insertions(+), 30 deletions(-)
I like it :)
Reviewed-by: Philippe Mathieu-Daudé
On 8/18/21 11:29 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/arm/tcg-target.c.inc | 20 ++--
> 1 file changed, 10 insertions(+), 10 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 8/18/21 11:29 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/arm/tcg-target.c.inc | 136 +++
> 1 file changed, 68 insertions(+), 68 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 8/18/21 11:29 PM, Richard Henderson wrote:
> Let the compiler decide about inlining.
> Remove tcg_out_nop as unused.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/arm/tcg-target.c.inc | 234 +++
> 1 file changed, 114 insertions(+), 120 deletions(-)
Revi
On 8/18/21 11:29 PM, Richard Henderson wrote:
> Some of the functions specified _reg, some _imm, and some
> left it blank. Make it clearer to which we are referring.
>
> Split tcg_out_b_reg from tcg_out_bx_reg, to indicate when
> we do not actually require BX semantics.
>
> Signed-off-by: Richar
Most TCG helpers only have access to a DisasContext pointer,
not CPUMIPSState. Store a copy of CPUMIPSState::CP0_Config0
in DisasContext so we can access it from TCG helpers.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210818164321.2474534-5-f4...@amsat.or
Add the inlined cpu_is_bigendian() function in "translate.h".
Replace the TARGET_WORDS_BIGENDIAN #ifdef'ry by calls to
cpu_is_bigendian().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210818164321.2474534-6-f4...@amsat.org>
---
target/mips/tcg/translate.h
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.
We can remove another use of the TARGET_WORDS_BIGENDIAN definition.
Signed-off-by:
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.
We can remove one use of the TARGET_WORDS_BIGENDIAN definition.
Signed-off-by: Phi
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
As a first step, inline the GET_OFFSET() macro, calling
cpu_is_bigendian() to get the 'direction' of the offset.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/ldst_helper.c | 55 +
Missing review: 1-3
MIPS CPU store its endianess in the CP0 Config0 register.
Use that runtime information instead of #ifdef'ry checking
TARGET_WORDS_BIGENDIAN by introducing the cpu_is_bigendian()
helper.
Since v1:
- Addressed rth's comments (call cpu_is_bigendian/get_lmask once)
- Add rth R-b o
On 8/18/21 6:56 PM, Richard Henderson wrote:
> On 8/18/21 6:43 AM, Philippe Mathieu-Daudé wrote:
>> The target endianess information is stored in the BigEndian
>> bit of the Config0 register in CP0.
>>
>> As a first step, replace the GET_OFFSET() macro by an inlined
>> get_offset() function, passin
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 65 +---
1 file changed, 35 insertions(+), 30 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 2f55b94ada..35bd4c68d6 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b
On 8/18/21 3:04 PM, Dr. David Alan Gilbert wrote:
* Tobin Feldman-Fitzthum (to...@linux.ibm.com) wrote:
On 8/17/21 6:04 PM, Steve Rutherford wrote:
Ahh, It sounds like you are looking into sidestepping the existing
AMD-SP flows for migration. I assume the idea is to spin up a VM on
the target s
For v6+, use ldm/stm, ldrd/strd for the normal case of alignment
matching the access size. Otherwise, emit a test + branch sequence
invoking helper_unaligned_{ld,st}.
For v4+v5, use piecewise load and stores to implement misalignment.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h
Use the environment variable to test an older ISA from
the one supported by the host.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 8 +++-
tcg/arm/tcg-target.c.inc | 32
2 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/tcg/ar
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index b20c313615..2f55b94ada 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.
Some of the functions specified _reg, some _imm, and some
left it blank. Make it clearer to which we are referring.
Split tcg_out_b_reg from tcg_out_bx_reg, to indicate when
we do not actually require BX semantics.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 38
We have already computed the rotated value of the imm8
portion of the complete imm12 encoding. No sense leaving
the combination of rot + rotation to the caller.
Create an encode_imm12_nofail helper that performs an assert.
This removes the final use of the local "rotl" function,
which duplicated
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 136 +++
1 file changed, 68 insertions(+), 68 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 327032f0df..b20c313615 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b
ARMv4T has BX as its only interworking instruction. In order
to support testing of different architecture revisions with a
qemu binary that may have been built for, say ARMv6T2, fill in
the blank required to make calls to helpers in thumb mode.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-t
Expand these hard-coded instructions symbolically.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index c55167cc84..63b786a3e5 100644
--- a/
On 8/18/21 7:09 PM, Richard Henderson wrote:
> On 8/18/21 6:43 AM, Philippe Mathieu-Daudé wrote:
>> - if (GET_LMASK(arg2) <= 2) {
>> + if (get_lmask(env, arg2, 32) <= 2) {
>
> Whatever you decide to do with respect to the previous patch, the result
> of get_lmask is constant across the funct
Let the compiler decide about inlining.
Remove tcg_out_nop as unused.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 234 +++
1 file changed, 114 insertions(+), 120 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
Based-on: <20210818191920.390759-1-richard.hender...@linaro.org>
("[PATCH v3 00/66] Unaligned access for user-only")
Important points:
* Support unaligned accesses.
* Add environment variable to for testing older architecture revs.
* More use of enum types.
r~
Richard Henderson (14):
t
>From armv6, the architecture supports unaligned accesses.
All we need to do is perform the correct alignment check
in tcg_out_tlb_read and not use LDRD/STRD when the access
is not aligned.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 69 ++-
According to the Arm ARM DDI 0406C, section A1.3, the valid variants
are ARMv5T, ARMv5TE, ARMv5TEJ -- there is no ARMv5 without Thumb.
Therefore simplify the test from preprocessor ifdefs to base
architecture revision. Retain the "t" in the name to minimize churn.
Signed-off-by: Richard Henderson
Reserve a register for the guest_base using aarch64 for reference.
By doing so, we do not have to recompute it for every memory load.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 39 ---
1 file changed, 28 insertions(+), 11 deletions(-)
dif
GCC since 4.8 provides the definition and we now require 7.5.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 19 ---
1 file changed, 19 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index d113b7f8db..18bb16c784 100644
--- a/tcg/arm/tcg-target
On 8/18/21 9:19 PM, Richard Henderson wrote:
> Having observed e.g. al8+leq in dumps, canonicalize to al+leq.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tcg-op.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
Nice.
Reviewed-by: Philippe Mathieu-Daudé
On 8/18/21 9:19 PM, Richard Henderson wrote:
> There is nothing target specific about this. The implementation
> is host specific, but the declaration is 100% common.
>
> Signed-off-by: Richard Henderson
> ---
> include/exec/exec-all.h | 13 +
> target/alpha/cpu.h | 6 --
>
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