>From f780b0ee2ee36c562ab814915fff0e7217b25e63 Mon Sep 17 00:00:00 2001
From: Jianxian Wen
Date: Tue, 3 Aug 2021 09:44:35 +0800
Subject: [PATCH] hw/dma/pl330: Add memory region to replace default
address_space_memory
PL330 needs a memory region which can connect with SMMU translate IOMMU region
On Fri, Aug 6, 2021 at 3:59 AM Ruinland Chuan-Tzu Tsai
wrote:
>
> From: Ruinland ChuanTzu Tsai
>
> Dear all,
>
> In this patch, the implementation of custom CSR handling logic is introduced.
>
> If --enable-riscv-custom is set during configuration, custom CSR logic will be
> turned on. During CPU
On Fri, Aug 6, 2021 at 11:06 PM Jessica Clarke wrote:
>
> > From: Ruinalnd ChuanTzu Tsai
> >
> > In this patch we enabled custom CSR logic for Andes AX25 and A25 logic.
> > Hence csr_andes.inc.c and andes_cpu_bits.h is added.
> >
> > Signed-off-by: Dylan Jhong
> > ---
> > target/riscv/andes_cpu
On Fri, Aug 6, 2021 at 7:51 PM Bin Meng wrote:
>
> On Fri, Aug 6, 2021 at 2:12 PM Ruinland Chuan-Tzu Tsa(蔡傳資)
> wrote:
> >
> > Hi Bin and Alistair,
> >
> > >> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without
> >
> > > The latest RISC-V core from Andes is AX45 and A45. Should we ju
On Fri, Aug 6, 2021 at 3:58 AM Ruinland Chuan-Tzu Tsai
wrote:
>
> From: Ruinalnd ChuanTzu Tsai
>
> For now we add a custom CSR handling mechanism to handle non-standard CSR read
> or write.
>
> The write_stub() and read_zero() are provided for quick placeholder usage if
> such CSRs' behavior are
Hi Jason,
Do you have any comments on this patch?
Thank you!
On 8/6/2021 2:08 PM, Xu, Tao3 wrote:
When COLO use only one vnet_hdr_support parameter between
COLO network filter(filter-mirror, filter-redirector or
filter-rewriter and colo-compare, packet will not be parsed
correctly. Acquire net
On Fri, Aug 6, 2021 at 11:54 PM Bin Meng wrote:
>
> On Fri, Aug 6, 2021 at 8:58 PM Jessica Clarke wrote:
> >
> > > On Fri, Aug 6, 2021 at 10:39 AM Bin Meng wrote:
> > > >
> > > > On Fri, Aug 6, 2021 at 1:57 AM Ruinland Chuan-Tzu Tsai
> > > > wrote:
> > > > >
> > > > > From: Ruinland ChuanTzu Ts
On Thu, Aug 12, 2021 at 7:52 PM Peter Maydell wrote:
>
> All the devices that used to use system_clock_scale have now been
> converted to use Clock inputs instead, so the global is no longer
> needed; remove it and all the code that sets it.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alistair
In migration resume phase, all unmasked msix vectors need to be
setup when load the VF state. However, the setup operation would
takes longer if the VF has more unmasked vectors.
In our case, the VF has 65 vectors and each one spend 0.8ms on
setup operation (vfio_add_kvm_msi_virq -> kvm_irqchip_co
Hi Alex,
Recently I was reading the DMA call-back functions in the fuzzer. It seems
fuzz_dma_read_cb() is inserted into flatview_read_continue() and
address_space_map() to make the host read changed content between different
DMA actions.
My question is about address_space_map() -- How do we emula
Don't allocate the string until error conditions have been checked
Fixes: a00cfed0e ("Hexagon (disas) disassembler")
Eliminate Coverity CID 1460121 (Resource leak)
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daud?
Signed-off-by: Taylor Simpson
---
disas/hexagon.c | 3 ++-
1 file
The following changes since commit 703e8cd6189cf699c8d5c094bc68b5f3afa6ad71:
Update version for v6.1.0-rc3 release (2021-08-10 19:08:09 +0100)
are available in the git repository at:
https://github.com/quic/qemu tags/pull-hex-20210812
for you to fetch changes up to
We are going to introduce an unit test for the parser smp_parse()
in hw/core/machine.c, but now machine.c is only built in softmmu.
In order to solve the build dependency on the smp parsing code and
avoid building unrelated stuff for the unit tests, move the related
code from machine.c into a new
Put both sanity-check of the input SMP configuration and sanity-check
of the output SMP configuration uniformly in the generic parser. Then
machine_set_smp() will become cleaner, also all the invalid scenarios
can be tested only by calling the parser.
Signed-off-by: Yanan Wang
Reviewed-by: Andrew
Now we have a generic smp parser for all arches, and there will
not be any other arch specific ones, so let's remove the callback
from MachineClass and call the parser directly.
Signed-off-by: Yanan Wang
Reviewed-by: Andrew Jones
---
hw/core/machine.c | 3 +--
include/hw/boards.h | 5 -
2
Currently the only difference between smp_parse and pc_smp_parse
is the support of dies parameter and the related error reporting.
With some arch compat variables like "bool dies_supported", we can
make smp_parse generic enough for all arches and the PC specific
one can be removed.
Making smp_pars
Add 6.2 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Yanan Wang
Acked-by: David Gibson
Reviewed-by: Andrew Jones
Reviewed-by: Cornelia Huck
Reviewed-by: Pankaj Gupta
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c
Hi,
This is new version (v5 with a little update in patch #6) of the series [1]
that I have posted to introduce some fixes and improvement for SMP parsing.
[1]
https://lore.kernel.org/qemu-devel/20210803080527.156556-1-wangyana...@huawei.com/
Most of this series is about the SMP parsers:
maxcpu
Now that all the possible topology parameters are integrated in struct
CpuTopology, tweak the order of topology members to be "cpus/sockets/
dies/cores/threads/maxcpus" for readability and consistency. We also
tweak the comment by adding explanation of dies parameter.
Signed-off-by: Yanan Wang
Re
Currently we directly calculate the omitted cpus based on the given
incomplete collection of parameters. This makes some cmdlines like:
-smp maxcpus=16
-smp sockets=2,maxcpus=16
-smp sockets=2,dies=2,maxcpus=16
-smp sockets=2,cores=4,maxcpus=16
not work. We should probably set the value of
Add a QEMU unit test for the parsing of given SMP configuration.
Since all the parsing logic is in generic function smp_parse(),
this test passes different SMP configurations to the function
and compare the parsing result with what is expected.
In the test, all possible collections of the topology
To pave the way for the functional improvement in later patches,
make some refactor/cleanup for the smp parsers, including using
local maxcpus instead of ms->smp.max_cpus in the calculation,
defaulting dies to 0 initially like other members, cleanup the
sanity check for dies.
No functional change
In the sanity-check of smp_cpus and max_cpus against mc in function
machine_set_smp(), we are now using ms->smp.max_cpus for the check
but using current_machine->smp.max_cpus in the error message.
Tweak this by uniformly using the local ms.
Signed-off-by: Yanan Wang
Reviewed-by: Andrew Jones
Rev
Now we have a common structure SMPCompatProps used to store information
about SMP compatibility stuff, so we can also move smp_prefer_sockets
there for cleaner code.
No functional change intended.
Signed-off-by: Yanan Wang
Acked-by: David Gibson
Reviewed-by: Andrew Jones
---
hw/arm/virt.c
In the real SMP hardware topology world, it's much more likely that
we have high cores-per-socket counts and few sockets totally. While
the current preference of sockets over cores in smp parsing results
in a virtual cpu topology with low cores-per-sockets counts and a
large number of sockets, whic
We are currently using maxcpus to calculate the omitted sockets
but using cpus to calculate the omitted cores/threads. This makes
cmdlines like:
-smp cpus=8,maxcpus=16
-smp cpus=8,cores=4,maxcpus=16
-smp cpus=8,threads=2,maxcpus=16
work fine but the ones like:
-smp cpus=8,sockets=2,maxcpus=
We have two requirements for a valid SMP configuration:
the product of "sockets * cores * threads" must represent all the
possible cpus, i.e., max_cpus, and then must include the initially
present cpus, i.e., smp_cpus.
So we only need to ensure 1) "sockets * cores * threads == maxcpus"
at first an
On Tue, Aug 10, 2021 at 11:48 AM LIU Zhiwei wrote:
>
> For U-mode CSRs, read-only check is also needed.
>
> Signed-off-by: LIU Zhiwei
> Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
>
On Thu, Aug 12, 2021 at 7:44 PM Peter Maydell wrote:
>
> Delete the trailing blank line at the end of the source file.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/stm32vldiscovery.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/arm/stm3
On Thu, Aug 12, 2021 at 7:38 PM Peter Maydell wrote:
>
> Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board
On Thu, Aug 12, 2021 at 7:41 PM Peter Maydell wrote:
>
> Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board
On Thu, Aug 12, 2021 at 7:37 PM Peter Maydell wrote:
>
> Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board
On Thu, Aug 12, 2021 at 7:37 PM Peter Maydell wrote:
>
> In the realize methods of the stm32f100 and stm32f205 SoC objects, we
> call g_new() to create new MemoryRegion objjects for the sram, flash,
> and flash_alias. This is unnecessary (and leaves open the
> possibility of leaking the allocatio
On Thu, Aug 12, 2021 at 7:38 PM Peter Maydell wrote:
>
> It is quite common for a clock tree to involve possibly programmable
> clock multipliers or dividers, where the frequency of a clock is for
> instance divided by 8 to produce a slower clock to feed to a
> particular device.
>
> Currently we
On Thu, Aug 12, 2021 at 7:42 PM Peter Maydell wrote:
>
> Wire up the cpuclk for the systick devices to the SSE object's
> existing mainclk clock.
>
> We do not wire up the refclk because the SSE subsystems do not
> provide a refclk. (This is documented in the IoTKit and SSE-200
> TRMs; the SSE-30
On Thu, Aug 12, 2021 at 7:38 PM Peter Maydell wrote:
>
> Create input clocks on the armv7m container object which pass through
> to the systick timers, so that users of the armv7m object can specify
> the clocks being used.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alistair Francis
Alistai
On Thu, Aug 12, 2021 at 7:36 PM Peter Maydell wrote:
>
> The v7M systick timer can be programmed to run from either of
> two clocks:
> * an "external reference clock" (when SYST_CSR.CLKSOURCE == 0)
> * the main CPU clock (when SYST_CSR.CLKSOURCE == 1)
>
> Our implementation currently hardwires t
On Thu, Aug 12, 2021 at 7:34 PM Peter Maydell wrote:
>
> Add the usual-style QEMU interface comment documenting what
> properties, etc, this device exposes.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alistair Francis
Alistair
> ---
> include/hw/timer/armv7m_systick.h | 7 +++
> 1 file
On Thu, Aug 12, 2021 at 7:36 PM Peter Maydell wrote:
>
> There's no particular reason why the NVIC should be owning the
> SysTick device objects; move them into the ARMv7M container object
> instead, as part of consolidating the "create the devices which are
> built into an M-profile CPU and map t
On Thu, Aug 12, 2021 at 7:34 PM Peter Maydell wrote:
>
> Currently we implement the RAS register block within the NVIC device.
> It isn't really very tightly coupled with the NVIC proper, so instead
> move it out into a sysbus device of its own and have the top level
> ARMv7M container create it a
On Fri, Aug 13, 2021 at 2:17 AM Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 8/12/21 4:46 PM, Peter Maydell wrote:
> > In the riscv virt machine init function, We assemble a string
> > plic_hart_config which is a comma-separated list of N copies of the
> > VIRT_PLIC_HART_CONFIG string. The
On Thu, Aug 12, 2021 at 12:46 AM LIU Zhiwei wrote:
>
> For some cpu, the isa version has already been set in cpu init function.
> Thus only override the isa version when isa version is not set, or
> users set different isa version explicitly by cpu parameters.
>
> Signed-off-by: LIU Zhiwei
Revie
On 8/12/21 11:24 AM, Daniel Henrique Barboza wrote:
+void helper_insns_inc(CPUPPCState *env)
+{
+ env->pmu_insns_count++;
+}
+
+void helper_insns_dec(CPUPPCState *env)
+{
+ env->pmu_insns_count--;
+}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 60f35360b7..c56c656694 1
On 8/12/21 7:17 AM, Daniel Henrique Barboza wrote:
On 8/12/21 1:56 AM, Richard Henderson wrote:
On 8/11/21 6:45 PM, Richard Henderson wrote:
On 8/11/21 5:39 PM, David Gibson wrote:
I mean, nothing is stopping us from calculating cycles using time, but in the
end we would do the same thing
On 8/12/21 9:10 AM, matheus.fe...@eldorado.org.br wrote:
static bool avr_need_swap(CPUPPCState *env)
{
+bool le;
+#if defined(CONFIG_USER_ONLY)
+le = false;
+#else
+le = msr_le;
+#endif
It certainly doesn't seem like the right fix.
My first guess was that MSR_LE wasn't being pr
On 8/11/21 11:20 PM, Song Gao wrote:
This is easily implemented inline, followed by a single helper call to re-load
the rounding mode (if required by the mask).
Hi, Richard,
Sorry to bother you， When I was revising this patch, I found that I didn't seem
to
understand your opinion. Could you
On Thu, 12 Aug 2021 at 19:29, Richard Henderson
wrote:
>
> PIng for review, or this slips to 6.2.
>
> On 8/10/21 1:25 PM, Richard Henderson wrote:
> > We need to be able to represent VEX.W on a 32-bit host, where REX.W
> > will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ.
> >
> > R
From: Matheus Ferst
It seems that access to elements of ppc_avr_t should only depend on
msr_le when !CONFIG_USER_ONLY.
Signed-off-by: Matheus Ferst
---
To reproduce the problem, build the following program for ppc64le:
int main(void)
{
__uint128_t a = 0x1122334455667788llu;
a <<= 64;
This is a bug fix to be included in case we are going to have a
6.1.0-rc4. I don't think this bug alone should delay the release
of QEMU 6.1.0.
The following changes since commit 703e8cd6189cf699c8d5c094bc68b5f3afa6ad71:
Update version for v6.1.0-rc3 release (2021-08-10 19:08:09 +0100)
are av
From: Daniel P. Berrangé
The machine_set_smp() mistakenly checks 'errp' not '*errp',
and so thinks there is an error every single time it runs.
This causes it to jump to the end of the method, skipping
the max CPUs checks. The caller meanwhile sees no error
and so carries on execution. The result
On Thu, Aug 12, 2021 at 06:53:53PM +0100, Daniel P. Berrangé wrote:
> The machine_set_smp() mistakenly checks 'errp' not '*errp',
> and so thinks there is an error every single time it runs.
> This causes it to jump to the end of the method, skipping
> the max CPUs checks. The caller meanwhile sees
PIng for review, or this slips to 6.2.
On 8/10/21 1:25 PM, Richard Henderson wrote:
We need to be able to represent VEX.W on a 32-bit host, where REX.W
will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385
Signed-off-by: Ri
Currently pushes to user forks run the same set of build / test jobs as
pushes to the main repo. This results in creation of 120+ individual
jobs. While it is useful for subsystem maintainers, and even regular
contributors to be able to run the full set of jobs, it is wasteful to
run all of them al
This splits the CI docs into one file talking about job setup and usage
and another file describing provisioning of custom runners.
Signed-off-by: Daniel P. Berrangé
---
docs/devel/ci-jobs.rst| 40 ++
docs/devel/ci-runners.rst | 117
docs/devel/ci.rst
A while ago GitLab announced it would be ending the free unlimited CI
minutes for public projects. It hasn't happened yet, but it is certainly
still on the radar. It is possible for OSS projects to get a greater
allowance, but it is still unclear how this will work for contributors'
forks. Even wit
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> On 12/08/21 13:09, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > ShellCheck points out that tr '[a-z]' actually replaces the []'s
> > and only the a-z is needed.
> >
> > Remove the spurious [] - although in this use
The machine_set_smp() mistakenly checks 'errp' not '*errp',
and so thinks there is an error every single time it runs.
This causes it to jump to the end of the method, skipping
the max CPUs checks. The caller meanwhile sees no error
and so carries on execution. The result of all this is:
$ qemu-s
On 12/08/21 15:05, Dr. David Alan Gilbert wrote:
In configure line 4464:
if !(GIT="$git" "$source_path/scripts/git-submodule.sh" "$git_submodules_action"
"$git_submodules"); then
^-- SC1035: You are missing a required space after the !.
which hmm I've not quite got my head around yet; but
On 12/08/21 13:09, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
ShellCheck points out that tr '[a-z]' actually replaces the []'s
and only the a-z is needed.
Remove the spurious [] - although in this use it will make no
difference.
Fixes: bb55b712e8dc4d4eb515144d5c26798fe
On 12/08/21 13:10, Lara Lazier wrote:
~0UL has 64 bits on Linux and 32 bits on Windows.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/512";.
Reported-by: Volker Rümelin
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/misc_helper.c | 2 +-
target/i386/tcg/sysemu/svm_helper.c |
On Fri, 2021-08-06 at 13:09 +0200, Igor Mammedov wrote:
> On Thu, 5 Aug 2021 18:30:01 -0400
> Shashi Mallela wrote:
>
> > Included creation of ITS as part of virt platform GIC
> > initialization. This Emulated ITS model now co-exists with kvm
> > ITS and is enabled in absence of kvm irq kernel s
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 28 +++
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 79 ---
1 file changed, 75 insertions(+), 4 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index c1629df603..f
Updated expected IORT files applicable with latest GICv3
ITS changes.
Full diff of new file disassembly:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180629 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
* Disassembly of tests/data/acpi/virt/IORT
Added expected IORT files applicable with latest GICv3
ITS changes.Temporarily differences in these files are
okay.
Signed-off-by: Shashi Mallela
Acked-by: Igor Mammedov
---
tests/data/acpi/virt/IORT | 0
tests/data/acpi/virt/IORT.memhp | 0
tests/data/acpi/virt/IO
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands
Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part o
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_common.c |
Defined descriptors for ITS device table,collection table and ITS
command queue entities.Implemented register read/write functions,
extract ITS table parameters and command queue parameters,extended
gicv3 common to capture qemu address space(which host the ITS table
platform memories required for s
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Tested-by: Neil Arm
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Rev
This patchset implements qemu device model for enabling physical
LPI support and ITS functionality in GIC as per GICv3 specification.
Both flat table and 2 level tables are implemented.The ITS commands
for adding/deleting ITS table entries,trigerring LPI interrupts are
implemented.Translated LPI in
SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
interface that reports AMD SoC's Ttcl (normalized temperature),
and resembles a typical 8-pin remote temperature sensor's I2C interface
to BMC.
This patch implements a basic AMD SB-TSI sensor that is
compatible with the open-source da
On Thu, 12 Aug 2021 at 17:09, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 8/12/21 4:46 PM, Peter Maydell wrote:
> > In the riscv virt machine init function, We assemble a string
> > plic_hart_config which is a comma-separated list of N copies of the
> > VIRT_PLIC_HART_CONFIG string. The co
On 8/12/21 4:18 PM, Peter Maydell wrote:
> The gunzip() function reads various fields from a passed in source
> buffer in order to skip a header before passing the actual compressed
> data to the zlib inflate() function. It does check whether the
> passed in buffer is too small, but unfortunately
Hi Peter,
On 8/12/21 4:46 PM, Peter Maydell wrote:
> In the riscv virt machine init function, We assemble a string
> plic_hart_config which is a comma-separated list of N copies of the
> VIRT_PLIC_HART_CONFIG string. The code that does this has a
> misunderstanding of the strncat() length argumen
Signed-off-by: Kevin Wolf
---
tests/unit/test-qobject-input-visitor.c | 218 ++
tests/qapi-schema/alias-bad-type.err | 2 +
tests/qapi-schema/alias-bad-type.json | 3 +
tests/qapi-schema/alias-bad-type.out | 0
tests/qapi-schema/alias-missing-
Introduce alias definitions for object types (structs and unions). This
allows using the same QAPI type and visitor for many syntax variations
that exist in the external representation, like between QMP and the
command line. It also provides a new tool for evolving the schema while
maintaining back
This series introduces alias definitions for QAPI object types (structs
and unions).
This allows using the same QAPI type and visitor even when the syntax
has some variations between different external interfaces such as QMP
and the command line.
It also provides a new tool for evolving the schem
When looking for an object in a struct in the external representation,
check not only the currently visited struct, but also whether an alias
in the current StackObject matches and try to fetch the value from the
alias then. Providing two values for the same object through different
aliases is an e
This makes qobject-input-visitor remember the currently valid aliases in
each StackObject. It doesn't actually allow using the aliases yet.
Signed-off-by: Kevin Wolf
---
qapi/qobject-input-visitor.c | 147 +++
1 file changed, 147 insertions(+)
diff --git a/qapi/q
This adds functions to the Visitor interface that can be used to define
aliases and alias scopes.
Signed-off-by: Kevin Wolf
---
include/qapi/visitor-impl.h | 12
include/qapi/visitor.h | 59 ++---
qapi/qapi-visit-core.c | 22 ++
3 fi
Instead of counting how many elements from the top of the stack we need
to ignore until we find the thing we're interested in, we can just
directly pass the StackObject pointer because all callers already know
it.
We only need a different way now to tell if we want to know the name of
something co
On Thu, 12 Aug 2021, Philippe Mathieu-Daudé wrote:
> On 8/12/21 3:22 PM, Ani Sinha wrote:
> > On Thu, 12 Aug 2021, Ani Sinha wrote:
> >
> >> Currently various acpi hotplug modules like cpu hotplug, memory hotplug,
> >> pci
> >> hotplug, nvdimm hotplug are all pulled in when CONFIG_ACPI_X86 is t
Paolo Bonzini writes:
> Il gio 12 ago 2021, 11:40 Alex Bennée ha scritto:
>
>ERROR: glib-2.56 gmodule-noexport-2.0 is required to compile QEMU
>
> Should it be gmodule-no-export? Hopefully the different distros aren't
> packaging different .pc files.
>
> My bad. :( It's correct with the
On 8/11/21 3:25 AM, Joel Stanley wrote:
> On Tue, 10 Aug 2021 at 23:37, Corey Minyard wrote:
>>
>> On Mon, Aug 09, 2021 at 03:15:55PM +0200, Cédric Le Goater wrote:
>>> From: Joel Stanley
>>>
>>> This contains some hardcoded register values that were obtained from the
>>> hardware after reading t
The realpath() function can return NULL on error, so we need to check
for it to avoid crashing when we try to strstr() into it.
This can happen if we run out of memory, or if /sys/ is not mounted,
among other situations.
Fixes: Coverity 1459913, 1460474
Fixes: ce317be98db0 ("exec: fetch the alignm
In the alignment check added to qemu_ram_alloc_from_fd() in commit
ce317be98db0dfdfa, the condition includes a check that 'mr' is not
NULL. This check is unnecessary because we can assume that the
caller always passes us a valid MemoryRegion, and indeed later in the
function we assume mr is not NU
On Mon, 9 Aug 2021 at 10:46, Peter Maydell wrote:
>
> On Tue, 25 Aug 2020 at 20:03, Alistair Francis
> wrote:
> >
> > From: Anup Patel
> >
> > We extend RISC-V virt machine to allow creating a multi-socket
> > machine. Each RISC-V virt machine socket is a NUMA node having
> > a set of HARTs, a
In the riscv virt machine init function, We assemble a string
plic_hart_config which is a comma-separated list of N copies of the
VIRT_PLIC_HART_CONFIG string. The code that does this has a
misunderstanding of the strncat() length argument. If the source
string is too large strncat() will write a
On Thu, 12 Aug 2021 12:23:41 +0200
Gerd Hoffmann wrote:
> Related: https://bugzilla.redhat.com//show_bug.cgi?id=1985924
> Signed-off-by: Gerd Hoffmann
Reviewed-by: Igor Mammedov
> ---
> hw/isa/lpc_ich9.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/isa/lpc_ich9
The gunzip() function reads various fields from a passed in source
buffer in order to skip a header before passing the actual compressed
data to the zlib inflate() function. It does check whether the
passed in buffer is too small, but unfortunately it checks that only
after reading bytes from the
With the introduction of the batch hinting, meaningless batches can be
created with no IOTLB updates if the memory region was skipped by
vhost_vdpa_listener_skipped_section. This is the case of host notifiers
memory regions, device un/realize, and others. This causes the vdpa
device to receive dma
On Thu, Aug 12, 2021 at 02:05:36PM +0100, Dr. David Alan Gilbert wrote:
> Indeed it's not; there's LOTS of warnings; although most of them are
> probably irrelevant; there are also two others at the error level:
>
> In configure line 4406:
> if "$ld" -verbose 2>&1 | grep -q "^[[:space:]]*$
On 8/12/21 3:22 PM, Ani Sinha wrote:
> On Thu, 12 Aug 2021, Ani Sinha wrote:
>
>> Currently various acpi hotplug modules like cpu hotplug, memory hotplug, pci
>> hotplug, nvdimm hotplug are all pulled in when CONFIG_ACPI_X86 is turned on.
>> This brings in support for whole lot of subsystems that
On Thu, 12 Aug 2021, Ani Sinha wrote:
> Currently various acpi hotplug modules like cpu hotplug, memory hotplug, pci
> hotplug, nvdimm hotplug are all pulled in when CONFIG_ACPI_X86 is turned on.
> This brings in support for whole lot of subsystems that some targets like
> mips does not need. T
On 8/12/21 3:09 PM, Taylor Simpson wrote:
> Don't allocate the string until error conditions have been checked
>
> Fixes: a00cfed0e ("Hexagon (disas) disassembler")
> Eliminate Coverity CID 1460121 (Resource leak)
>
> Signed-off-by: Taylor Simpson
> ---
> disas/hexagon.c | 3 ++-
> 1 file chang
Hi all,
On 8/12/21 2:24 PM, Christian Schoenebeck wrote:
> On Donnerstag, 12. August 2021 10:42:10 CEST Gerd Hoffmann wrote:
>> Hi,
>>
On Tue, Aug 10, 2021 at 03:17:43PM +0300, cla...@hotmail.com wrote:
> Gerd Hoffmann writes:
>
> Hell Gerd.
>
>> New maintainer wanted.
On Thu, 12 Aug 2021 at 14:09, Taylor Simpson wrote:
>
> Don't allocate the string until error conditions have been checked
>
> Fixes: a00cfed0e ("Hexagon (disas) disassembler")
> Eliminate Coverity CID 1460121 (Resource leak)
>
> Signed-off-by: Taylor Simpson
> ---
> disas/hexagon.c | 3 ++-
> 1
Don't allocate the string until error conditions have been checked
Fixes: a00cfed0e ("Hexagon (disas) disassembler")
Eliminate Coverity CID 1460121 (Resource leak)
Signed-off-by: Taylor Simpson
---
disas/hexagon.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/disas/hexag
1 - 100 of 178 matches
Mail list logo
