[PATCH] target/xtensa: fix meson.build rule for xtensa cores

import_core.sh tries to change Makefile.objs when importing new xtensa core, but that file no longer exists. Rewrite meson.build rule to pick up all source files that match core-*.c pattern and drop commands that change Makefile.objs. Cc: qemu-sta...@nongnu.org # v5.2.0 Signed-off-by: Max Filippov

[Bug 1922391] Re: qemu-system-ppc assertion "!mr->container" failed

** Description changed: Hi, I'm trying to run the NetBSD/macppc 8.2 installer (which is 32-bit ppc) in qemu-system-ppc version 5.2.0, and I'm hitting this assertion failure quite a bit into the "unpacking sets" part of the installation procedure, unpacking from the install iso image.

Re: [PATCH v7 2/4] Add NVMM accelerator: x86 CPU support

On 4/2/21 1:25 PM, Reinoud Zandijk wrote: +i386_softmmu_ss.add(when: 'CONFIG_NVMM', if_true: + declare_dependency(link_args: ['-lnvmm']) +) You shouldn't be playing with link flags directly. In patch 1, you found the nvmm library, and assigned it to the variable 'nvmm'. You should just add

Re: [PATCH v3 00/11] target/arm mte fixes

Patchew URL: https://patchew.org/QEMU/20210402214217.422585-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210402214217.422585-1-richard.hender...@linaro.org Subject: [PATCH v3 00/11]

[PATCH v3 10/11] target/arm: Simplify sve mte checking

Now that mte_check1 and mte_checkN have been merged, we can merge sve_cont_ldst_mte_check1 and sve_cont_ldst_mte_checkN. Which means that we can eliminate the function pointer into sve_ldN_r and sve_stN_r, calling sve_cont_ldst_mte_check directly. Signed-off-by: Richard Henderson --- target/arm

[PATCH v3 11/11] target/arm: Remove log2_esize parameter to gen_mte_checkN

The log2_esize parameter is not used except trivially. Drop the parameter and the deferral to gen_mte_check1. This fixes a bug in that the parameters as documented in the header file were the reverse from those in the implementation. Which meant that translate-sve.c was passing the parameters in

[PATCH v3 09/11] target/arm: Rename mte_probe1 to mte_probe

For consistency with the mte_check1 + mte_checkN merge to mte_check, rename the probe function as well. Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/mte_helper.c | 6 +++--- target/arm/sve_helper.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) d

[PATCH v3 06/11] test/tcg/aarch64: Add mte-5

Buglink: https://bugs.launchpad.net/bugs/1921948 Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte-5.c | 44 +++ tests/tcg/aarch64/Makefile.target | 2 +- 2 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/mte-5.c

[PATCH v3 08/11] target/arm: Merge mte_check1, mte_checkN

The mte_check1 and mte_checkN functions are now identical. Drop mte_check1 and rename mte_checkN to mte_check. Signed-off-by: Richard Henderson --- target/arm/helper-a64.h| 3 +-- target/arm/internals.h | 5 + target/arm/mte_helper.c| 26 +++--- target/arm/s

[PATCH v3 02/11] target/arm: Check PAGE_WRITE_ORG for MTE writeability

We can remove PAGE_WRITE when (internally) marking a page read-only because it contains translated code. This can be triggered by tests/tcg/aarch64/bti-2, after having serviced SIGILL trampolines on the stack. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 2 +- 1 file changed,

[PATCH v3 03/11] target/arm: Fix unaligned mte checks for mte_checkN

We were incorrectly assuming that only the first byte of an MTE access is checked against the tags. But per the ARM, unaligned accesses are pre-decomposed into single-byte accesses. So by the time we reach the actual MTE check in the ARM pseudocode, all accesses are aligned. Therefore, the first

[PATCH v3 05/11] target/arm: Fix unaligned checks for mte_check1, mte_probe1

We were incorrectly assuming that only the first byte of an MTE access is checked against the tags. But per the ARM, unaligned accesses are pre-decomposed into single-byte accesses. So by the time we reach the actual MTE check in the ARM pseudocode, all accesses are aligned. We cannot tell a pri

[PATCH v3 07/11] target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1

After recent changes, mte_checkN does not use ESIZE, and mte_check1 never used TSIZE. We can combine the two into a single field: SIZEM1. Choose to pass size - 1 because size == 0 is never used, our immediate need in mte_probe_int is for the address of the last byte (ptr + size - 1), and since al

[PATCH v3 00/11] target/arm mte fixes

Changes for v3: * linux-user mprotect fix moved to start, just to get it out of the way while I reworked the others. * Patch 2, the fix for unaligned accesses, has been split into 9. Hopefully these are much easier to review than previously. Technically only patches 1-6,11 are req

[PATCH v3 04/11] target/arm: Split out mte_probe_int

Split out a helper function from mte_checkN to perform all of the checking and address manpulation. So far, just use this in mte_checkN itself. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 52 +++-- 1 file changed, 40 insertions(+), 12 delet

[PATCH v3 01/11] accel/tcg: Preserve PAGE_ANON when changing page permissions

Using mprotect() to change PROT_* does not change the MAP_ANON previously set with mmap(). Our linux-user version of MTE only works with MAP_ANON pages, so losing PAGE_ANON caused MTE to stop working. Reported-by: Stephen Long Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte.h

[Bug 1922391] Re: qemu-system-ppc assertion "!mr->container" failed

** Tags added: ppc ** Description changed: Hi, - I'm trying to run the NetBSD/macppc 8.2 installer (which is 32-bit ppc) in qemu-system-ppc - version 5.2.0, and I'm hitting this assertion failure quite a bit into the "unpacking sets" - part of the installation procedure, unpacking from th

[Bug 1922391] [NEW] qemu-system-ppc assertion "!mr->container" failed

Public bug reported: Hi, I'm trying to run the NetBSD/macppc 8.2 installer (which is 32-bit ppc) in qemu-system-ppc version 5.2.0, and I'm hitting this assertion failure quite a bit into the "unpacking sets" part of the installation procedure, unpacking from the install iso image. Qemu is run

[PATCH v7 0/4] Implements the NetBSD Virtual Machine Monitor accelerator

The NetBSD team has implemented its new hypervisor called NVMM. It has been included since NetBSD 9.0 and has been in use now for quite some time. NVMM adds user-mode capabilities to create and manage virtual machines, configure memory mappings for guest machines, and create and control execution o

[PATCH v7 1/4] Add NVMM accelerator: configure and build logic

Signed-off-by: Kamil Rytarowski Signed-off-by: Reinoud Zandijk --- accel/Kconfig | 3 +++ configure | 8 +++- meson.build | 14 ++ meson_options.txt | 2 ++ qemu-options.hx | 8 5 files changed, 30 insertions(+), 5 deletions(-) diff --git a/acce

[PATCH v7 2/4] Add NVMM accelerator: x86 CPU support

Signed-off-by: Kamil Rytarowski Signed-off-by: Reinoud Zandijk --- target/i386/meson.build |1 + target/i386/nvmm/meson.build | 10 + target/i386/nvmm/nvmm-accel-ops.c | 111 +++ target/i386/nvmm/nvmm-accel-ops.h | 24 + target/i386/nvmm/nvmm-all.c | 1226 +

[PATCH v7 3/4] Add NVMM accelerator: acceleration enlightenments

Signed-off-by: Kamil Rytarowski Signed-off-by: Reinoud Zandijk --- include/sysemu/hw_accel.h | 1 + include/sysemu/nvmm.h | 26 ++ target/i386/helper.c | 2 +- 3 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 include/sysemu/nvmm.h diff --g

[PATCH v7 4/4] Add NVMM Accelerator: add maintainers for NetBSD/NVMM

Signed-off-by: Kamil Rytarowski Signed-off-by: Reinoud Zandijk --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 554be84b32..cf9d81ea7c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -510,6 +510,15 @@ F: accel/stubs/hax-stub.c F: in

[PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 10 -- target/riscv/csr.c | 12 ++-- target/riscv/translate.c | 19 +-- 3 files changed, 27 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8ca

Re: [PATCH v3 0/4] Add support for Shakti SoC from IIT-M

On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K wrote: > > Changes in v3: > - Drop SHAKTI_C_DEBUG register > > Changes in v2: > - Moved CPU addition to a separate patch(P1) > - Use riscv_setup_rom_resetvec API to setup reset vector > - Dropped unused DPRINTF and unwanted break statements > - Fix

[PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 11 --- target/riscv/cpu_helper.c | 21 - 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 969dd05eae..8caab23b62 100644 --- a/target

[PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6a816ce9c2..9f6fbe3dc5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -416,12 +416,6 @@ #define HSTA

[PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 6 -- target/riscv/csr.c | 9 - 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf4599207..969dd05eae 100644 --- a/target/riscv/cpu_bits.h +++ b/t

[PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro

Signed-off-by: Alistair Francis --- target/riscv/translate.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9c6d998efa..4af55deaea 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,12 +67,6 @@ typedef st

[PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build

Signed-off-by: Alistair Francis --- target/riscv/insn16-32.decode | 24 target/riscv/insn16-64.decode | 31 +++ target/riscv/translate.c | 18 +- target/riscv/meson.build | 7 +-- 4 files changed, 77 insertions(+)

[PATCH v1 0/8] RISC-V: Steps towards running 32-bit guests on

This is another step towards running 32-bit CPU code on the 64-bit softmmu builds for RISC-V. I have tested this and am able to run some 32-bit code, but eventually hit some issue. This series doesn't allow users to use 32-bit CPUs with 64-bit softmmu builds as it doesn't work yet. This series in

[PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 11 --- target/riscv/cpu_helper.c | 30 +++--- target/riscv/csr.c| 33 - target/riscv/monitor.c| 22 +- 4 files changed, 64 insertions(+)

[PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro

Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 6 -- target/riscv/cpu.c | 6 +- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba..ef838f5fbf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -53,12

Re: [PATCH v2 01/21] Hexagon (target/hexagon) TCG generation cleanup

On 4/2/21 12:42 PM, Taylor Simpson wrote: @@ -43,12 +42,17 @@ static inline void gen_log_predicated_reg_write(int ... Having looked forward at patch 5, it appears this could be further improved by examining ctx->regs_written. It's not obvious how. This is for a predicated instruction (e.g.,

RE: [PATCH v2 01/21] Hexagon (target/hexagon) TCG generation cleanup

> -Original Message- > From: Richard Henderson > Sent: Friday, April 2, 2021 12:47 PM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: phi...@redhat.com; a...@rev.ng; Brian Cain > Subject: Re: [PATCH v2 01/21] Hexagon (target/hexagon) TCG generation > cleanup > > On 3/31/21 8:53 PM, Ta

Re: [PATCH v2] qapi: introduce 'query-cpu-model-cpuid' action

On Wed, Mar 31, 2021 at 11:19:35AM +0200, Igor Mammedov wrote: > On Tue, 30 Mar 2021 12:37:11 +0300 > Valeriy Vdovin wrote: > > > On Tue, Mar 30, 2021 at 02:15:10AM +0200, Igor Mammedov wrote: > > > On Thu, 25 Mar 2021 19:57:05 +0300 > > > Valeriy Vdovin wrote: > > > > > > > Introducing new q

Re: [PATCH] qemu_fw_cfg: Make fw_cfg_rev_attr a proper kobj_attribute

On Fri, Apr 2, 2021 at 8:31 PM Nathan Chancellor wrote: > > On Fri, Apr 02, 2021 at 11:25:42AM -0700, Kees Cook wrote: > > On Fri, Apr 02, 2021 at 08:42:07AM +0200, Sedat Dilek wrote: > > > On Thu, Feb 25, 2021 at 10:25 PM Kees Cook wrote: > > > > > > > > On Thu, 11 Feb 2021 12:42:58 -0700, Natha

Re: [PATCH 2/2] target/arm: Fix unaligned mte checks

On 4/2/21 11:35 AM, Peter Maydell wrote: On Fri, 2 Apr 2021 at 06:42, Richard Henderson wrote: We were incorrectly assuming that only the first byte of an MTE access is checked against the tags. But per the ARM, unaligned accesses are pre-decomposed into single-byte accesses. So by the time

Re: [PATCH v2 07/11] tests/tcg: relax the next step precision of the gdb sha1 test

On 4/2/21 9:41 AM, Richard Henderson wrote: On 4/1/21 3:25 AM, Alex Bennée wrote:   check_break("SHA1Init") -    # check step and inspect values +    # Check step and inspect values. We do a double next after the +    # breakpoint as depending on the version of gdb we may step the +    # pre

Re: [PATCH 2/2] target/arm: Fix unaligned mte checks

On Fri, 2 Apr 2021 at 06:42, Richard Henderson wrote: > > We were incorrectly assuming that only the first byte of an MTE access > is checked against the tags. But per the ARM, unaligned accesses are > pre-decomposed into single-byte accesses. So by the time we reach the > actual MTE check in th

Re: [PATCH] qemu_fw_cfg: Make fw_cfg_rev_attr a proper kobj_attribute

On Fri, Apr 02, 2021 at 11:25:42AM -0700, Kees Cook wrote: > On Fri, Apr 02, 2021 at 08:42:07AM +0200, Sedat Dilek wrote: > > On Thu, Feb 25, 2021 at 10:25 PM Kees Cook wrote: > > > > > > On Thu, 11 Feb 2021 12:42:58 -0700, Nathan Chancellor wrote: > > > > fw_cfg_showrev() is called by an indirect

Re: [PATCH] qemu_fw_cfg: Make fw_cfg_rev_attr a proper kobj_attribute

On Fri, Apr 02, 2021 at 08:42:07AM +0200, Sedat Dilek wrote: > On Thu, Feb 25, 2021 at 10:25 PM Kees Cook wrote: > > > > On Thu, 11 Feb 2021 12:42:58 -0700, Nathan Chancellor wrote: > > > fw_cfg_showrev() is called by an indirect call in kobj_attr_show(), > > > which violates clang's CFI checking

Re: [PATCH v2 09/21] Hexagon (target/hexagon) use softfloat default NaN and tininess

On 3/31/21 8:53 PM, Taylor Simpson wrote: Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson --- fpu/softfloat-specialize.c.inc | 3 +++ target/hexagon/cpu.c | 5 + target/hexagon/op_helper.c | 47 -- 3 files changed, 8 i

Re: [PATCH v2 01/21] Hexagon (target/hexagon) TCG generation cleanup

On 3/31/21 8:53 PM, Taylor Simpson wrote: Simplify TCG generation of hex_reg_written Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson --- target/hexagon/genptr.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/hexagon/genptr.c b/target/

Re: [PATCH v2 05/21] Hexagon (target/hexagon) decide if pred has been written at TCG gen time

On 3/31/21 8:53 PM, Taylor Simpson wrote: Multiple writes to the same preg are and'ed together. Rather than generating a runtime check, we can determine at TCG generation time if the predicate has previously been written in the packet. Test added to tests/tcg/hexagon/misc.c Suggested-by: Richa

Re: [PATCH v3] hw/smbios: support for type 41 (onboard devices extended information)

❦ 1 avril 2021 23:07 +02, Vincent Bernat: >>> This can be invoked with: >>> >>> $QEMU -netdev user,id=internet >>> -device >>> virtio-net-pci,mac=50:54:00:00:00:42,netdev=internet,id=internet-dev \ >>> -smbios type=41,designation='Onboard >>> LAN',instance=1,kind=ether

Re: [PATCH v2 04/21] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN

On 3/31/21 8:53 PM, Taylor Simpson wrote: @@ -601,19 +612,12 @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_exec_counters(ctx); tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); if (ctx->base.singlestep_enabled) { -

Re: [PATCH v2 03/21] Hexagon (target/hexagon) use env_archcpu and env_cpu

On 3/31/21 8:53 PM, Taylor Simpson wrote: Remove hexagon_env_get_cpu and replace with env_archcpu Replace CPU(hexagon_env_get_cpu(env)) with env_cpu(env) Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson --- linux-user/hexagon/cpu_loop.c | 2 +- target/hexagon/cpu.c | 4 +

Re: [PATCH v2 02/21] Hexagon (target/hexagon) remove unnecessary inline directives

On 3/31/21 8:53 PM, Taylor Simpson wrote: Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson --- target/hexagon/cpu.c | 9 - target/hexagon/decode.c| 6 +++--- target/hexagon/fma_emu.c | 39 --- target/hexagon/op_helper.c |

Re: [PATCH v2 01/21] Hexagon (target/hexagon) TCG generation cleanup

On 3/31/21 8:53 PM, Taylor Simpson wrote: Simplify TCG generation of hex_reg_written Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson --- target/hexagon/genptr.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v2 5/5] target/riscv: Use RISCVException enum for CSR access

On 4/1/21 8:18 AM, Alistair Francis wrote: Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 11 +++ target/riscv/csr.c | 37 ++--- target/riscv/gdbstub.c | 8 target/riscv/op_helper.c | 18 +- 4 files ch

Re: [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations

On 4/1/21 8:17 AM, Alistair Francis wrote: Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 14 +- target/riscv/csr.c | 643 +++-- 2 files changed, 390 insertions(+), 267 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions

On 4/1/21 8:17 AM, Alistair Francis wrote: Signed-off-by: Alistair Francis --- target/riscv/csr.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v2 2/5] target/riscv: Use the RISCVException enum for CSR predicates

On 4/1/21 8:17 AM, Alistair Francis wrote: Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +- target/riscv/csr.c | 80 +- 2 files changed, 46 insertions(+), 37 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v2 1/5] target/riscv: Convert the RISC-V exceptions to an enum

On 4/1/21 8:17 AM, Alistair Francis wrote: Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 44 --- target/riscv/cpu.c| 2 +- target/riscv/cpu_helper.c | 4 ++-- 3 files changed, 26 insertions(+), 24 deletions

Re: [PATCH v2 07/11] tests/tcg: relax the next step precision of the gdb sha1 test

On 4/1/21 3:25 AM, Alex Bennée wrote: check_break("SHA1Init") -# check step and inspect values +# Check step and inspect values. We do a double next after the +# breakpoint as depending on the version of gdb we may step the +# preamble and not the first actual line of so

[Bug 1921948] Re: MTE tags not checked properly for unaligned accesses at EL1

Yeah, I saw an error right after posting. Please try v2: https://patchew.org/QEMU/20210402161835.286665-1-richard.hender...@linaro.org/ -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1921948 Title:

Re: [PATCH v2 0/3] target/arm mte fixes

Patchew URL: https://patchew.org/QEMU/20210402161835.286665-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210402161835.286665-1-richard.hender...@linaro.org Subject: [PATCH v2 0/3] ta

Re: [PATCH v2 04/11] tests/tcg/configure.sh: make sure we pick up x86_64 cross compilers

On 4/1/21 3:25 AM, Alex Bennée wrote: While it's hard to find cross compilers packaged for arches other than x86_64 the same cannot be said for the x86_64 compiler which is available on Debians i386, arm64 and ppc64el release architectures. Signed-off-by: Alex Bennée --- tests/tcg/configure.sh

Re: [PATCH v2 06/11] tests/tcg/i386: force -fno-pie for test-i386

On 4/1/21 3:25 AM, Alex Bennée wrote: +-Werror -fno-pie -no-pie -o $TMPE $TMPC; then What is -no-pie? That isn't a compiler option, afaik. r~

[Bug 1921948] Re: MTE tags not checked properly for unaligned accesses at EL1

Hi Richard, I tried your patch, but QEMU crashes with: ERROR:../target/arm/mte_helper.c:588:mte_check_fail: code should not be reached Bail out! ERROR:../target/arm/mte_helper.c:588:mte_check_fail: code should not be reached when running KASAN tests. Thanks! -- You received this bug notifica

Re: [PATCH v2 03/11] tests/tcg: add concept of container_hosts

On 4/1/21 3:25 AM, Alex Bennée wrote: While docker is nominally multarch these days it doesn't mean our distros actually package all cross compilers for all architectures. The upcoming Debian bullseye release will improve things further. At least for now we can get things like the 32 bit ARM comp

[PATCH] tests/qtest: add one more test for the am53c974

Original crash: qemu-fuzz-i386: ../hw/scsi/esp.c:791: void esp_transfer_data(SCSIRequest *, uint32_t): Assertion `!s->do_cmd' failed. ==257532== ERROR: libFuzzer: deadly signal __assert_fail assert/assert.c:101:3 esp_transfer_data hw/scsi/esp.c:791:5 scsi_req_data hw/scsi/scsi-bus.c:1412:9 scsi_di

[PATCH v2 3/3] accel/tcg: Preserve PAGE_ANON when changing page permissions

Using mprotect() to change PROT_* does not change the MAP_ANON previously set with mmap(). Our linux-user version of MTE only works with MAP_ANON pages, so losing PAGE_ANON caused MTE to stop working. Reported-by: Stephen Long Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte.h

[PATCH v2 1/3] target/arm: Check PAGE_WRITE_ORG for MTE writeability

We can remove PAGE_WRITE when (internally) marking a page read-only because it contains translated code. This can be triggered by tests/tcg/aarch64/bti-2, after having serviced SIGILL trampolines on the stack. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 2 +- 1 file changed,

[PATCH v2 2/3] target/arm: Fix unaligned mte checks

We were incorrectly assuming that only the first byte of an MTE access is checked against the tags. But per the ARM, unaligned accesses are pre-decomposed into single-byte accesses. So by the time we reach the actual MTE check in the ARM pseudocode, all accesses are aligned. Therefore, drop mte_

[PATCH v2 0/3] target/arm mte fixes

In addition to re-instating the "is tag checking enabled" test in gen_mte_checkN, add a fix for a second bug in mprotect. I have verified that the 5.10 kernel, running in system mode, allows setting PROT_MTE with mprotect. r~ Supercedes: 20210402053728.265173-1-richard.hender...@linaro.org ("t

Re: [PATCH v3 3/4] hw/char: Add Shakti UART emulation

On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K wrote: > > This is the initial implementation of Shakti UART. > > Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis Alistair > --- > MAINTAINERS | 2 + > hw/char/meson.build | 1 + > hw/char/shakti_uart.c

[v5 3/3] block/io: Merge discard request alignments

Signed-off-by: Akihiko Odaki --- block/io.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/block/io.c b/block/io.c index ca2dca30070..aad74bd6714 100644 --- a/block/io.c +++ b/block/io.c @@ -124,6 +124,8 @@ void bdrv_parent_drained_begin_single(BdrvChild *c, bool poll) static void bdrv

[v5 2/3] block: Add backend_defaults property

backend_defaults property allow users to control if default block properties should be decided with backend information. If it is off, any backend information will be discarded, which is suitable if you plan to perform live migration to a different disk backend. If it is on, a block device may ut

[v5 1/3] block/file-posix: Optimize for macOS

This commit introduces "punch hole" operation and optimizes transfer block size for macOS. Thanks to Konstantin Nazarov for detailed analysis of a flaw in an old version of this change: https://gist.github.com/akihikodaki/87df4149e7ca87f18dc56807ec5a1bc5#gistcomment-3654667 Signed-off-by: Akihiko

[v4 3/3] block/io: Merge discard request alignments

Signed-off-by: Akihiko Odaki --- block/io.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/block/io.c b/block/io.c index ca2dca30070..aad74bd6714 100644 --- a/block/io.c +++ b/block/io.c @@ -124,6 +124,8 @@ void bdrv_parent_drained_begin_single(BdrvChild *c, bool poll) static void bdrv

[v4 2/3] block: Add backend_defaults property

backend_defaults property allow users to control if default block properties should be decided with backend information. If it is off, any backend information will be discarded, which is suitable if you plan to perform live migration to a different disk backend. If it is on, a block device may ut

[v4 1/3] block/file-posix: Optimize for macOS

This commit introduces "punch hole" operation and optimizes transfer block size for macOS. Thanks to Konstantin Nazarov for detailed analysis of a flaw in an old version of this change: https://gist.github.com/akihikodaki/87df4149e7ca87f18dc56807ec5a1bc5#gistcomment-3654667 Signed-off-by: Akihiko

[Bug 1921948] Re: MTE tags not checked properly for unaligned accesses at EL1

https://patchew.org/QEMU/20210402053728.265173-1-richard.hender...@linaro.org/ -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1921948 Title: MTE tags not checked properly for unaligned accesses at E

Re: [PATCH 2/2] target/arm: Fix unaligned mte checks

On 4/1/21 10:37 PM, Richard Henderson wrote: TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, -bool tag_checked, int log2_esize, int total_size) +bool tag_checked, int total_size) { -if (tag_checked && s->mte_active[0]

Re: [PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform

On Fri, 02 Apr 2021 18:35:04 +0530 Alistair Francis wrote > On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K wrote: > > > > Connect one shakti uart to the shakti_c machine. > > > > Signed-off-by: Vijai Kumar K > > In future can you please keep the Reviewed by tags when

Re: [PATCH v3] ppc/spapr: Add support for implement support for H_SCM_HEALTH

On Fri, 2 Apr 2021 15:51:28 +0530 Vaibhav Jain wrote: > Add support for H_SCM_HEALTH hcall described at [1] for spapr > nvdimms. This enables guest to detect the 'unarmed' status of a > specific spapr nvdimm identified by its DRC and if its unarmed, mark > the region backed by the nvdimm as read

Re: [PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform

On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K wrote: > > Connect one shakti uart to the shakti_c machine. > > Signed-off-by: Vijai Kumar K In future can you please keep the Reviewed by tags when sending a new version of the patch series? Reviewed-by: Alistair Francis Alistair > --- > hw/risc

Re: [PATCH v3 1/4] target/riscv: Add Shakti C class CPU

On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K wrote: > > C-Class is a member of the SHAKTI family of processors from IIT-M. > > It is an extremely configurable and commercial-grade 5-stage in-order > core supporting the standard RV64GCSUN ISA extensions. > > Signed-off-by: Vijai Kumar K Reviewed-

Re: [PATCH v3 2/4] riscv: Add initial support for Shakti C machine

On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K wrote: > > Add support for emulating Shakti reference platform based on C-class > running on arty-100T board. > > https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst > > Signed-off-by: Vijai Kumar K Reviewed-by: Alistair Francis

[PATCH v1 8/8] target/riscv: Add ePMP support for the Ibex CPU

The physical Ibex CPU has ePMP support and it's enabled for the OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU. Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d66568

[PATCH v1 5/8] target/riscv: Implementation of enhanced PMP (ePMP)

From: Hou Weiying This commit adds support for ePMP v0.9.1. The ePMP spec can be found in: https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8 Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Message-Id: [ Changes by AF: - Re

[PATCH v1 4/8] target/riscv: Add ePMP CSR access functions

From: Hou Weiying Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Message-Id: [ Changes by AF: - Rebase on master - Fix build errors - Fix some style issues ] Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 1 + target/riscv/pmp.h

[PATCH v1 6/8] target/riscv: Add a config option for ePMP

From: Hou Weiying Add a config option to enable experimental support for ePMP. This is disabled by default and can be enabled with 'x-epmp=true'. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Message-Id: Signed-off-by: Alistair Francis --- target/ris

[PATCH v1 3/8] target/riscv: Add the ePMP feature

Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba..8dcb4a4bb2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -80,6 +80,7 @@ enum { RISCV_FEATURE_MMU, RISCV_FEA

[PATCH v1 7/8] target/riscv/pmp: Remove outdated comment

Signed-off-by: Alistair Francis --- target/riscv/pmp.c | 4 1 file changed, 4 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 3794c808e8..07e4c407ab 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -19,10 +19,6 @@ * this program. If not, see

[PATCH v1 1/8] target/riscv: Fix the PMP is locked check when using TOR

The RISC-V spec says: if PMP entry i is locked and pmpicfg.A is set to TOR, writes to pmpaddri-1 are ignored. The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which is incorrect. Update the pmp_is_locked() function to not check the suppording fields and instaed enforce t

[PATCH v1 2/8] target/riscv: Define ePMP mseccfg

From: Hou Weiying Use address 0x390 and 0x391 for the ePMP CSRs. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Reviewed-by: Alistair Francis Message-Id: [ Changes by AF: - Tidy up commit message ] Signed-off-by: Alistair Francis --- target/riscv/c

[PATCH v1 0/8] RISC-V: Add support for ePMP v0.9.1

This series adds support for ePMP v0.9.1 to the QEMU RISC-V target. This is based on previous patches, but has been rebased on the latest master and updated for the latest spec. The spec is avaliable at: https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8 This was te

[PATCH v1 0/2] Add the SiFive PWM device

This series adds a the SiFive PWM device and connects it to the sifive_u machine. This has been tested as a timer with seL4. Alistair Francis (2): sifive_u_pwm: Initial commit sifive_u: Connect the SiFive PWM device include/hw/dma/sifive_pdma.h| 2 +- include/hw/riscv/sifive_u.h |

[PATCH v1 2/2] sifive_u: Connect the SiFive PWM device

Signed-off-by: Alistair Francis --- include/hw/riscv/sifive_u.h | 14 +- hw/riscv/sifive_u.c | 23 ++- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 2656b39808..6e0779562d 100

[PATCH v1 1/2] sifive_u_pwm: Initial commit

Signed-off-by: Justin Restivo Signed-off-by: Alexandra Clifford Signed-off-by: Amanda Strnad Signed-off-by: Alistair Francis --- include/hw/dma/sifive_pdma.h| 2 +- include/hw/timer/sifive_u_pwm.h | 62 hw/timer/sifive_u_pwm.c | 483 MAINTAI

[PATCH v1 1/1] hw/riscv: Enalbe VIRTIO_VGA for RISC-V virt machine

imply VIRTIO_VGA for the virt machine, this fixes the following error when specifying `-vga virtio` as a command line argument: qemu-system-riscv64: Virtio VGA not available Signed-off-by: Alistair Francis --- hw/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/riscv/Kconfig

Re: [PULL 00/13] Updates to MAINTAINERS, docs, and some small fixes

On Thu, 1 Apr 2021 at 14:12, Thomas Huth wrote: > > Hi Peter, > > the following changes since commit 6ee55e1d10c25c2f6bf5ce2084ad2327e17affa5: > > Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-20210331' > into staging (2021-03-31 13:14:18 +0100) > > are available in the Git

Re: Bug: fstenv is wrongly implemented

On Fri, 2 Apr 2021 at 09:47, Paolo Bonzini wrote: > > On 02/04/21 10:29, Ziqiao Kong wrote: > > > > According to git blame, this bug is introduced about 13 years ago: > > https://github.com/qemu/qemu/blame/633decd71119a4293e5e53e6059026c517a8bef0/target-i386/fpu_helper.c#L997. > > > > We also had

[PATCH v3] ppc/spapr: Add support for implement support for H_SCM_HEALTH

Add support for H_SCM_HEALTH hcall described at [1] for spapr nvdimms. This enables guest to detect the 'unarmed' status of a specific spapr nvdimm identified by its DRC and if its unarmed, mark the region backed by the nvdimm as read-only. The patch adds h_scm_health() to handle the H_SCM_HEALTH

Re: [PATCH v2] ppc/spapr: Add support for implement support for H_SCM_HEALTH

Hi Greg, Thanks for looking into this patch. Greg Kurz writes: > On Thu, 1 Apr 2021 13:26:11 +1100 > David Gibson wrote: > >> On Thu, Apr 01, 2021 at 06:35:19AM +0530, Vaibhav Jain wrote: >> > Add support for H_SCM_HEALTH hcall described at [1] for spapr >> > nvdimms. This enables guest to det

Re: [PATCH v2] ppc/spapr: Add support for implement support for H_SCM_HEALTH

Hi David, Thanks for looking into this patch David Gibson writes: > On Thu, Apr 01, 2021 at 06:35:19AM +0530, Vaibhav Jain wrote: >> Add support for H_SCM_HEALTH hcall described at [1] for spapr >> nvdimms. This enables guest to detect the 'unarmed' status of a >> specific spapr nvdimm identi

[PATCH] hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs

In emulation of the CFGI_STE_RANGE command, we now take StreamID as the start of the invalidation range, regardless of whatever the Range is, whilst the spec clearly states that - "Invalidation is performed for an *aligned* range of 2^(Range+1) StreamIDs." - "The bottom Range+1 bits of the

  1   2   >