Starting from pss->page, ram_save_host_page() will check every page
and send the dirty pages up to the end of the current host page or
the boundary of used_length of the block. If the host page size is
a huge page, the step "check" will take a lot of time.
This will improve performance to use migr
When the host page is a huge page and something is sent in the
current iteration, the migration_rate_limit() should be executed.
If not, this function can be omitted to save time.
Rename tmppages to pages_this_iteration to express its meaning
more clearly.
Signed-off-by: Keqian Zhu
Signed-off-by
The ram_save_host_page() has been modified several times
since its birth. But the comment hasn't been modified as it should
be. It'd better to modify the comment to explain ram_save_host_page()
more clearly.
Signed-off-by: Kunkun Jiang
---
migration/ram.c | 16 +++-
1 file changed, 7
Hi,
This series include patches as below:
Patch 1:
- modified the comment ram_save_host_page() to make them match each other
Patch 2:
- reduce unnecessary rate limitting in ram_save_host_page()
Patch 3:
- optimized ram_save_host_page() by using migration_bitmap_find_dirty() to find
dirty pages
On 04/03/2021 22:58, Philippe Mathieu-Daudé wrote:
On 3/4/21 11:10 PM, Mark Cave-Ayland wrote:
This patch series comes from an experimental branch that I've been working on
to try and boot a MacOS toolbox ROM under the QEMU q800 machine. The effort is
...
v3:
- Rebase onto master (fix up mino
On 04/03/2021 14:02, Markus Armbruster wrote:
Several QOM type names contain ',':
ARM,bitband-memory
etraxfs,pic
etraxfs,serial
etraxfs,timer
fsl,imx25
fsl,imx31
fsl,imx6
fsl,imx6ul
fsl,imx7
grlib,ahbpnp
grlib,apbpnp
grlib,apbuart
On 2021/3/5 2:39 下午, P J P wrote:
Hello all,
Just to note:
* Let's use list to review non-public/embargoed patch(es) only.
* If patch(es) is being reviewed publicly on list,
CC'ing list does not help much.
Thank you.
---
-P J P
http://feedmug.com
I see.
Thanks
Peter Krempa writes:
> On Thu, Mar 04, 2021 at 17:23:05 +0100, Markus Armbruster wrote:
>> Daniel P. Berrangé writes:
>>
>> > On Thu, Mar 04, 2021 at 03:26:55PM +0100, Markus Armbruster wrote:
>> >> Daniel P. Berrangé writes:
>> >>
>> >> > On Thu, Mar 04, 2021 at 11:00:57AM +0100, Markus Armb
Hello all,
Just to note:
* Let's use list to review non-public/embargoed patch(es) only.
* If patch(es) is being reviewed publicly on list,
CC'ing list does not help much.
Thank you.
---
-P J P
http://feedmug.com
From: Alexander Bulekov
This patch switches to use qemu_receive_packet() which can detect
reentrancy and return early.
This is intended to address CVE-2021-3416.
Cc: Prasad J Pandit
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alexander Bulekov
Signed-off-by: Jason Wang
---
hw/net/ca
From: Alexander Bulekov
This patch switches to use qemu_receive_packet() which can detect
reentrancy and return early.
This is intended to address CVE-2021-3416.
Cc: Prasad J Pandit
Buglink: https://bugs.launchpad.net/qemu/+bug/1910826
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason
From: Alexander Bulekov
This patch switches to use qemu_receive_packet() which can detect
reentrancy and return early.
This is intended to address CVE-2021-3416.
Cc: Prasad J Pandit
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/lan9118.c | 2 +-
1 file changed, 1
From: Alexander Bulekov
This patch switches to use qemu_receive_packet() which can detect
reentrancy and return early.
This is intended to address CVE-2021-3416.
Cc: Prasad J Pandit
Buglink: https://bugs.launchpad.net/qemu/+bug/1917085
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason
This patch switches to use qemu_receive_receive_iov() which can detect
reentrancy and return early.
This is intended to address CVE-2021-3416.
Cc: Prasad J Pandit
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/net_tx_pkt.c | 2 +-
1 file changed, 1 insertion(+), 1 de
This patch switches to use qemu_receive_packet() which can detect
reentrancy and return early.
This is intended to address CVE-2021-3416.
Cc: Prasad J Pandit
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/dp8393x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/dp83
Some NIC supports loopback mode and this is done by calling
nc->info->receive() directly which in fact suppresses the effort of
reentrancy check that is done in qemu_net_queue_send().
Unfortunately we can't use qemu_net_queue_send() here since for
loopback there's no sender as peer, so this patch
This patch switches to use qemu_receive_packet() which can detect
reentrancy and return early.
This is intended to address CVE-2021-3416.
Cc: Prasad J Pandit
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/sungem.c | 2 +-
1 file changed
This patch switches to use qemu_receive_packet() which can detect
reentrancy and return early.
This is intended to address CVE-2021-3416.
Cc: Prasad J Pandit
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/msf2-emac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
This patch switches to use qemu_receive_packet() which can detect
reentrancy and return early.
This is intended to address CVE-2021-3416.
Cc: Prasad J Pandit
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/e1000.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Hi All:
Followed by commit 22dc8663d9 ("net: forbid the reentrant RX"), we
still need to fix the issues casued by loopback mode where the NIC
usually it via calling nc->info->receive() directly.
The fix is to introduce new network helper and check the
queue->delivering.
This series addresses CVE
ping
On 2021/2/12 23:02, LIU Zhiwei wrote:
This patchset implements the packed extension for RISC-V on QEMU.
This patchset have passed all my direct Linux user mode cases(RV64) and
bare metal cases(RV32) on X86-64 Ubuntu host machine. I will later push
these test cases to my repo(https://github
On 3/1/2021 5:48 PM, Andrew Jones wrote:
On Fri, Feb 26, 2021 at 04:41:45PM +0800, Ying Fang wrote:
On 2/25/2021 8:02 PM, Andrew Jones wrote:
On Thu, Feb 25, 2021 at 04:56:22PM +0800, Ying Fang wrote:
An accurate cpu topology may help improve the cpu scheduler's decision
making when deali
{IP,IPV6}_MULTICAST_IF was not supported.
Signed-off-by: Jiaxun Yang
---
linux-user/syscall.c | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 389ec09764..77343130b3 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -2219,6 +
在 2021/3/5 上午11:35, Jiaxun Yang 写道:
> {IP,IPV6}_MULTICAST_IF was not supported.
>
> Reported-by: Yunqiang Su
> Signed-off-by: Jiaxun Yang
> ---
> linux-user/syscall.c | 4 +
> linux-user/syscall.c.orig | 13305
^ Sorry ^ ^ sorry for the nois
Patchew URL:
https://patchew.org/QEMU/20210305033510.8600-1-jiaxun.y...@flygoat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210305033510.8600-1-jiaxun.y...@flygoat.com
Subject: [PATCH] linux-user: add missing
On Tue, Mar 02, 2021 at 11:10:18AM -0300, Daniel Henrique Barboza wrote:
> We are asserting the existence of the first DRC LMB after sending unplug
> requests to all LMBs of the DIMM, where every DRC is being asserted
> inside the loop. This means that the first DRC is being asserted twice.
>
> Re
On Tue, Mar 02, 2021 at 11:10:19AM -0300, Daniel Henrique Barboza wrote:
> Recent changes allowed the pSeries machine to rollback the hotunplug
> process for the DIMM when the guest kernel signals, via a
> reconfiguration of the DR connector, that it's not going to release the
> LMBs.
>
> Let's al
Hi John,
Thanks for your comment.
On 2021/3/5 7:53, John Snow wrote:
On 2/28/21 9:39 PM, Like Xu wrote:
Hi Genius,
I am a user of QEMU v4.2.0 and stuck in an interesting bug, which may
still exist in the mainline.
Thanks in advance to heroes who can take a look and share understanding.
D
On Fri, Feb 19, 2021 at 1:56 AM Philippe Mathieu-Daudé wrote:
>
> The SDHC_SYSAD and SDHC_BLKSIZE can not be accessed while a
> transaction is in progress, see 'SD Host Controller Simplified
> Specification'
>
> 1.5) SD Command Generation
>
> The Host Driver should not read the SDMA System Add
On 3/4/21 5:17 AM, Vladimir Sementsov-Ogievskiy wrote:
Allow benchmark with different kinds of target cache.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/simplebench/bench-backup.py| 33 --
scripts/simplebench/bench_block_job.py | 10 +---
2 files
On 3/4/21 5:17 AM, Vladimir Sementsov-Ogievskiy wrote:
We should not report success if there is an error in final event.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/simplebench/bench_block_job.py | 4
1 file changed, 4 insertions(+)
diff --git a/scripts/simplebench/bench_bl
On 3/4/21 5:17 AM, Vladimir Sementsov-Ogievskiy wrote:
Add support for qcow2 source. New option says to use test-source.qcow2
instead of test-source. Of course, test-source.qcow2 should be
precreated.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/simplebench/bench-backup.py| 5 +
On 3/4/21 5:17 AM, Vladimir Sementsov-Ogievskiy wrote:
Add arguments to set number of test runs per table cell and to disable
initial run that is not counted in results.
It's convenient to set --count 1 --no-initial-run to fast run test
onece, and to set --count to some large enough number for g
On 3/4/21 5:17 AM, Vladimir Sementsov-Ogievskiy wrote:
It probably may improve reliability of results when testing in cached
mode.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/simplebench/bench_block_job.py | 2 ++
1 file changed, 2 insertions(+)
diff --git a/scripts/simplebench/
On 2/19/21 6:46 AM, Peter Maydell wrote:
@@ -1,5 +1,5 @@
-Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``,
``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``)
-===
On 3/4/21 5:17 AM, Vladimir Sementsov-Ogievskiy wrote:
statistics.stdev raises if sequence length is less than two. Support
that case by hand.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/simplebench/simplebench.py | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --
On 3/4/21 5:17 AM, Vladimir Sementsov-Ogievskiy wrote:
Sometimes one of cells in a testing table runs too slow. And we really
don't want to wait so long. Limit number of runs in this case.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/simplebench/simplebench.py | 29
On 2/19/21 6:46 AM, Peter Maydell wrote:
Add support for the mps3-an547 board; this is an SSE-300 based
FPGA image that runs on the MPS3.
Signed-off-by: Peter Maydell
---
Reviewed-by: Richard Henderson
r~
On Thu, Mar 04, 2021 at 11:23:22PM +0100, Philippe Mathieu-Daudé wrote:
> We can only check if a vCPU has work with TCG.
> Restrict the has_work() handler to TCG by moving it to
> the TCGCPUOps structure, and adapt all the targets.
>
> cpu_common_has_work() is removed as being inlined in
> cpu_has
Ping.
On Thu, Feb 18, 2021 at 1:24 PM Doug Evans wrote:
> This is a 10/100 ethernet device that has several features.
> Only the ones needed by the Linux driver have been implemented.
> See npcm7xx_emc.c for a list of unimplemented features.
>
> Doug Evans (3):
> hw/net: Add npcm7xx emc model
On Thu, Mar 04, 2021 at 11:42:10PM +0100, Philippe Mathieu-Daudé wrote:
> On 3/4/21 9:16 PM, BALATON Zoltan wrote:
> > On Thu, 4 Mar 2021, Philippe Mathieu-Daudé wrote:
> >> On 3/2/21 10:11 PM, BALATON Zoltan wrote:
> >>> To allow reusing ISA bridge emulation for vt8231_isa move the device
> >>> st
On Thu, Mar 04, 2021 at 11:23:20PM +0100, Philippe Mathieu-Daudé wrote:
65;6203;1c> POWER CPUs have specific CPUClass::has_work() handlers.
> In preparation of moving this field to TCGCPUOps, we need
> to duplicate the current ppc_tcg_ops structure for the
> POWER cpus.
>
> Signed-off-by: Philippe
On 2/19/21 6:46 AM, Peter Maydell wrote:
The AN547 configures the SSE-300 with a different initsvtor0
setting from its default; make this a board-specific setting.
Signed-off-by: Peter Maydell
---
Reviewed-by: Richard Henderson
r~
On 2/19/21 6:46 AM, Peter Maydell wrote:
The AN547 runs the APB peripherals outside the SSE-300 on a different
and slightly slower clock than it runs the SSE-300 with. Support
making the APB peripheral clock frequency board-specific. (For our
implementation only the UARTs actually take a clock.
On Fri, 5 Mar 2021 at 01:31, Gerd Hoffmann wrote:
> Hi,
>
> > Would adding support to host-libusb to use these
> > ioctl to claim the port be beneficial?
>
> I don't feel like side-stepping libusb. That is asking for trouble
> because usbdevfs might behave differently then and confuse libusb.
On 2/19/21 6:46 AM, Peter Maydell wrote:
Implement the minor changes required to the SCC block for AN547 images:
* CFG2 and CFG5 exist (like AN524)
* CFG3 is reserved (like AN524)
* CFG0 bit 1 is CPU_WAIT; we don't implement it, but note this
in the TODO comment
Signed-off-by: Peter Ma
On 2/28/21 9:39 PM, Like Xu wrote:
Hi Genius,
I am a user of QEMU v4.2.0 and stuck in an interesting bug, which may
still exist in the mainline.
Thanks in advance to heroes who can take a look and share understanding.
Do you have a test case that reproduces on 5.2? It'd be nice to know if
On 2/18/21 12:56 PM, Philippe Mathieu-Daudé wrote:
The SDHC_SYSAD and SDHC_BLKSIZE can not be accessed while a
transaction is in progress, see 'SD Host Controller Simplified
Specification'
1.5) SD Command Generation
The Host Driver should not read the SDMA System Address, Block
Size an
On 3/4/21 3:16 AM, Zenghui Yu wrote:
> Quote docs/devel/style.rst (section "Automatic memory deallocation"):
>
> * Variables declared with g_auto* MUST always be initialized,
> otherwise the cleanup function will use uninitialized stack memory
>
> Initialize @name properly to get rid of the com
On 3/4/21 3:16 AM, Zenghui Yu wrote:
> Quote docs/devel/style.rst (section "Automatic memory deallocation"):
>
> * Variables declared with g_auto* MUST always be initialized,
> otherwise the cleanup function will use uninitialized stack memory
>
> Initialize @name properly to get rid of the com
On 3/4/21 11:10 PM, Mark Cave-Ayland wrote:
> This patch series comes from an experimental branch that I've been working on
> to try and boot a MacOS toolbox ROM under the QEMU q800 machine. The effort is
...
> v3:
> - Rebase onto master (fix up minor conflicts with Paolo's SCSI error handling
> c
On 3/4/21 11:01 PM, Laurent Vivier wrote:
> Implement the goldfish tty device as defined in
>
> https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
>
> and based on the kernel driver code:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvald
On Wed, Mar 3, 2021 at 12:37 PM Alex Bennée wrote:
>
> Hypervisors, especially type-1 ones, need the firmware/bootcode to put
> their initial guest somewhere in memory and pass the information to it
> via platform data. The guest-loader is modelled after the generic
> loader for exactly this sort
On 3/4/21 11:01 PM, Laurent Vivier wrote:
> Implement the goldfish pic device as defined in
>
> https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
>
> Signed-off-by: Laurent Vivier
> ---
> include/hw/intc/goldfish_pic.h | 33 +
> hw/intc/
On Thu, Mar 4, 2021 at 9:03 AM Markus Armbruster wrote:
>
> Almost all QOM type names consist only of letters, digits, '-', '_',
> and '.'. Just two contain ':': "qemu:memory-region" and
> "qemu:iommu-memory-region". Neither can be plugged with -object.
> Rename them to "memory-region" and "iomm
On 3/4/21 9:35 PM, Niek Linnenbank wrote:
> Update the download URL of the Armbian 20.08 Bionic image for
> test_arm_orangepi_bionic_20_08 of the orangepi-pc machine.
>
> The archive.armbian.com URL contains more images and should keep stable
> for a longer period of time than dl.armbian.com.
>
>
On 3/4/21 11:01 PM, Laurent Vivier wrote:
> A (generic) copy of the GLUE device we already have for q800 to use with
> the m68k-virt machine.
> The q800 one would disappear in the future as q800 uses actually the djMEMC
> controller.
>
> Signed-off-by: Laurent Vivier
> ---
> include/hw/intc/m68k
We can only check if a vCPU has work with TCG.
Move the cpu_has_work() prototype to "sysemu/tcg.h".
Signed-off-by: Philippe Mathieu-Daudé
---
RFC: could another accelerator do that?
can we rename this tcg_vcpu_has_work()?
---
include/hw/core/cpu.h | 16
include/sysemu/tcg.h
arm_cpu_has_work() is only used from TCG.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 2 +-
target/arm/cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1930be08828..db81db9bf57 100644
-
Invert the #ifdef'ry to easily restrict tcg_exec_init() declaration
to CONFIG_TCG.
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/tcg.h | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
index 00349fb18a7..fddde2b6
We can only check if a vCPU has work with TCG.
Restrict the has_work() handler to TCG by moving it to
the TCGCPUOps structure, and adapt all the targets.
cpu_common_has_work() is removed as being inlined in
cpu_has_work().
Reviewed-by: Taylor Simpson
Signed-off-by: Philippe Mathieu-Daudé
---
v2
POWER CPUs have specific CPUClass::has_work() handlers.
In preparation of moving this field to TCGCPUOps, we need
to duplicate the current ppc_tcg_ops structure for the
POWER cpus.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/translate_init.c.inc | 69 +
1
The SCSI bus should remain in the message out phase after the SATN and stop
command rather than transitioning to the command phase. A new ESPState variable
cmdbuf_cdb_offset is added which stores the offset of the CDB from the start
of cmdbuf when accumulating extended message out phase data.
Curr
On 3/4/21 9:16 PM, BALATON Zoltan wrote:
> On Thu, 4 Mar 2021, Philippe Mathieu-Daudé wrote:
>> On 3/2/21 10:11 PM, BALATON Zoltan wrote:
>>> To allow reusing ISA bridge emulation for vt8231_isa move the device
>>> state of vt82c686b_isa emulation in an abstract via_isa class.
>>>
>>> Signed-off-by
We will restrict the s390_cpu_has_work() function to TCG.
First declare it in "internal.h" and move it to excp_helper.c.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/internal.h| 1 +
target/s390x/cpu.c | 17 -
target/s390x/excp_hel
At this point it is now possible to properly implement the FIFO flush command
without causing guest errors.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 2dded90be6..6aae6f9
The bottom 5 bits contain the number of bytes remaining in the FIFO which is
trivial to implement with Fifo8 (the remaining bits are unimplemented and left
as 0 for now).
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 4
Hi,
cpu_has_work() isn't used out of TCG, so restrict it to it.
RFC because maybe it could?
Since v1:
- finished PPC
- check cc->tcg_ops->has_work non-null (thuth)
Based-on: <20210227232519.222663-1-richard.hender...@linaro.org>
Philippe Mathieu-Daudé (8):
sysemu/tcg: Restrict tcg_exec_init()
Currently the target selection for PDMA is done after the SCSI command has been
delivered which is not correct. Perform target selection as part of the initial
get_cmd() call when the command is submitted: if no target is present, don't
raise DRQ.
If the target is present then switch to the comman
This matches the description in the datasheet and is required as support for
non-DMA transfers is added.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index eb6681ca66..4ac299
Rename ESP_CMDBUF_SZ to ESP_CMDFIFO_SZ and cmdbuf_cdb_offset to
cmdfifo_cdb_offset
to indicate that the command buffer type has changed from an array to a Fifo8.
This also enables us to remove the ESPState field cmdlen since the command
length
is now simply the number of elements used in cmdfifo
There is only one CPUClass::has_work() ARM handler: arm_cpu_has_work().
Avoid a dereference by declaring it in "internals.h" and call it
directly in the WFI helper.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 1 +
target/arm/cpu.c | 2 +-
target/arm/op_helper.c | 2
The cmdbuf is really just a copy of FIFO data (including extra message phase
bytes) so its pdma_origin is effectively TI. Fortunately we already know when
we are receiving a SCSI command since do_cmd == 1 which enables us to
distinguish between the two cases in esp_pdma_read()/esp_pdma_write().
Si
The MacOS toolbox ROM issues a command to the ESP controller as part of its
"FAST" SCSI routines and then proceeds to read the incoming data soon after
receiving the command completion interrupt.
Unfortunately due to SCSI block transfers being asynchronous the incoming data
may not yet be present
Rename TI_BUFSZ to ESP_FIFO_SZ since this constant is really describing the size
of the FIFO and is not directly related to the TI size.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 118 ++---
qemu_tcg_mttcg_enabled() shouldn't not be used outside of TCG,
restrict its declaration.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 9 -
include/sysemu/tcg.h | 9 +
accel/tcg/cpu-exec.c | 1 +
tcg/tcg.c | 1 +
4 files changed, 11 insertions(+)
Now that all SCSI commands are accumulated in cmdbuf, remove the buf parameter
from do_cmd() since this always points to cmdbuf.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 13 +++--
1 file changed, 7 insertions(+)
Currently the ESP_RINTR register is set to a specific value as required within
the ESP state machine. In order to implement the upcoming deferred interrupt
functionality it is necessary to set individual bits within ESP_RINTR so that
a deferred interrupt will not overwrite the value of any other in
Some guests use a mixture of DMA and non-DMA transfers in combination with the
SATN and stop command to transfer message out phase and command phase bytes to
the target. Prepare for the next commit by adding a maxlen parameter to
get_cmd() to allow partial transfers.
Signed-off-by: Mark Cave-Aylan
When the MacOS toolbox ROM transfers data from a target device to an unaligned
memory address, the first/last byte of a 16-bit transfer needs to be handled
separately. This means that the first byte is preloaded into the FIFO before
the transfer, or the last byte remains in the FIFO after the trans
ESP SCSI commands are already accumulated in cmdbuf and so there is no need to
keep a separate pdma_buf buffer. Accumulate SCSI commands for PDMA transfers in
cmdbuf instead of pdma_buf so update cmdlen accordingly and change pdma_origin
for PDMA transfers to CMD which allows the PDMA origin to be
PDMA as implemented on the Quadra 800 uses DREQ to load data into the FIFO
up to a maximum of 16 bytes at a time. The MacOS toolbox ROM requires this
because it mixes FIFO and PDMA transfers whilst checking the FIFO status
and counter registers to ensure success.
Signed-off-by: Mark Cave-Ayland
R
The MacOS toolbox ROM performs 4 byte reads/writes when transferring data to
and from the target. Since the SCSI bus is 16-bits wide, use the memory API
to split a 4 byte access into 2 x 2 byte accesses.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Viv
The MacOS toolbox ROM uses non-DMA TI commands to handle the first/last byte
of an unaligned 16-bit transfer to memory.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 133 ++
include/hw/scsi/esp.h | 1 +
2 files
This is the first step in removing get_pdma_buf() from esp.c.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 34 --
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/hw/scsi/esp.c
Real hardware simply counts down using the in-built TC to determine when the
the PDMA request is complete. Use the TC to determine the PDMA transfer length
which then enables us to remove the redundant pdma_len variable.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewe
Now that all data is transferred via the FIFO (ti_buf) there is no need to track
the source buffer being used for the data transfer. This also eliminates the
need for a separate subsection for PDMA state migration.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c
Commit ea84a44250 "scsi: esp: Defer command completion until previous interrupts
have been handled" provided a mechanism to delay the command completion
interrupt
until ESP_RINTR is read after the command has completed.
With the previous fixes for latching the ESP_RINTR bits and deferring the
se
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 07d57cb791..0fafc866a4 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -151,6 +151
This eliminates the last user of the PDMA-specific pdma_cur variable which can
now be removed.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 23 ---
include/hw/scsi/esp.h | 1 -
2 files changed,
Now that PDMA SCSI commands are accumulated in cmdbuf in the same way as normal
commands, the existing logic for locating the start of the SCSI command in
cmdbuf via cmdlen can be used. This enables the PDMA-specific pdma_start and
also get_pdma_buf() to be removed.
Signed-off-by: Mark Cave-Ayland
This better describes the purpose of the function.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index d5c03f9697..d8
The limiting of DMA transfers to the maximum size of the available data is
already
handled by esp_do_dma() and do_dma_pdma_cb().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 12 ++--
1 file changed, 2 insertions(+)
Here the updates to async_len and ti_size are moved into the corresponding
esp_pdma_read()/esp_pdma_write() function to eliminate the reference to
pdma_cur in do_dma_pdma_cb().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 24 ++--
1 file ch
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 50 --
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 58be98f047..b8d1ec41e9 1
Now that all SCSI commands are accumulated in cmdbuf, remove the buf and buflen
parameters from get_cmd() since these always reference cmdbuf and ESP_CMDBUF_SZ
respectively.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 11 +
The ESP device already keeps track of the remaining bytes left to transfer via
its TC (transfer counter) register which is decremented for each byte that
is transferred across the SCSI bus.
Switch the transfer logic to use the value of TC instead of dma_left and then
remove dma_left completely, ad
The value of dma_counter is set once at the start of the transfer and remains
the same until the transfer is complete. This allows the check in
esp_transfer_data
to be simplified since dma_left will always be non-zero until the transfer is
completed.
Signed-off-by: Mark Cave-Ayland
Reviewed-by:
These functions simplify reading and writing the TC register value without
having to
manually shift each individual 8-bit value.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
---
hw/scsi/esp.c | 38 +++---
1 fil
Perform the length adjustment whereby a value of 0 in the STC represents
a transfer length of 0x1 at the point where the TC is loaded at the
start of a DMA command rather than just when a TI (Transfer Information)
command is executed. This better matches the description as given in the
datashee
1 - 100 of 357 matches
Mail list logo
