[PATCH] net: Fix build error when DEBUG_NET is on

From: Bin Meng "qemu-common.h" should be included to provide the forward declaration of qemu_hexdump() when DEBUG_NET is on. Signed-off-by: Bin Meng --- net/net.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/net.c b/net/net.c index fb7b7dc..32d71c1 100644 --- a/net/net.c +++ b/net/

Re: [PATCH] multiprocess: move feature to meson_options.txt

On 26/02/21 00:16, Philippe Mathieu-Daudé wrote: I personally don’t have any preference for the name. Great. So with the summary/description updated as: summary_info += {'Multiprocess QEMU (vfio-user device backends)': multiprocess_allowed} option('multiprocess', type: 'feature', value: 'auto

Re: [PATCH] e1000: fail early for evil descriptor

On 2021/2/24 1:45 下午, Jason Wang wrote: During procss_tx_desc(), driver can try to chain data descriptor with legacy descriptor, when will lead underflow for the following calculation in process_tx_desc() for bytes: if (tp->size + bytes > msh) bytes = msh - tp->si

Re: [PATCH] iotests: Fix up python style in 300

16.02.2021 02:21, John Snow wrote: On 2/15/21 5:05 PM, Eric Blake wrote: Break some long lines, and relax our type hints to be more generic to any JSON, in order to more easily permit the additional JSON depth now possible in migration parameters.  Detected by iotest 297. Fixes: ca4bfec41d56  

Re: [PATCH] iotests: Fix up python style in 300

16.02.2021 01:05, Eric Blake wrote: Break some long lines, and relax our type hints to be more generic to any JSON, in order to more easily permit the additional JSON depth now possible in migration parameters. Detected by iotest 297. Fixes: ca4bfec41d56 (qemu-iotests: 300: Add test case for

Re: [PATCH 3/6] dp8393x: switch to use qemu_receive_packet() for loopback packet

On 2021/2/25 10:42 下午, Stefan Weil wrote: Am 25.02.21 um 15:36 schrieb Philippe Mathieu-Daudé: On 2/24/21 7:13 AM, Stefan Weil wrote: Am 24.02.21 um 06:53 schrieb Jason Wang: This patch switches to use qemu_receive_packet() which can detect reentrancy and return early. Signed-off-by: Jaso

[PATCH 4/4] hw/misc: Model KCS devices in the Aspeed LPC controller

Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC IO cycles from the BMC to the host. Expose support on the BMC side by implementing the usual MMIO behaviours, and expose the ability to inspect the KCS registers in "host" style by accessing QOM properties associated with each

[PATCH 3/4] hw/misc: Add a basic Aspeed LPC controller model

From: Cédric Le Goater This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space. Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery --- docs/system/arm/aspeed.rst | 2 +- hw/a

[PATCH 1/4] arm: ast2600: Force a multiple of 32 of IRQs for the GIC

This appears to be a requirement of the GIC model. The AST2600 allocates 197 GIC IRQs, which we will adjust shortly. Signed-off-by: Andrew Jeffery --- hw/arm/aspeed_ast2600.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c

[PATCH 2/4] arm: ast2600: Fix iBT IRQ ID

The AST2600 allocates individual GIC IRQ lines for the LPC sub-devices. This is a contrast to the AST2400 and AST2500 which use one shared VIC IRQ line for the LPC sub-devices. Switch the iBT device to use the GIC IRQ ID documented in the datasheet. While we're here, set the number of IRQs to the

[PATCH 0/4] aspeed: LPC peripheral controller devices

Hello, This series adds support for some of the LPC[1] peripherals found in Aspeed BMC SoCs. BMCs typically provide a number of features to their host via LPC that include but are not limited to: 1. Mapping LPC firmware cycles to BMC-controlled flash devices 2. UART(s) for system console routing

Re: QEMU Clock record and replay

On 25.02.2021 18:43, Philippe Mathieu-Daudé wrote: Cc'ing Pavel/Alex. On 2/25/21 4:09 PM, Arnabjyoti Kalita wrote: Hello all, I am trying to understand how the clock values are recorded and replayed in QEMU (when it runs in TCG mode). I have been specifically following the document that has be

Re: [PATCH] hvf: Sign the code after installation

2021年2月25日(木) 22:48 Paolo Bonzini : > > On 25/02/21 01:06, Akihiko Odaki wrote: > > Before this change, the code signed during the build was installed > > directly. > > > > However, the signature gets invalidated because meson modifies the code > > to fix dynamic library install names during the in

Re: [PATCH] virtio-gpu: Respect graphics update interval for EDID

2021年2月25日(木) 20:46 Gerd Hoffmann : > > Hi, > > > > Because of the wasted frames I'd like this to be an option you can > > > enable when needed. For the majority of use cases this seems to be > > > no problem ... > > > > I see blinks with GNOME on Wayland on Ubuntu 20.04 and virtio-gpu with > >

[PATCH v2 2/2] hw/riscv: allow ramfb on virt

Allow ramfb on virt. This lets `-device ramfb' work. Signed-off-by: Asherah Connor --- Changes in v2: * Add DMA interface support. * Add ramfb as allowed on riscv virt machine class. hw/riscv/virt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index

[PATCH v2 1/2] hw/riscv: Add fw_cfg support to virt

Provides fw_cfg for the virt machine on riscv. This enables using e.g. ramfb later. Signed-off-by: Asherah Connor --- Changes in v2: * Add DMA support (needed for writes). hw/riscv/Kconfig| 1 + hw/riscv/virt.c | 27 +++ include/hw/riscv/virt.h | 4 +

Re: [PATCH v2 10/10] target/hexagon: import additional tests

On 2/25/21 7:18 AM, Alessandro Di Federico wrote: > +++ b/tests/tcg/hexagon/first.S > @@ -21,24 +21,24 @@ > > #define FD_STDOUT1 > > - .type str,@object > - .section.rodata > +.typestr,@object > +.section .rodata > str: > - .string "Hello!\n"

[PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()

From: Frank Chang rvv v0.10 adds vector unit-stride mask load/store instructions (vle1.v, vse1.v), which has: evl (effective vector length) = ceil(env-vl/8). The new instructions operate the same as unmasked byte loads and stores. Add evl parameter to reuse vext_ldst_us(). Signed-off-by: Fr

[PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid

From: Frank Chang If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check and trig

[PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function

From: Frank Chang helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang --- target/riscv/fpu_helper.c | 5 + target/riscv/helper.h | 1 +

[PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions

From: Frank Chang Add the following instructions: * vfcvt.rtz.xu.f.v * vfcvt.rtz.x.f.v Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 11 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 83

[PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert

From: Frank Chang Add the following instructions: * vfwcvt.rtz.xu.f.v * vfwcvt.rtz.x.f.v Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 + target/riscv/insn32.decode

[PATCH v2 0/2] hw/riscv: Add fw_cfg support, allow ramfb

Here's version two of the series to bring fw_cfg support to riscv's virt machine. We add support for the DMA interface, as this is needed for writes. The ultimate goal is to add ramfb support, in the second patch. It works well! Changes in v2: * Add DMA interface support. * Add ramfb as allowed

[PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions

From: Frank Chang * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/

[PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/csr.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index aa76da9e185..e0f1106d909 100644 --- a/target/riscv/csr.c +++ b/target/risc

Re: [PATCH v22 16/17] i386: gdbstub: only write CR0/CR2/CR3/EFER for SOFTMMU

On 2/25/21 12:55 AM, Claudio Fontana wrote: > On 2/25/21 5:19 AM, Richard Henderson wrote: >> On 2/24/21 5:34 AM, Claudio Fontana wrote: >>> Signed-off-by: Claudio Fontana >>> Cc: Paolo Bonzini >>> --- >>> target/i386/gdbstub.c | 16 >>> 1 file changed, 16 insertions(+) >>> >>>

[PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions

From: Frank Chang Sign-extend vsaddu.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans

Re: [RFC v1 27/38] target/arm: move sve_zcr_len_for_el to common_cpu

On 2/25/21 12:13 PM, Claudio Fontana wrote: > sve_zcr_len_for_el is also called in arch_dump.c in aarch64_write_el64_sve, > via sve_current_vq(). > > Wonder if a stub is needed, or we need the whole implementation.. For sve_zcr_len_for_el, I'd use the whole thing. The dump seems to be callable

[PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits

From: Frank Chang Signed-off-by: Frank Chang -- Signed-off-by: Frank Chang --- target/riscv/cpu.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/targ

Re: [PATCH v2 09/10] target/hexagon: call idef-parser functions

On 2/25/21 7:18 AM, Alessandro Di Federico wrote: > +elif hex_common.is_new_val(regtype, regid, tag): > +declared.append("%s%sN" % (regtype,regid)) > +else: > +print("Bad register parse: ",regtype,regid,toss,numregs) print, but nothing to for

[PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions

From: Frank Chang Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 14 + target/riscv/insn32.decode | 8 +++ target

Re: [PATCH v2 08/10] target/hexagon: import parser for idef-parser

On 2/25/21 7:18 AM, Alessandro Di Federico wrote: > +instructions : instruction instructions > +| %empty > +; I have never seen bison written flush-left like this, and I find it really hard to read, especially with some of the larger non-terminals. I'm also not a fan of large blocks of code withi

[PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c5e65720120..e3056a06fe2

[PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions

From: Frank Chang * Add vrgatherei16.vv instruction. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 27 ++--- target/r

[PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.c.inc | 40 + target/riscv/vector_helper.c| 21 + 4 files changed

[PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11

From: Frank Chang Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn

[PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions

From: Frank Chang log(SEW) truncate vssra.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/i

[PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended

From: Frank Chang For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 32 + 1 file changed, 22 insertions(+), 10 deletions(-) dif

[PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.c.inc | 30 + 2 files changed, 32 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6fb85c83278..47

[PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/csr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e0f1106d909..0082db9cc0c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -209,7 +209,7 @@ stati

[PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index c4b03

[PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction

From: Frank Chang Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper

[PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index fae5ea3fa63..a593938e5c8 100644 --- a/target/riscv/insn32

[PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/gdbstub.c | 184 + 3 files changed, 187 insertions(+) diff --git

[PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 12 +--- target/riscv/vector_helper.c| 12 ++-- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rv

[PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction

From: Frank Chang Implement the floating-point reciprocal square-root estimate to 7 bits instruction. Signed-off-by: Frank Chang --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/v

[PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 7 --- target/riscv/vector_helper.c| 6 +++--- 4 files chang

[PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 12 +++--- target/riscv/vector_helper.c| 52

[PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR

From: Frank Chang * Update and check vstart value for vector instructions. * Add whole register move instruction helper functions as we have to call helper function for case where vstart is not zero. Signed-off-by: Frank Chang -- Perhaps we can remove the probe functions in vector_helper.c

[PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 22 +- target/riscv/insn32.decode | 15 --- target/riscv/insn_trans/trans_rvv.c.inc | 58 + target/riscv/vector_helper.c| 45 ++

[PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e11666f16df..c0053cfb828 1

[PATCH v7 50/75] target/riscv: rvv-1.0: floating-point slide instructions

From: Frank Chang Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.c.inc | 16 +++ target/riscv/vector_helper.c

[PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 6 -- target/riscv/insn32.decode | 2 -- target/riscv/insn_trans/trans_rvv.c.inc | 2 -- target/riscv/vector_helper.c| 7 --- 4 files chang

[PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 12 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- target/riscv/internals.h| 9 + 3 files changed, 24 insertions(+),

[PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions

From: Frank Chang Add the following instructions: * vlre.v * vsr.v Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 21 target/riscv/insn32.decode | 22 target/riscv/insn_trans/trans_rvv.c.inc | 69 +

[PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c| 4 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/ri

[PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_rvv.c.inc | 23 --- 2 files changed, 24 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.

[PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 22 --- target/riscv/insn32.decode | 7 - target/riscv/insn_trans/trans_rvv.c.inc | 9 -- target/riscv/vector_helper.c| 205 --

[PATCH v7 22/75] target/riscv: rvv-1.0: amo operations

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 100 +++--- target/riscv/insn32-64.decode | 18 +- target/riscv/insn32.decode | 36 +++- target/riscv/insn_trans/trans_rvv.c.inc | 229 +

[PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 8 1 file changed, 8 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 5622fb23f85..93ed6f54e99 100644 --- a/target/riscv/vector_he

[PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 53 + target/riscv/vector_helper.c| 14 ++- 2 files changed, 31 insertions(+), 36 deletions(-) diff

[PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions

From: Frank Chang * Sign-extend vmselu.vi and vmsgtu.vi immediate values. * Remove "set tail elements to zeros" as tail elements can be unchanged for either VTA to have undisturbed or agnostic setting. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/tra

[PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 022530697ec..8467dfc84b1 100644 --- a/target/riscv/

[PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions

From: Frank Chang Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 16 ++ target/riscv/insn32.decode

[PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +- target/riscv/insn_trans/trans_rvv.c.inc | 30 - target/riscv/vecto

[PATCH v7 14/75] target/riscv: rvv-1.0: update check functions

From: Frank Chang Update check functions with RVV 1.0 rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 732 1 file changed, 499 insertions(+), 233 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv

[PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow

From: Frank Chang * Only do carry-in or borrow-in if is masked (vm=0). * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 20 ++-- target/riscv/insn_trans/trans_

[PATCH v7 38/75] target/riscv: rvv-1.0: whole register move instructions

From: Frank Chang Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.c.inc | 25 + 2 files changed, 29 insertions(+) diff --git a/t

[PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions

From: Frank Chang Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/tra

[PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 10 -- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/ins

[PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.c.inc | 39 + target/riscv/internals.h| 5 3

[PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn

[PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL

From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600) and MSTATUS_FS (0x6000) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by:

[PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions

From: Frank Chang * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.c.inc | 45 - 2 files chang

[PATCH v7 27/75] target/riscv: rvv-1.0: floating-point classify instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c0053cfb828..a0a47dbceb3 1

[PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 5 - target/riscv/vector_helper.c| 4 3 files changed, 7 insertions(+), 8 deletions(-) diff --git

[PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/r

[PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 6 +++--- 4 files changed,

[PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 32 +++-- target/riscv/vector_helper.c| 90 ++--- 2 files changed, 74 insertions(+), 48 deletions(-) diff --git a/target/riscv/insn_tran

[PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register

From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv

[PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function

From: Frank Chang * Add fp16 nan-box check generator function, if a 16-bit input is not properly nanboxed, then the input is replaced with the default qnan. * Add do_nanbox() helper function to utilize gen_check_nanbox_X() to generate the NaN-boxed floating-point values based on SEW setting.

[PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation

From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 43 ++--- target/riscv/insn_tr

[PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 8 1 file changed, 4 i

[PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions

From: Frank Chang Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW)

[PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status

From: Frank Chang Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 69 - target/riscv/translate.c| 33 2 files changed, 90 inser

[PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 27 +++- target/riscv/insn32.decode | 14 +++ target/riscv/insn_trans/trans_rvv.c.inc | 33 --- target/r

[PATCH v7 19/75] target/riscv: rvv-1.0: index load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 67 target/riscv/insn32.decode | 21 ++- target/riscv/insn_trans/trans_rvv.c.inc | 209 target/riscv/vector_helper.c

[PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations

From: Frank Chang As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 35 +--- target/riscv/inter

[PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field

From: Frank Chang Implementations may have a writable misa.v field. Analogous to the way in which the floating-point unit is handled, the mstatus.vs field may exist even if misa.v is clear. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/ris

[PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 129 +++--- target/riscv/insn32.decode | 43 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 227 +++- target/riscv/vector_helper.c

[PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers

From: Frank Chang * Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. * Remove RVV loose check in fs() predicate function. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 13

[PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 21 + 2 files changed, 28 insertions(+) diff --git a/target/riscv/cpu_bi

[PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a156573d281..bc3f212

[PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target

[PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 7 +++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 15 ++- target/riscv/csr.c| 25

[PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 +- target/riscv/cpu.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16f1a34238

[PATCH v7 00/75] support vector extension v1.0

From: Frank Chang This patchset implements the vector extension v1.0 for RISC-V on QEMU. The port is available here: https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=v1.0) to run with RVV v1.0 instructions. Note: This pa

Re: [PATCH] exec/memory: Use struct Object typedef

On Thu, Feb 25, 2021 at 07:20:03PM +0100, Philippe Mathieu-Daudé wrote: > We forward-declare Object typedef in "qemu/typedefs.h" since commit > ca27b5eb7cd ("qom/object: Move Object typedef to 'qemu/typedefs.h'"). > Use it everywhere to make the code simpler. > > Signed-off-by: Philippe Mathieu-Da

Re: [RFC PATCH 5/5] hw/arm/virt-acpi-build: add PPTT table

On 2/25/2021 7:38 PM, Andrew Jones wrote: This is just [*] with some minor code changes [*] https://github.com/rhdrjones/qemu/commit/439b38d67ca1f2cbfa5b9892a822b651ebd05c11 so it's disappointing that my name is nowhere to be found on it. Also, the explanation of the DT and ACPI differenc

Re: [RFC PATCH 4/5] hw/acpi/aml-build: add processor hierarchy node structure

On 2/25/2021 7:47 PM, Andrew Jones wrote: On Thu, Feb 25, 2021 at 04:56:26PM +0800, Ying Fang wrote: Add the processor hierarchy node structures to build ACPI information for CPU topology. Since the private resources may be used to describe cache hierarchy and it is variable among different t

  1   2   3   4   >