On 10/02/2021 22:33, Philippe Mathieu-Daudé wrote:
On 2/9/21 8:29 PM, Mark Cave-Ayland wrote:
This simplifies reading the STC register value without having to manually shift
each individual 8-bit value.
If possible repeat the subject so the sentence is easier to understand.
I've always read
On Feb 11 11:55, Minwoo Im wrote:
> On 21-02-09 12:08:26, Klaus Jensen wrote:
> > From: Klaus Jensen
> >
> > Move a bunch of functions that are internal to a device out of the
> > shared header.
>
> May I ask why? I think some kind of these helpers can stick onto the
> header.
I just thought t
On Feb 11 13:24, Keith Busch wrote:
> On Thu, Feb 11, 2021 at 12:38:48PM +0900, Minwoo Im wrote:
> > On 21-02-11 12:00:11, Keith Busch wrote:
> > > But I would prefer to see advanced retry tied to real errors that can be
> > > retried, like if we got an EBUSY or EAGAIN errno or something like that.
Hi Minwoo,
Please ignore this mail, I see a fix already floating around in the list.
Regards,
Sai Pavan
On Thu, Feb 11, 2021 at 12:15:57PM +0530, Sai Pavan Boddu wrote:
> Hi Minwoo,
>
> On Sun, Jan 17, 2021 at 11:53:32PM +0900, Minwoo Im wrote:
> > Volatile Write Cache(VWC) feature is set in nvm
On Fri, Feb 5, 2021 at 5:54 PM wrote:
>
> From: Phillip Tennen
>
> This patch implements a new netdev device, reachable via -netdev
> vmnet-macos, that’s backed by macOS’s vmnet framework.
>
> The vmnet framework provides native bridging support, and its usage in
> this patch is intended as a rep
update golden master acpi tables and empty
bios-tables-test-allowed-diff.h.
Signed-off-by: Isaku Yamahata
---
tests/data/acpi/q35/DSDT| Bin 7801 -> 7892 bytes
tests/data/acpi/q35/DSDT.acpihmat | Bin 9126 -> 9217 bytes
tests/data/acpi/q35/DSDT.bridge |
If SMM is not supported, ACPI fixed hardware doesn't support
legacy-mode. ACPI-only platform. Where SCI_EN in PM1_CNT register is
always set.
The bit tells OS legacy mode(SCI_EN cleared) or ACPI mode(SCI_EN set).
With the next patch (setting fadt.smi_cmd = 0 when smm isn't enabled),
guest Linux tr
Reviewed-by: Igor Mammedov
Signed-off-by: Isaku Yamahata
---
tests/qtest/bios-tables-test.c | 12
1 file changed, 12 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 096d15db68..72c8765baf 100644
--- a/tests/qtest/bios-tables-test.c
+
From: Sean Christopherson
Omit HPET AML if the HPET is disabled, QEMU is not emulating it and the
guest may get confused by seeing HPET in the ACPI tables without a
"physical" device present.
The change of DSDT when -no-hpet is as follows.
@@ -141,47 +141,6 @@ DefinitionBlock ("", "DSDT", 1, "B
Declare PNP0C01 device to reserve MMCONFIG region to conform to the
spec better and play nice with guest BIOSes/OSes.
According to PCI Firmware Specification[0], MMCONFIG region must be
reserved by declaring a motherboard resource. It's optional to reserve
the region in memory map by Int 15 E820h
Reviewed-by: Igor Mammedov
Signed-off-by: Isaku Yamahata
---
tests/qtest/bios-tables-test.c | 12
1 file changed, 12 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 669202fc95..096d15db68 100644
--- a/tests/qtest/bios-tables-test.c
+
The following patch will introduce incompatible behavior of SMM.
Introduce a property to keep the old behavior for compatibility.
To enable smm compat, use "-machine x-smm-compat-5=on"
Signed-off-by: Isaku Yamahata
---
hw/i386/pc_piix.c | 10 ++
hw/i386/pc_q35.c | 1 +
hw/i386/
The following tests will modify acpi tables.
prepare qtests to allow acpi table change.
add new tables for new tests.
- tests/data/acpi/q35/DSDT.nosmm
- tests/data/acpi/q35/FACP.nosmm
- tests/data/acpi/q35/DSDT.nohpet
Acked-by: Igor Mammedov
Signed-off-by: Isaku Yamahata
---
tests/data/acpi/q35
>From table 5.9 SMI_CMD of ACPI spec
> This field is reserved and must be zero on system
> that does not support System Management mode.
When smm is not enabled, set it to zero to comform to the spec.
When -machine smm=off is passed, the change to FACP is as follows.
@@ -1,46 +1,46 @@
/*
* Int
Miscellaneous bug fixes related to ACPI to play nice with guest BIOSes/OSes
by conforming to ACPI spec better.
Changes from v2:
- improved commit message
- introduced compat property x-smm-compat-5
- _CRS for MMCONFIG resource, read MMCONFIG info from qemu, generate resource
instead of dynamical
Newly created acpi data files(tests/data/acpi/) cause false positive
warning.
If file names are acpi expected file, don't emit warning.
Fixes: e625ba2a41 ("checkpatch: fix acpi check with multiple file name")
Signed-off-by: Isaku Yamahata
---
scripts/checkpatch.pl | 4 +++-
1 file changed, 3 ins
Hi Minwoo,
On Sun, Jan 17, 2021 at 11:53:32PM +0900, Minwoo Im wrote:
> Volatile Write Cache(VWC) feature is set in nvme_ns_setup() in the
> initial time. This feature is related to block device backed, but this
> feature is controlled in controller level via Set/Get Features command.
>
> This
Hi Marc,
Requesting you to please pull these changes. Without this fix, migration
is failing in case any helper has more than 4KiB of data.
Thanks and Regards,
Priyankar Jain
On 02/02/21 7:24 pm, Priyankar Jain wrote:
This commit fixes an issue where migration is failing in the load phase
be
On 21-02-11 13:24:22, Keith Busch wrote:
> On Thu, Feb 11, 2021 at 12:38:48PM +0900, Minwoo Im wrote:
> > On 21-02-11 12:00:11, Keith Busch wrote:
> > > But I would prefer to see advanced retry tied to real errors that can be
> > > retried, like if we got an EBUSY or EAGAIN errno or something like
We already have similar jobs in the gitlab-CI ("build-some-softmmu" and
"build-user-plugins"), so let's switch one of them to use --enable-debug
instead of --enable-debug-tcg, then we can simply drop these jobs from
the Travis-CI.
Reviewed-by: Alex Bennée
Reviewed-by: Wainer dos Santos Moschetta
Simply add the flag to an existing job, no need for yet another
job here.
Reviewed-by: Wainer dos Santos Moschetta
Reviewed-by: Alex Bennée
Signed-off-by: Thomas Huth
---
.gitlab-ci.yml | 1 +
.travis.yml| 6 --
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/.gitlab-ci.y
On Thu, 28 Jan 2021 at 23:04, Shreyansh Chouhan <
chouhan.shreyansh2...@gmail.com> wrote:
> I think I will give it a quick look :P
>
This certainly wasn't quick I admit.
> Thanks a lot!
> --
> Shreyansh
>
> Hey! I hope you people are doing fine. :)
So colleges reopened and I was a bit busy for th
Add it to the existing Clang job and also add a job that covers the
linux-user code with this compiler flag. To make sure that the detected
problems are not simply ignored, let's also use "-fno-sanitize-recover=..."
now instead.
Signed-off-by: Thomas Huth
---
.gitlab-ci.yml | 16 +---
I was able to run the reproducer from Beraldo Leal, and achieved the
same results.
Additionally, I got the following output from QEMU:
qemu-system-x86_64: Missing character write event in the replay log
Which seems to come from replay/replay-char.c:158.
I then tested the record and replay se
From: Philippe Mathieu-Daudé
Similarly to commit 8cdb2cef3f1, move the gprof/gcov test to GitLab.
The coverage-summary.sh script is not Travis-CI specific, make it
generic.
[thuth: Add gcovr and bsdmainutils which are required for the
coverage-summary.sh script to the ubuntu docker file
Use clang-10, so we can also use the --enable-tsan configure
option instead of only passing the flag via --extra-cflags.
Reviewed-by: Alex Bennée
Signed-off-by: Thomas Huth
---
.gitlab-ci.yml | 9 +
.travis.yml| 51 --
2 files changed
Since Travis changed their policies, travis-ci.org will soon become
completely useless for the QEMU project. We should now really make sure
that we move the remaining tests as good as possible to the gitlab-CI
instead.
v3:
- Use 'debian-all-test-cross' and 'check-tcg' in the 2nd patch
- Adjusted
On Wed, Feb 10, 2021, 9:26 PM Keith Busch wrote:
> On Thu, Feb 11, 2021 at 12:38:48PM +0900, Minwoo Im wrote:
> > On 21-02-11 12:00:11, Keith Busch wrote:
> > > But I would prefer to see advanced retry tied to real errors that can
> be
> > > retried, like if we got an EBUSY or EAGAIN errno or som
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1906948
Title:
Enabling Op
On Thu, Feb 11, 2021 at 12:38:48PM +0900, Minwoo Im wrote:
> On 21-02-11 12:00:11, Keith Busch wrote:
> > But I would prefer to see advanced retry tied to real errors that can be
> > retried, like if we got an EBUSY or EAGAIN errno or something like that.
>
> I have seen a thread [1] about ACRE.
On 21-02-10 21:19:43, Klaus Jensen wrote:
> On Feb 11 04:52, Minwoo Im wrote:
> > @@ -945,6 +945,11 @@ static void nvme_post_cqes(void *opaque)
> > static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
> > {
> > assert(cq->cqid == req->sq->cqid);
> > +
> > +if (req->s
On 21-02-11 12:00:11, Keith Busch wrote:
> On Thu, Feb 11, 2021 at 04:52:52AM +0900, Minwoo Im wrote:
> > nvme_inject_state command is to give a controller state to be.
> > Human Monitor Interface(HMP) supports users to make controller to a
> > specified state of:
> >
> > normal:
On Wed, Feb 10, 2021 at 08:06:46AM +0100, Klaus Jensen wrote:
> From: Gollu Appalanaidu
>
> Add support for marking blocks invalid with the Write Uncorrectable
> command. Block status is tracked in a (non-persistent) bitmap that is
> checked on all reads and written to on all writes. This is pote
On 21-02-10 21:33:50, Klaus Jensen wrote:
> On Feb 11 04:52, Minwoo Im wrote:
> > nvme_inject_state command is to give a controller state to be.
> > Human Monitor Interface(HMP) supports users to make controller to a
> > specified state of:
> >
> > normal: Normal state (no inje
On Thu, Feb 11, 2021 at 04:52:52AM +0900, Minwoo Im wrote:
> nvme_inject_state command is to give a controller state to be.
> Human Monitor Interface(HMP) supports users to make controller to a
> specified state of:
>
> normal: Normal state (no injection)
> cmd-interrup
On 21-02-09 12:08:26, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Move a bunch of functions that are internal to a device out of the
> shared header.
May I ask why? I think some kind of these helpers can stick onto the
header.
On 21-02-09 12:08:25, Klaus Jensen wrote:
> From: Klaus Jensen
>
> With the introduction of the nvme-subsystem device we are really
> cluttering up the hw/block directory.
>
> As suggested by Philippe previously, move the nvme emulation to
> hw/nvme.
>
> Suggested-by: Philippe Mathieu-Daudé
>
On 21-01-27 14:15:05, Klaus Jensen wrote:
> From: Klaus Jensen
>
> For most commands, when issuing an AIO, the BlockAIOCB is stored in the
> NvmeRequest aiocb pointer when the AIO is issued. The purpose of storing
> this is to allow the AIO to be cancelled when deleting submission
> queues (it is
On 10.02.21 23:17, Peter Maydell wrote:
On Wed, 10 Feb 2021 at 20:25, Peter Collingbourne wrote:
On Thu, Jan 28, 2021 at 8:25 AM Peter Maydell wrote:
On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote:
+if (!seconds && nanos < 200) {
+break;
+
I found a way to fix the high host cpu usage issue. To fix this issue
click on Start->All Programs->Accessories->System Tools->System Restore.
Then pick a restore point that is set before you tried the smp option.
After the VM restarts the high CPU usage issue will be gone :)
--
You received this
On 2/9/21 2:20 PM, Peter Maydell wrote:
> Use the new clock_ns_to_ticks() function in npcm7xx_timer where
> appropriate.
>
> Signed-off-by: Peter Maydell
> ---
> hw/timer/npcm7xx_timer.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 2/9/21 2:20 PM, Peter Maydell wrote:
> Add a clock_ns_to_ticks() function which does the opposite of
> clock_ticks_to_ns(): given a duration in nanoseconds, it returns the
> number of clock ticks that would happen in that time. This is useful
> for devices that have a free running counter regis
Use the new clock_ns_to_ticks() function in cp0_timer where
appropriate. This allows us to remove CPUMIPSState::cp0_count_ns
and mips_cp0_period_set().
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <20210209132040.5091-1-peter.mayd...@linaro.org>
RFC because this is just a starter patch to
On 2/9/21 2:20 PM, Peter Maydell wrote:
> Add a new callback event type ClockPreUpdate, which is called on
> period changes before the period is updated.
>
> Signed-off-by: Peter Maydell
> ---
> docs/devel/clocks.rst | 9 -
> include/hw/clock.h| 1 +
> hw/core/clock.c | 3 +++
>
On Wed, Feb 10, 2021 at 8:49 AM Daniel P. Berrangé
wrote:
> On Wed, Feb 10, 2021 at 08:31:40AM -0800, Doug Evans wrote:
> > On Wed, Feb 10, 2021 at 1:31 AM Daniel P. Berrangé
> > wrote:
> >
> > > On Tue, Feb 09, 2021 at 06:16:57PM -0800, Doug Evans wrote:
> > > > On Thu, Feb 4, 2021 at 10:25 AM
On Wed, Feb 10, 2021 at 12:02 PM Pascal Scholz
wrote:
>
> Hi Alistair,
>
> thanks for your quick and helpful reply. :)
>
> I'll see, if I can try them out on the weekend and will report my results.
Great!
>
> Best regards and thanks again!
No worries!
Alistair
>
> Pascal
>
> On 08.02.21 23:49
I could reproduce this without Avocado:
--
#!/bin/bash
SOCKET="/tmp/qemu.sock"
VMLINUZ_PATH="/tmp/vmlinuz"
REPLAY_FILE="/tmp/replay.bin"
function run_and_wait() {
/usr/bin/qemu-system-x86_64 -display none \
-vga none \
When we exit a block under icount with instructions left to execute we
might need a shorter than normal block to take us to the next
deterministic event. Instead of creating a throwaway block on demand
we use the existing compile flags mechanism to ensure we fetch (or
compile and fetch) a block wit
Now we no longer generate CF_NOCACHE blocks we can remove a bunch of
the special case handling for them. While we are at it we can remove
the unused tb->orig_tb field and save a few bytes on the TB structure.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20210209182749.3
Hi Mark,
On 2/9/21 8:29 PM, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/scsi/esp.c | 28
> 1 file changed, 20 insertions(+), 8 deletions(-)
>
> diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
> index e7cf36f4b8..b0cba889a9 100644
> --- a/hw/scsi/
This is just a simple test to count the instructions executed by a
kernel. However a later test will detect a failure condition when
icount is enabled.
Signed-off-by: Alex Bennée
Message-Id: <20210209182749.31323-7-alex.ben...@linaro.org>
---
tests/acceptance/tcg_plugins.py | 103 +++
On Wed, 10 Feb 2021 at 20:53, Hao Wu wrote:
>
>
>
> On Tue, Feb 9, 2021 at 5:24 AM Peter Maydell wrote:
>> diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
>> index 870a6d50c27..573f4876dc6 100644
>> --- a/hw/adc/npcm7xx_adc.c
>> +++ b/hw/adc/npcm7xx_adc.c
>> @@ -238,7 +238,7 @@ static vo
On Wed, 10 Feb 2021 at 22:21, Alexander Graf wrote:
>
>
> On 28.01.21 16:52, Peter Maydell wrote:
> > On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote:
> >> +break;
> >> +case EC_AA64_SMC:
> >> +cpu_synchronize_state(cpu);
> >> +if (arm_is_psci_call(a
On Wed, 10 Feb 2021 at 20:25, Peter Collingbourne wrote:
>
> On Thu, Jan 28, 2021 at 8:25 AM Peter Maydell
> wrote:
> >
> > On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote:
> > > +if (!seconds && nanos < 200) {
> > > +break;
> > > +}
>
On 2/9/21 8:29 PM, Mark Cave-Ayland wrote:
> The existing ESP QOM type currently represents a sysbus device with an
> embedded
> ESP state. Rename the type to SYSBUS_ESP accordingly.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/dma/sparc32_dma.c | 4 ++--
> hw/m68k/q800.c| 4 ++--
>
On 2/9/21 8:29 PM, Mark Cave-Ayland wrote:
> The value of dma_counter is set once at the start of the transfer and remains
> the same until the transfer is complete. This allows the check in
> esp_transfer_data
> to be simplified since dma_left will always be non-zero until the transfer is
> compl
The insn plugin has a simple heuristic to detect if an instruction is
detected running twice in a row. Check the plugin log after the run
and pass accordingly.
Signed-off-by: Alex Bennée
Message-Id: <20210209182749.31323-13-alex.ben...@linaro.org>
---
tests/acceptance/tcg_plugins.py | 31 +++
On 2/9/21 8:29 PM, Mark Cave-Ayland wrote:
> This simplifies reading the STC register value without having to manually
> shift
> each individual 8-bit value.
If possible repeat the subject so the sentence is easier to understand.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/scsi/esp.c | 15
From: Richard Henderson
Move the code from accel/tcg/translate-all.c to target/sh4/cpu.c.
Signed-off-by: Richard Henderson
Signed-off-by: Alex Bennée
Reviewed-by: Alex Bennée
Message-Id: <20210208233906.479571-5-richard.hender...@linaro.org>
Message-Id: <20210209182749.31323-5-alex.ben...@lin
On Mon, Feb 8, 2021 at 6:11 PM Alistair Francis
wrote:
>
> Signed-off-by: Alistair Francis
> Acked-by: Bin Meng
Thanks!
Applied to riscv-to-apply.next with the title fixed.
Alistair
> ---
> MAINTAINERS | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINE
On 2/10/21 10:58 AM, Nir Soffer wrote:
> On Tue, Feb 9, 2021 at 5:28 PM Eric Blake wrote:
>>
>> Our default of a backlog of 1 connection is rather puny; it gets in
>> the way when we are explicitly allowing multiple clients (such as
>> qemu-nbd -e N [--shared], or nbd-server-start with its default
From: Richard Henderson
This also means we don't need an extra declaration of
the structure in hw/core/cpu.h.
Signed-off-by: Richard Henderson
Signed-off-by: Alex Bennée
Reviewed-by: Alex Bennée
Message-Id: <20210208233906.479571-2-richard.hender...@linaro.org>
Message-Id: <20210209182749.313
On Wed, 10 Feb 2021 at 10:23, Bin Meng wrote:
>
> From: Bin Meng
>
> Current QEMU HEAD nvme.c does not compile:
>
> hw/block/nvme.c:3242:9: error: ‘result’ may be used uninitialized in this
> function [-Werror=maybe-uninitialized]
> trace_pci_nvme_getfeat_vwcache(result ? "enabled" :
On Tue, Feb 9, 2021 at 2:55 AM Bin Meng wrote:
>
> At the end of sdhci_send_command(), it starts a data transfer if
> the command register indicates a data is associated. However the
> data transfer should only be initiated when the command execution
> has succeeded.
>
> Cc: qemu-sta...@nongnu.org
From: Richard Henderson
Create a hook in which to split out the mips and
sh4 ifdefs from cpu_io_recompile.
[AJB: s/stoped/stopped/]
Signed-off-by: Richard Henderson
Signed-off-by: Alex Bennée
Reviewed-by: Alex Bennée
Message-Id: <20210208233906.479571-3-richard.hender...@linaro.org>
Message-
From: Richard Henderson
Move the code from accel/tcg/translate-all.c to target/mips/cpu.c.
Signed-off-by: Richard Henderson
Signed-off-by: Alex Bennée
Reviewed-by: Alex Bennée
Message-Id: <20210208233906.479571-4-richard.hender...@linaro.org>
Message-Id: <20210209182749.31323-4-alex.ben...@li
On 28.01.21 16:52, Peter Maydell wrote:
On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote:
With Apple Silicon available to the masses, it's a good time to add support
for driving its virtualization extensions from QEMU.
This patch adds all necessary architecture specific code to get basic V
A duplicate insn is one that is appears to be executed twice in a row.
This is currently possible due to -icount and cpu_io_recompile()
causing a re-translation of a block. On it's own this won't trigger
any tests though.
The heuristics that the plugin use can't deal with the x86 rep
instruction w
From: zhouyang
I am reading contrib related code and found some style problems while
check the code using checkpatch.pl. This commit fixs the issue below:
ERROR: space required after that ','
Signed-off-by: zhouyang
Signed-off-by: Alex Bennée
Message-Id: <20210118031004.1662363-5-zhouyang...@h
This may well end up being anonymous but it should always be unique.
Signed-off-by: Alex Bennée
Reviewed-by: Clement Deschamps
Reviewed-by: Emilio G. Cota
Reviewed-by: Richard Henderson
Message-Id: <20200713200415.26214-11-alex.ben...@linaro.org>
---
v4
- use g_intern_static_string for stat
When icount is enabled and we recompile an MMIO access we end up
double counting the instruction execution. To avoid this we introduce
the CF_NOINSTR cflag which disables instrumentation for the next TB.
As this is part of the hashed compile flags we will only execute the
generated TB while coming
There is no real need to use CF_NOCACHE here. As long as the TB isn't
linked to other TBs or included in the QHT or jump cache then it will
only get executed once.
Signed-off-by: Alex Bennée
Message-Id: <20210209182749.31323-10-alex.ben...@linaro.org>
---
accel/tcg/translate-all.c | 30 +
This is a plugin intended to help with profiling access to various
bits of system hardware. It only really makes sense for system
emulation.
It takes advantage of the recently exposed helper API that allows us
to see the device name (memory region name) associated with a device.
You can specify a
On Wed, Feb 10, 2021 at 03:31:57AM -0500,
"Michael S. Tsirkin" wrote:
> On Tue, Feb 09, 2021 at 12:02:58PM -0800, Isaku Yamahata wrote:
> > > > + * When the method of _CRS is called to determine MMCONFIG region,
> > > > + * only port io is allowed to access PCI configuration space.
> > >
Again there is no reason to jump through the nocache hoops to execute
a single instruction block. We do have to add an additional wrinkle to
the cpu_handle_interrupt case to ensure we let through a TB where we
have specifically disabled icount for the block.
As the last user of cpu_exec_nocache we
On Wed, Feb 10, 2021 at 04:39:06PM -0500, Michael S. Tsirkin wrote:
> On Mon, Jan 25, 2021 at 01:01:09PM -0500, Vivek Goyal wrote:
> > Hi,
> >
> > We are working on DAX support in virtiofs and have some patches out of
> > the tree hosted here.
> >
> > https://gitlab.com/virtio-fs/qemu/-/commits/v
From: zhouyang
I am reading contrib related code and found some style problems while
check the code using checkpatch.pl. This commit fixs the issue below:
ERROR: "foo * bar" should be "foo *bar"
Signed-off-by: zhouyang
Signed-off-by: Alex Bennée
Message-Id: <20210118031004.1662363-3-zhouyang..
Add AT24 EEPROM and temperature sensors for GSJ machine.
Reviewed-by: Doug Evans
Reviewed-by: Tyrong Ting
Signed-off-by: Hao Wu
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index be017b997a..4e6f4ffe90 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -370,6 +370,7 @@ config NPCM7XX
bool
A recent change to the handling of constants in TCG changed the
pattern of ops emitted for a constant add. We no longer emit a mov and
the constant can be applied directly to the TCG_op_add arguments. This
was causing SEGVs when running the insn plugin with arg=inline. Fix
this by updating copy_add
From: zhouyang
I am reading contrib related code and found some style problems while
check the code using checkpatch.pl. This commit fixs the issue below:
ERROR: spaces required around that '*'
Signed-off-by: zhouyang
Signed-off-by: Alex Bennée
Message-Id: <20210118031004.1662363-4-zhouyang...
Hi,
OK time to start preparing a plugins PR with all the accumulated fixes
over the last few months. Broadly they are:
- a new API for HW access profiling
- a bunch of style clean-ups
- a fix for a regression caused by recent TCG updates
- Richard's io_recompile clean-ups
- a fix for an
This patch implements the FIFO mode of the SMBus module. In FIFO, the
user transmits or receives at most 16 bytes at a time. The FIFO mode
allows the module to transmit large amount of data faster than single
byte mode.
Since we only added the device in a patch that is only a few commits
away in t
From: zhouyang
I am reading contrib related code and found some style problems while
check the code using checkpatch.pl. This commit fixs the misuse of
'#' flag of printf format
Signed-off-by: zhouyang
Signed-off-by: Alex Bennée
Message-Id: <20210118031004.1662363-2-zhouyang...@huawei.com>
---
From: zhouyang
I found some style problems whil check the code using checkpatch.pl.
This commit fixs the issue below:
ERROR: that open brace { should be on the previous line
Signed-off-by: zhouyang
Signed-off-by: Alex Bennée
Message-Id: <20210118031004.1662363-6-zhouyang...@huawei.com>
---
co
When viewing/debugging memory regions it is sometimes hard to figure
out which PCI device something belongs to. Make the names unique by
including the vdev name in the name string.
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Message-Id: <20200
This patch adds a QTest for NPCM7XX SMBus's single byte mode. It sends a
byte to a device in the evaluation board, and verify the retrieved value
is equivalent to the sent value.
Reviewed-by: Doug Evans
Reviewed-by: Tyrong Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
diff --git a/tests
This commit implements the single-byte mode of the SMBus.
Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses
compliant with SMBus and I2C protocol.
This patch implements the single-byte mode of the SMBus. In this mode,
the user sends or receives a byte each time. The SMBus device
Add I2C temperature sensors for NPCM750 eval board.
Reviewed-by: Doug Evans
Reviewed-by: Tyrong Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 3fdd5cab01..47a215bd01 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npc
This patch set implements the System manager bus (SMBus) module in NPCM7XX
SoC. Basically, it emulates the data transactions of the module, not the
SDA/SCL levels. We have also added a QTest which contains read and write
operations for both single-byte and FIFO mode, and added basic I2C devices
for
On Wed, Feb 10, 2021 at 02:37:31PM +0100,
Igor Mammedov wrote:
> On Tue, 9 Feb 2021 12:02:58 -0800
> Isaku Yamahata wrote:
>
> > On Tue, Feb 09, 2021 at 04:52:41PM +0100,
> > Igor Mammedov wrote:
> >
> > > On Mon, 8 Feb 2021 13:57:25 -0800
> > > isaku.yamah...@gmail.com wrote:
> > >
> > >
Hi Alistair,
thanks for your quick and helpful reply. :)
I'll see, if I can try them out on the weekend and will report my results.
Best regards and thanks again!
Pascal
On 08.02.21 23:49, Alistair Francis wrote:
> On Mon, Feb 8, 2021 at 12:00 PM Pascal Scholz
> wrote:
>> Hi all,
>>
>> I'm ho
On Mon, Feb 8, 2021 at 8:59 AM Peter Maydell
wrote:
> On Fri, 29 Jan 2021 at 01:04, Hao Wu wrote:
> >
> > This patch implements the FIFO mode of the SMBus module. In FIFO, the
> > user transmits or receives at most 16 bytes at a time. The FIFO mode
> > allows the module to transmit large amount
On Mon, Jan 25, 2021 at 01:01:09PM -0500, Vivek Goyal wrote:
> Hi,
>
> We are working on DAX support in virtiofs and have some patches out of
> the tree hosted here.
>
> https://gitlab.com/virtio-fs/qemu/-/commits/virtio-fs-dev
>
> These patches have not been proposed for merge yet, becasue Davi
On 28.01.21 16:28, Peter Maydell wrote:
On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote:
The hooks we have that call us after reset, init and loadvm really all
just want to say "The reference of all register state is in the QEMU
vcpu struct, please push it".
We already have a working push
Thanks. I'll take patch 1 out of the next version.
On Mon, Feb 8, 2021 at 9:01 AM Peter Maydell
wrote:
> On Fri, 29 Jan 2021 at 01:04, Hao Wu wrote:
> >
> > This patch set implements the System manager bus (SMBus) module in
> NPCM7XX
> > SoC. Basically, it emulates the data transactions of the
On Tue, Feb 9, 2021 at 5:28 PM Eric Blake wrote:
>
> This gives us better feature parity with QMP nbd-server-start, where
> max-connections defaults to 0 for unlimited.
Sound useful
> Signed-off-by: Eric Blake
> ---
> docs/tools/qemu-nbd.rst | 4 ++--
> qemu-nbd.c | 7 +++
> 2
On Tue, Feb 9, 2021 at 5:27 AM Peter Maydell
wrote:
> Add a clock_ns_to_ticks() function which does the opposite of
> clock_ticks_to_ns(): given a duration in nanoseconds, it returns the
> number of clock ticks that would happen in that time. This is useful
> for devices that have a free running
On Jan 27 14:15, Klaus Jensen wrote:
> From: Klaus Jensen
>
> For most commands, when issuing an AIO, the BlockAIOCB is stored in the
> NvmeRequest aiocb pointer when the AIO is issued. The purpose of storing
> this is to allow the AIO to be cancelled when deleting submission
> queues (it is curr
On Tue, Feb 9, 2021 at 5:21 AM Peter Maydell
wrote:
> Use the new clock_ns_to_ticks() function in npcm7xx_timer where
> appropriate.
>
> Signed-off-by: Peter Maydell
>
Reviewed-by: Hao Wu
Thanks!
> ---
> hw/timer/npcm7xx_timer.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>
On Feb 9 12:10, Philippe Mathieu-Daudé wrote:
> On 2/9/21 11:45 AM, Klaus Jensen wrote:
> > From: Gollu Appalanaidu
> >
> > Commit 6eb7a071292a ("hw/block/nvme: change controller pci id") changed
> > the controller to use a Red Hat assigned PCI Device and Vendor ID, but
> > did not change the IE
1 - 100 of 356 matches
Mail list logo
