Will do.
On Wed, 10 Feb 2021, 05:44 Thomas Huth, wrote:
> On 09/02/2021 21.37, Alex Bennée wrote:
> >
> > Thomas Huth writes:
> >
> >> Since Travis changed their policies, travis-ci.org will soon become
> >> completely useless for the QEMU project. We should now really make sure
> >> that we mo
From: Gollu Appalanaidu
Add support for marking blocks invalid with the Write Uncorrectable
command. Block status is tracked in a (non-persistent) bitmap that is
checked on all reads and written to on all writes. This is potentially
expensive, so keep Write Uncorrectable disabled by default.
Sig
From: Gollu Appalanaidu
Add the 'oncs' nvme device parameter to allow optional features to be
enabled/disabled explicitly. Since most of these are optional commands,
make the CSE log pages dynamic to account for the value of ONCS.
Signed-off-by: Gollu Appalanaidu
Signed-off-by: Klaus Jensen
--
From: Klaus Jensen
First, add support for toggling optional features through the new `oncs`
nvme device parameter.
Secondly, add support for the Write Uncorrectable command.
Gollu Appalanaidu (2):
hw/block/nvme: add oncs device parameter
hw/block/nvme: add write uncorrectable command
docs
On Feb 10 12:32, Keith Busch wrote:
> On Mon, Feb 08, 2021 at 08:08:17PM +0100, Klaus Jensen wrote:
> > On Feb 9 03:59, Keith Busch wrote:
> > > This whole implementation would be much simpler with the synchronous
> > > blk_flush() routine instead of the AIO equivalent. This is not really a
> > >
On 27/01/2021 12:28, Alexey Kardashevskiy wrote:
On 25/01/2021 21:23, Greg Kurz wrote:
On Sat, 23 Jan 2021 13:36:34 +1100
Alexey Kardashevskiy wrote:
On 23/01/2021 04:01, Greg Kurz wrote:
It is currently not possible to perform a strict boot from USB storage:
$ qemu-system-ppc64 -acc
On 2021/2/9 下午11:04, Michael S. Tsirkin wrote:
On Tue, Feb 09, 2021 at 02:51:05PM +, Daniel P. Berrangé wrote:
On Tue, Feb 09, 2021 at 09:34:20AM -0500, Michael S. Tsirkin wrote:
On Thu, Feb 04, 2021 at 10:29:12PM +0200, Yuri Benditovich wrote:
This set of patches introduces graceful swi
From: Bin Meng
At present the property of the serial node is
populated with value zero. U-Boot's ns16550 driver is not happy
about this, so let's fill in a meaningful value.
Signed-off-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1612362288-22216-2-git-send-email-bmeng...@gm
From: Cédric Le Goater
The memory layout of the PowerNV machine is defined as :
#define KERNEL_LOAD_BASE ((void *)0x2000)
#define KERNEL_LOAD_SIZE 0x0800
#define INITRAMFS_LOAD_BASE KERNEL_LOAD_BASE + KERNEL_LOAD_SIZE
#define INITRAMFS_LOAD_SIZE 0x0800
#defi
From: Bin Meng
Per EREF 2.0 [1] chapter 3.11.2:
The following bits in L2CSR0 (exists in the e500mc/e5500/e6500 core):
- L2FI (L2 cache flash invalidate)
- L2FL (L2 cache flush)
- L2LFC (L2 cache lock flash clear)
when set, a cache operation is initiated by hardware, and these bits
will be cl
From: Cédric Le Goater
This to map the PNOR from the machine init handler directly and finish
the cleanup of the LPC model.
Signed-off-by: Cédric Le Goater
Message-Id: <20210126171059.307867-8-...@kaod.org>
Reviewed-by: Joel Stanley
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 11 +
From: Cédric Le Goater
The PowerNV machine can be run with an external IPMI BMC device
connected to a remote QEMU machine acting as BMC, using these options :
-chardev socket,id=ipmi0,host=localhost,port=9002,reconnect=10 \
-device ipmi-bmc-extern,id=bmc0,chardev=ipmi0 \
-device isa-ipmi-b
From: Daniel Henrique Barboza
We'll need to check the initial value given to spapr->gpu_numa_id when
building the rtas DT, so put it in a helper for easier access and to
avoid repetition.
Tested-by: Cédric Le Goater
Reviewed-by: Greg Kurz
Signed-off-by: Daniel Henrique Barboza
Message-Id: <20
From: Bin Meng
Per MPC8548ERM [1] chapter 14.5.3.4.1:
When RCTRL.RSF is 1, frames less than 64 bytes are accepted upon
a DA match. But currently QEMU does the opposite. This commit
reverses the RCTRL.RSF testing logic to match the manual.
Due to the reverse of the logic, certain guests may pote
From: Cédric Le Goater
On POWER9 systems, PHB controllers signal the XIVE interrupt controller
of a source interrupt notification using a store on a MMIO region. Add
traces for such events.
Signed-off-by: Cédric Le Goater
Message-Id: <20210126171059.307867-2-...@kaod.org>
Signed-off-by: David G
From: Cédric Le Goater
On PowerNV systems, the BMC is in charge of mapping the PNOR contents
on the LPC FW address space using the HIOMAP protocol. Under QEMU, we
emulate this behavior and we also add an extra control on the flash
accesses by letting the HIOMAP command handler decide whether the
From: Bin Meng
At present the platform clock frequency is using a magic number.
Convert it to a macro and use it everywhere.
Signed-off-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1612362288-22216-1-git-send-email-bmeng...@gmail.com>
Signed-off-by: David Gibson
---
hw/ppc/
From: Daniel Henrique Barboza
The current logic for calculating 'maxdomain' making it a sum of
numa_state->num_nodes with spapr->gpu_numa_id. spapr->gpu_numa_id is
used as a index to determine the next available NUMA id that a
given NVGPU can use.
The problem is that the initial value of gpu_num
From: Cédric Le Goater
ENDs allocated by OPAL for the HW thread VPs are tagged as owned by FW.
Dump the state in 'info pic'.
Signed-off-by: Cédric Le Goater
Message-Id: <20210126171059.307867-3-...@kaod.org>
Signed-off-by: David Gibson
---
hw/intc/xive.c | 3 ++-
include/hw/ppc/xi
From: Daniel Henrique Barboza
This function is used only in spapr_numa.c.
Tested-by: Cédric Le Goater
Reviewed-by: Greg Kurz
Signed-off-by: Daniel Henrique Barboza
Message-Id: <20210128174213.1349181-2-danielhb...@gmail.com>
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 9 ---
From: Cédric Le Goater
The current settings are useful to load large kernels (with debug) but
it moves the initrd image in a memory region not protected by
skiboot. If skiboot is compiled with DEBUG=1, memory poisoning will
corrupt the initrd.
Cc: Murilo Opsfelder Araujo
Signed-off-by: Cédric L
From: Cédric Le Goater
and reuse pnv_bmc_set_pnor() to share the setting of the PNOR.
Signed-off-by: Cédric Le Goater
Message-Id: <20210126171059.307867-5-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_bmc.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/h
From: Philippe Mathieu-Daudé
Remove these confusing and unused definitions.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210127232401.3525126-1-f4...@amsat.org>
Signed-off-by: David Gibson
---
target/ppc/cpu.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/ppc/cpu.h b/ta
From: Daniel Henrique Barboza
Next patch will use the 'nodename' string in spapr_core_dt_populate()
after the point it's being freed today.
Instead of moving 'g_free(nodename)' around, let's do a QoL change in
both CPU DT functions where 'nodename' is being freed, and use
g_autofree to avoid the
From: Greg Kurz
It is currently not possible to perform a strict boot from USB storage:
$ qemu-system-ppc64 -accel kvm -nodefaults -nographic -serial stdio \
-boot strict=on \
-device qemu-xhci \
-device usb-storage,drive=disk,bootindex=0 \
-blockdev driver=file,n
From: Daniel Henrique Barboza
In the CPU hotunplug bug [1] the guest kernel throws a scary
message in dmesg:
pseries-hotplug-cpu: Failed to offline CPU , rc: -16
The reason isn't related to the bug though. This happens because the
kernel file arch/powerpc/platform/pseries/hotplug-cpu.c, functio
The following changes since commit 1214d55d1c41fbab3a9973a05085b8760647e411:
Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into
staging (2021-02-09 13:24:37 +)
are available in the Git repository at:
https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.0-20210210
On the hppa target userspace binaries may call signalfd4() and
eventfd2() with an old TARGET_O_NONBLOCK value of 00024 instead of
00020 for the "mask" syscall parameter, in which case the current
emulation doesn't handle the translation to the native O_NONBLOCK value
correctly.
The 0x04 bi
On 2/9/21 8:39 PM, Dmitry Fomichev wrote:
> On Mon, 2021-02-08 at 09:25 +0100, Klaus Jensen wrote:
>> From: Klaus Jensen
>>
>> The Zone Append Size Limit (ZASL) must be at least 4096 bytes, so
>> improve the user experience by adding an early parameter check in
>> nvme_check_constraints.
>>
>> Whe
On 2021/2/9 下午11:02, Eugenio Perez Martin wrote:
On Thu, Feb 4, 2021 at 4:27 AM Jason Wang wrote:
On 2021/2/2 下午6:08, Eugenio Perez Martin wrote:
On Mon, Feb 1, 2021 at 7:29 AM Jason Wang wrote:
On 2021/1/30 上午4:54, Eugenio Pérez wrote:
Shadow virtqueue notifications forwarding is disabl
On 2021/2/9 下午11:35, Eugenio Perez Martin wrote:
On Fri, Feb 5, 2021 at 4:52 AM Jason Wang wrote:
On 2021/2/4 下午5:25, Eugenio Perez Martin wrote:
On Thu, Feb 4, 2021 at 4:14 AM Jason Wang wrote:
On 2021/2/2 下午6:17, Eugenio Perez Martin wrote:
On Tue, Feb 2, 2021 at 4:31 AM Jason Wang wr
On 09/02/2021 21.37, Alex Bennée wrote:
Thomas Huth writes:
Since Travis changed their policies, travis-ci.org will soon become
completely useless for the QEMU project. We should now really make sure
that we move the remaining tests as good as possible to the gitlab-CI
instead.
Queued to te
On Sat, Jan 23, 2021 at 05:24:22PM -1000, Richard Henderson wrote:
> Use the cs_base field, because it happens to be the same
> size as hflags (and MSR, from which hflags is derived).
>
> In translate, extract most bits from a local hflags variable.
> Mark several cases where code generation is *n
On 2021/2/9 上午2:26, Peter Xu wrote:
Kevin,
On Mon, Feb 08, 2021 at 07:03:08AM +, Tian, Kevin wrote:
It really depends on the definition of dev-iotlb in this context. To me the
fact that virtio-iommu needs to notify the kernel for updating split cache
is already sort of dev-iotlb semantics
On Wed, Feb 10, 2021 at 10:10:21AM +0800, Bin Meng wrote:
> From: Bin Meng
>
> Per MPC8548ERM [1] chapter 14.5.3.4.1:
>
> When RCTRL.RSF is 1, frames less than 64 bytes are accepted upon
> a DA match. But currently QEMU does the opposite. This commit
> reverses the RCTRL.RSF testing logic to mat
On Mon, Feb 08, 2021 at 08:08:17PM +0100, Klaus Jensen wrote:
> On Feb 9 03:59, Keith Busch wrote:
> > This whole implementation would be much simpler with the synchronous
> > blk_flush() routine instead of the AIO equivalent. This is not really a
> > performant feature, so I don't think it's crit
From: Bin Meng
Per EREF 2.0 [1] chapter 3.11.2:
The following bits in L2CSR0 (exists in the e500mc/e5500/e6500 core):
- L2FI (L2 cache flash invalidate)
- L2FL (L2 cache flush)
- L2LFC (L2 cache lock flash clear)
when set, a cache operation is initiated by hardware, and these bits
will be cl
On Thu, Feb 4, 2021 at 10:25 AM Doug Evans wrote:
> On Thu, Feb 4, 2021 at 2:03 AM Daniel P. Berrangé
> wrote:
>
>> On Wed, Feb 03, 2021 at 03:35:36PM -0800, dje--- via wrote:
>> > Add support for ipv6 host forwarding
>> >
>> > This patchset takes the original patch from Maxim,
>> > https://www.
Hi David,
On Wed, Feb 10, 2021 at 10:09 AM David Gibson
wrote:
>
> On Wed, Feb 10, 2021 at 09:53:53AM +0800, Bin Meng wrote:
> > Hi David,
> >
> > On Wed, Feb 10, 2021 at 9:50 AM David Gibson
> > wrote:
> > >
> > > On Mon, Feb 08, 2021 at 05:40:58PM +0800, Bin Meng wrote:
> > > > From: Bin Meng
From: Bin Meng
Per MPC8548ERM [1] chapter 14.5.3.4.1:
When RCTRL.RSF is 1, frames less than 64 bytes are accepted upon
a DA match. But currently QEMU does the opposite. This commit
reverses the RCTRL.RSF testing logic to match the manual.
Due to the reverse of the logic, certain guests may pote
On Wed, Feb 10, 2021 at 09:53:53AM +0800, Bin Meng wrote:
> Hi David,
>
> On Wed, Feb 10, 2021 at 9:50 AM David Gibson
> wrote:
> >
> > On Mon, Feb 08, 2021 at 05:40:58PM +0800, Bin Meng wrote:
> > > From: Bin Meng
> > >
> > > There are several bits in L2CSR0 (exists in the e500mc/e5500/e6500
>
Hi David,
On Wed, Feb 10, 2021 at 9:50 AM David Gibson
wrote:
>
> On Mon, Feb 08, 2021 at 05:40:58PM +0800, Bin Meng wrote:
> > From: Bin Meng
> >
> > There are several bits in L2CSR0 (exists in the e500mc/e5500/e6500
> > core) that should be self-cleared when written:
> >
> > - L2FI (L2 cache
On Mon, Feb 08, 2021 at 05:40:58PM +0800, Bin Meng wrote:
> From: Bin Meng
>
> There are several bits in L2CSR0 (exists in the e500mc/e5500/e6500
> core) that should be self-cleared when written:
>
> - L2FI (L2 cache flash invalidate)
> - L2FL (L2 cache flush)
> - L2LFC (L2 cache lock flash cl
Hi David, Peter,
On Wed, Feb 10, 2021 at 9:16 AM David Gibson
wrote:
>
> On Tue, Feb 09, 2021 at 09:48:18AM +, Peter Maydell wrote:
> > On Tue, 9 Feb 2021 at 01:22, Bin Meng wrote:
> > >
> > > From: Bin Meng
> > >
> > > Per MPC8548ERM [1] chapter 14.5.3.4.1:
> > >
> > > When RCTRL.RSF is 1,
Kindly ping.
Any comments and reviews are wellcome :)
Thanks,
Jiahui
On 2021/2/5 18:13, Jiahui Cen wrote:
> A VM in the cloud environment may use a virutal disk as the backend storage,
> and there are usually filesystems on the virtual block device. When backend
> storage is temporarily down, any
On Tue, Feb 09, 2021 at 10:32:33PM +0100, Eric Auger wrote:
> Previous work on dev-iotlb message broke spapr_iommu/vhost integration
> as it did for SMMU and virtio-iommu. The spapr_iommu currently
> only sends IOMMU_NOTIFIER_UNMAP notifications. Since commit
> 958ec334bca3 ("vhost: Unbreak SMMU an
On Tue, Feb 09, 2021 at 09:48:18AM +, Peter Maydell wrote:
> On Tue, 9 Feb 2021 at 01:22, Bin Meng wrote:
> >
> > From: Bin Meng
> >
> > Per MPC8548ERM [1] chapter 14.5.3.4.1:
> >
> > When RCTRL.RSF is 1, frames less than 64 bytes are accepted upon
> > a DA match. But currently QEMU does the
On Sun, Feb 7, 2021 at 11:11 PM Bin Meng wrote:
>
> At present when building qemu-ppce500 the following warnings are seen:
>
> = WARNING ==
> This board does not use CONFIG_DM. CONFIG_DM will be
> compulsory starting with the v2020.01 release.
> Failure to u
Use the now-saved PAGE_ANON and PAGE_MTE bits,
and the per-page saved data.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/mte_helper.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/target/arm/mte_helper.c b/target
The real kernel collects _TIF_MTE_ASYNC_FAULT into the current thread's
state on any kernel entry (interrupt, exception etc), and then delivers
the signal in advance of resuming the thread.
This means that while the signal won't be delivered immediately, it will
not be delayed forever -- at minimu
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/mte.h | 60 +++
tests/tcg/aarch64/mte-1.c | 28 +++
tests/tcg/aarch64/mte-2.c | 45 +++
tests/tcg/aarch64/mte-3.c | 51 +
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 761f0c61bd..929de1071b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -209,6 +209,21 @@ static
This is the prctl bit that controls whether syscalls accept tagged
addresses. See Documentation/arm64/tagged-address-abi.rst in the
linux kernel.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_syscall.h | 4
target/arm/cpu-param.h |
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_signal.h | 2 ++
linux-user/aarch64/cpu_loop.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/linux-user/aarch64/target_signal.h
b/linux-user/aarch64/target_signal.h
index ddd73169f0..777fb66
Use simple arithmetic instead of a conditional
move when tbi0 != tbi1.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/a
A proper syndrome is required to fill in the proper si_code.
Use page_get_flags to determine permission vs translation for user-only.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/aarch64/cpu_loop.c | 24 +---
target/arm/tlb_helper.c | 15 +
These prctl fields are required for the function of MTE.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_syscall.h | 9 ++
linux-user/syscall.c| 43 +
2 files changed, 52 insertions(+)
diff --git a/linux
Move everything related to syndromes to a new file,
which can be shared with linux-user.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 245 +---
target/arm/syndrome.h | 273 +
2 f
Remember the PROT_MTE bit as PAGE_MTE/PAGE_TARGET_2.
Otherwise this does not yet have effect.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h| 1 +
linux-user/syscall_defs.h | 1 +
target/arm/cpu.h | 1 +
linux-user/mmap.c | 22
We were fudging TBI1 enabled to speed up the generated code.
Now that we've improved the code generation, remove this.
Also, tidy the comment to reflect the current code.
The pauth test was testing a kernel address (-1) and making
incorrect assumptions about TBI1; stick to userland addresses.
Rev
The places that use these are better off using untagged
addresses, so do not provide a tagged versions. Rename
to make it clear about the address type.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 4 ++--
linux-user/qemu.h | 4 ++--
accel/tc
Resolve the untagged address once, using thread_cpu.
Tidy the DEBUG_REMAP code using glib routines.
Signed-off-by: Richard Henderson
---
linux-user/uaccess.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/linux-user/uaccess.c b/linux-user/uacces
Use g2h_untagged in contexts that have no cpu, e.g. the binary
loaders that operate before the primary cpu is created. As a
colollary, target_mmap and friends must use untagged addresses,
since they are used by the loaders.
Use g2h_untagged on values returned from target_mmap, as the
kernel never
For copy_*_user, only 0 and -TARGET_EFAULT are returned; no need
to involve abi_long. Use size_t for lengths. Use bool for the
lock_user copy argument. Use ssize_t for target_strlen, because
we can't overflow the host memory space.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
-
We must always use GUEST_ADDR_MAX, because even 32-bit hosts can
use -R to restrict the memory address of the guest.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/include/exec
These functions are not small, except for unlock_user
without debugging enabled. Move them out of line, and
add missing braces on the way.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/qemu.h| 45 ++-
linux-user/uaccess.c
These constants are only ever used with access_ok, and friends.
Rather than translating them to PAGE_* bits, let them equal
the PAGE_* bits to begin.
Reviewed-by: Warner Losh
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
bsd-user/qemu.h | 9 -
1 file changed, 4 insert
Provide an identity fallback for target that do not
use tagged addresses.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index e62f4fba00..d9dc1d
We define target_mmap et al as untagged, so that they can be
used from the binary loaders. Explicitly call cpu_untagged_addr
for munmap, mprotect, mremap syscall entry points.
Add a few comments for the syscalls that are exempted by the
kernel's tagged-address-abi.rst.
Reviewed-by: Peter Maydell
Provide both tagged and untagged versions of access_ok.
In a few places use thread_cpu, as the user is several
callees removed from do_syscall1.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/qemu.h | 11 +--
linux-user/elfload.c | 2 +-
linux
Changes for v6:
* Drop the change to probe_access. The cpu_untagged_addr function
isn't correct, since that's specifically for syscalls. The uses
of probe_access in target/arm/ are already done with clean addresses.
* Move unlock_user comparison change from p19 to p18.
The only unrev
This is the only use of guest_addr_valid that does not begin
with a guest address, but a host address being transformed to
a guest address.
We will shortly adjust guest_addr_valid to handle guest memory
tags, and the host address should not be subjected to that.
Move h2g_valid adjacent to the oth
Verify that addr + size - 1 does not wrap around.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/qemu.h | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index 17aa992165..441ba6a78b 100644
--
We're currently open-coding the range check in access_ok;
use guest_range_valid when size != 0.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/qemu.h | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
in
This is more descriptive than 'unsigned long'.
No functional change, since these match on all linux+bsd hosts.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/cpu_ldst.
Return bool not int; pass abi_ulong not 'unsigned long'.
All callers use abi_ulong already, so the change in type
has no effect.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/ex
These constants are only ever used with access_ok, and friends.
Rather than translating them to PAGE_* bits, let them equal
the PAGE_* bits to begin.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/qemu.h | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
This is more descriptive than 'unsigned long'.
No functional change, since these match on all linux+bsd hosts.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 2 +-
bsd-user/main.c| 4 ++--
linux-user/elfload.c | 4 ++--
linux-user/main.c
This data can be allocated by page_alloc_target_data() and
released by page_set_flags(start, end, prot | PAGE_RESET).
This data will be used to hold tag memory for AArch64 MTE.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h| 42 ++
Record whether the backing page is anonymous, or if it has file
backing. This will allow us to get close to the Linux AArch64
ABI for MTE, which allows tag memory only on ram-backed VMAs.
The real ABI allows tag memory on files, when those files are
on ram-backed filesystems, such as tmpfs. We w
On Tue, Feb 09, 2021 at 03:04:05PM -0600, Babu Moger wrote:
> Adds the support for AMD 3rd generation processors. The model
> display for the new processor will be EPYC-Milan.
>
> Adds the following new feature bits on top of the feature bits from
> the first and second generation EPYC models.
>
> On Feb 9, 2021, at 4:53 PM, Ben Widawsky wrote:
>
> A couple of high level comments below. Overall your approach was what I had
> imagined originally. The approach Jonathan took is likely more versatile (but
> harder to read, for sure).
>
> I'm fine with either and I hope you two can come t
On Tue, Feb 09, 2021 at 10:32:31PM +0100, Eric Auger wrote:
> 958ec334bca3 ("vhost: Unbreak SMMU and virtio-iommu on dev-iotlb
> support") fixed part of the UNMAP related regressions introduced by
> b68ba1ca5767 ("memory: Add IOMMU_NOTIFIER_DEVIOTLB_UNMAP
> IOMMUTLBNotificationType").
>
> However
No consensus yet but I’d suggest that we’ll do the QEMU work and Jonathan
focuses
on the linux kernel and UEFI/edk2 and CXL SSWG efforts. Seems like
a way to maximize resources and everyone’s contribution and expertise. QEMU
part
requires the least expertise which is why we’re best suited for
Am 09.02.21 um 22:15 schrieb Stefan Weil:
Thanks for solving this. The patch works for me.
BIOS boot time with qemu-system-i386 is about 41 s (with my code which
lacks thread support and ffi it was 40 s).
With qemu-system-x86_64 it is twice as fast, so it looks like in my
last report where
A couple of high level comments below. Overall your approach was what I had
imagined originally. The approach Jonathan took is likely more versatile (but
harder to read, for sure).
I'm fine with either and I hope you two can come to an agreement on what the
best way forward is.
My ultimate goal w
Have you/Jonathan come to consensus about which implementation is going forward?
I'd rather not have to review two :D
On 21-02-09 15:35:49, Chris Browy wrote:
> ---
> MAINTAINERS | 7 +
> hw/pci/meson.build| 1 +
> hw/pci/pcie.c
Previous work on dev-iotlb message broke spapr_iommu/vhost integration
as it did for SMMU and virtio-iommu. The spapr_iommu currently
only sends IOMMU_NOTIFIER_UNMAP notifications. Since commit
958ec334bca3 ("vhost: Unbreak SMMU and virtio-iommu on dev-iotlb support"),
VHOST first tries to register
958ec334bca3 ("vhost: Unbreak SMMU and virtio-iommu on dev-iotlb
support") fixed part of the UNMAP related regressions introduced by
b68ba1ca5767 ("memory: Add IOMMU_NOTIFIER_DEVIOTLB_UNMAP
IOMMUTLBNotificationType").
However the case of the spapr_iommu was not addressed. It should be
identical to
In an attempt to fix smmu/virtio-iommu - vhost regression, commit
958ec334bca3 ("vhost: Unbreak SMMU and virtio-iommu on dev-iotlb support")
broke virtio-iommu integration. This is due to the fact VFIO registers
IOMMU_NOTIFIER_ALL notifiers, which includes IOMMU_NOTIFIER_DEVIOTLB_UNMAP
and this lat
Adds the support for AMD 3rd generation processors. The model
display for the new processor will be EPYC-Milan.
Adds the following new feature bits on top of the feature bits from
the first and second generation EPYC models.
pcid : Process context identifiers support
ibrs : Indi
Am 09.02.21 um 21:46 schrieb Richard Henderson:
On 2/8/21 2:55 PM, Richard Henderson wrote:
Ok, I've reproduced something on a T3 (gcc102.fsffrance.org).
Running the same code side-by-side vs the T5, I get different results.
Brown paper bag time: the T5 build dir lost the --enable-tcg-interpre
** Tags added: gdbstub
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1625216
Title:
memory writes via gdb don't work for memory mapped hardware
Status in QEMU:
Confirmed
Bug description:
When
On 2/9/21 10:27 AM, Alex Bennée wrote:
> When icount is enabled and we recompile an MMIO access we end up
> double counting the instruction execution. To avoid this we introduce
> the CF_NOINSTR cflag which disables instrumentation for the next TB.
> As this is part of the hashed compile flags we w
On 2/9/21 10:27 AM, Alex Bennée wrote:
> Now we no longer generate CF_NOCACHE blocks we can remove a bunch of
> the special case handling for them. While we are at it we can remove
> the unused tb->orig_tb field and save a few bytes on the TB structure.
>
> Signed-off-by: Alex Bennée
> ---
> inc
Richard Henderson writes:
> On 2/9/21 10:27 AM, Alex Bennée wrote:
>> /* Refill decrementer and continue execution. */
>> -insns_left = MIN(0x, cpu->icount_budget);
>> +insns_left = MIN(CF_COUNT_MASK, cpu->icount_budget);
> ...
>> +g_assert(insns_left < CF_COUNT_MASK);
Peter Maydell writes:
> We used to make a distinction between 'float64'/'float32' types and
> the 'uint64_t'/'uint32_t' types, requiring special conversion
> operations to go between them. We've now dropped this distinction as
> unnecessary, and the 'float*' types remain primarily for
> docume
Richard Henderson writes:
> On 2/9/21 10:27 AM, Alex Bennée wrote:
>> A duplicate insn is one that is appears to be executed twice in a row.
>> This is currently possible due to -icount and cpu_io_recompile()
>> causing a re-translation of a block. On it's own this won't trigger
>> any tests th
On 2/8/21 2:55 PM, Richard Henderson wrote:
> Ok, I've reproduced something on a T3 (gcc102.fsffrance.org).
> Running the same code side-by-side vs the T5, I get different results.
Brown paper bag time: the T5 build dir lost the --enable-tcg-interpreter flag,
so was testing tcg native.
Big-endian
---
MAINTAINERS | 7 +
hw/pci/meson.build| 1 +
hw/pci/pcie.c | 2 +-
hw/pci/pcie_doe.c | 414 ++
include/hw/pci/pci_ids.h | 2 +
include/h
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