Public bug reported:
I got the following error when I ran qemu on arm mac(MacOS 11.2).
```
$ ./qemu-system-x86_64
qemu-system-x86_64: qemu_mprotect__osdep: mprotect failed: Permission denied
**
ERROR:../tcg/tcg.c:844:tcg_region_init: assertion failed: (!rc)
Bail out! ERROR:../tcg/tcg.c:844:tcg_re
This patch supports Namespace Attachment command for the pre-defined
nvme-ns device nodes. Of course, attach/detach namespace should only be
supported in case 'subsys' is given. This is because if we detach a
namespace from a controller, somebody needs to manage the detached, but
allocated namesp
This patch has no functional changes. This patch just refactored
nvme_select_ns_iocs() to iterate the attached namespaces of the
controlller and make it invoke __nvme_select_ns_iocs().
Signed-off-by: Minwoo Im
---
hw/block/nvme.c | 36 +---
1 file changed, 21 ins
>From NVMe spec 1.4b "6.1.5. NSID and Namespace Relationships" defines
valid namespace types:
- Unallocated: Not exists in the NVMe subsystem
- Allocated: Exists in the NVMe subsystem
- Inactive: Not attached to the controller
- Active: Attached to the controller
T
Expand allocated namespace list (subsys->namespaces) to have 256 entries
which is a value lager than at least NVME_MAX_NAMESPACES which is for
attached namespace list in a controller.
Allocated namespace list should at least larger than attached namespace
list.
n->num_namespaces = NVME_MA
Given that now we have nvme-subsys device supported, we can manage
namespace allocated, but not attached: detached. This patch introduced
a parameter for nvme-ns device named 'detached'. This parameter
indicates whether the given namespace device is detached from
a entire NVMe subsystem('subsys'
subsys->namespaces array used to be sized to NVME_SUBSYS_MAX_NAMESPACES.
But subsys->namespaces are being accessed with 1-based namespace id
which means the very first array entry will always be empty(NULL).
Signed-off-by: Minwoo Im
---
hw/block/nvme-subsys.h | 2 +-
1 file changed, 1 insertion(
Hello,
This series supports namespace attachment: attach and detach. It means
that this series also introduced a scheme for allocated namespace which
is detached, but allocated in a NVMe subsystem. Given that now we have
nvme-subsys device to specify a NVMe subsystem, it can manage detached
name
From: Claudio Fontana
add a new optional interface to CPUClass, which allows accelerators
to extend the CPUClass with additional accelerator-specific
initializations.
This will allow to separate the target cpu code that is specific
to each accelerator, and register it automatically with object
h
From: Claudio Fontana
This will allow us to centralize the registration of
the cpus.c module accelerator operations (in accel/accel-softmmu.c),
and trigger it automatically using object hierarchy lookup from the
new accel_init_interfaces() initialization step, depending just on
which accelerators
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
[claudio: rebased on Richard's splitwx work]
Signed-off-by: Claudio Fontana
Message-Id: <20210204163931.7358-17-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/boards.h| 2 +-
i
From: Claudio Fontana
cpu_check_watchpoint, watchpoint_address_matches are TCG-only.
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Message-Id: <20210204163931.7358-13-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
softmmu/physmem.c | 141 +++-
From: Claudio Fontana
commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs")
introduced this ARM-specific, TCG-specific hack to adjust the address,
before checking it with cpu_check_watchpoint.
Make adjust_watchpoint_address optional and move it to tcg_ops.
Signed-off-by: Clau
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20210204163931.7358-8-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c
From: Claudio Fontana
commit 568496c0c0f1 ("cpu: Add callback to check architectural") and
commit 3826121d9298 ("target-arm: Implement checking of fired")
introduced an ARM-specific hack for cpu_check_watchpoint.
Make debug_check_watchpoint optional, and move it to tcg_ops.
Signed-off-by: Claud
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20210204163931.7358-10-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c| 4 ++--
target
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped target code in CONFIG_TCG, reworded comments]
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Message-Id: <20210204163931.7358-5-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 2
From: Claudio Fontana
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
[claudio: make the field presence in cpu.h unconditional, removing the ifdefs]
Message-Id: <20210204163931.7358
From: Eduardo Habkost
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Eduardo Habkost
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20210204163931.7358-7-cfont...@suse.de>
Signed-off-by: Ri
Trivially implemented like other arithmetic.
Tested via check-tcg and the ppc64 target.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 4 ++--
tcg/tci.c| 28 ++--
tcg/tci/tcg-target.c.inc
From: Claudio Fontana
cc->do_interrupt is in theory a TCG callback used in accel/tcg only,
to prepare the emulated architecture to take an interrupt as defined
in the hardware specifications,
but in reality the _do_interrupt style of functions in targets are
also occasionally reused by KVM to pr
From: Claudio Fontana
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.
Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations i
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20210204163931.7358-6-cfont...@suse.de>
Signed-off-by: Ric
From: Eduardo Habkost
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded
From: Claudio Fontana
move away TCG-only code, make it compile only on TCG.
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
[claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h]
Signed-off-by: Claudio Fontana
Message-Id: <20210204163931.7358-4-cfont...@suse.de>
Signed-o
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
[claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY]
avoiding its use in headers used by common_ss code (should be poisoned).
Note
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 8
1 file changed, 8 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 5c84a1c979..e0d815e4b2 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -33,14 +33,6 @@
#include "tcg/tcg-op.h"
#inclu
As noted in several comments, 8 regs is not enough for 32-bit
to perform calls, as currently implemented. Shortly, we will
rearrange the encoding which will make 32 regs impossible.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 32 +---
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 6819c97792..fe935e71a3 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -618,7 +618,7 @@ uintptr_t QEMU_
From: Claudio Fontana
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.
Signed-off-by: Claudio Fontana
Reviewed-by: Alistair Francis
Reviewed-by: Alex Bennée
Message-Id: <20210204163931.7358-3-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
target
Three TODO instances are never happen cases.
Other uses of tcg_abort are also indicating unreachable cases.
Tested-by: Alex Bennée
Reviewed-by: Stefan Weil
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 15 +++
1 file changed, 7 insertions(+), 8 deletion
Restrict all operands to registers. All constants will be forced
into registers by the middle-end. Removing the difference in how
immediate integers were encoded will allow more code to be shared
between 32-bit and 64-bit operations.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
--
Eliminating a TODO for ld16s_i64.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index b64d611ec9..259a8538bf 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@
This was removed from tcg_target_reg_alloc_order and
tcg_target_call_iarg_regs on the assumption that it
was the stack. This was incorrectly copied from i386.
For tci, the stack is R15.
By adding R4 back to tcg_target_call_iarg_regs, adjust the other
entries so that 6 (or 12) entries are still pr
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index ee2cd7dfa2..eb70672efb 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -625,6 +625,7 @@ uintptr_t QEMU_D
We do not simultaneously support div and div2 -- it's one
or the other. TCI is already using div, so remove div2.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c| 12
tcg/tci/tcg-target.c.inc | 8
2 files ch
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 0f56702b93..7e108bcbb3 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -455,6 +455,18 @@
The existing check was incomplete:
(1) Only applied to two of the 7 stores, and not to the loads at all.
(2) Only checked the upper, but not the lower bound of the stack.
Doing this at compile time means that we don't need to do it
at runtime as well.
Tested-by: Alex Bennée
Reviewed-by: Alex Ben
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 55863f76a7..6819c97792 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -612,7 +612,7 @@ uintptr_t QEMU_
Eliminating a TODO for ld16u_i32.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index c31be1a1f4..b64d611ec9 100644
--- a/tcg/tci.c
+++ b/tcg
Note that we had two functions of the same name: a 32-bit version
which took two register numbers and a 64-bit version which was a
no-op wrapper for tcg_write_reg. After this, we are left with
only the 32-bit version.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Hender
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 259a8538bf..55863f76a7 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -606,6 +606,7 @@ uintptr_t QEMU_D
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index e8023b5384..740244cc54 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,11 +117,6 @@ tci_write_re
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 740244cc54..005d2946c4 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,14 +117,6 @@ tci_write_r
For a 64-bit TCI, the upper bits of a 32-bit operation are
undefined (much like a native ppc64 32-bit operation). It
simplifies everything if we don't force-extend the result.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 66 +
Eliminating a TODO for ld8s_i32.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 7e108bcbb3..c31be1a1f4 100644
--- a/tcg/tci.c
+++ b/tcg/
Each thread must have its own pc, even under TCI.
Remove the GETPC ifdef, because GETPC is always available for
helpers, and thus is always required. Move the assignment
under INDEX_op_call, because the value is only visible when
we make a call to a helper function.
Reviewed-by: Alex Bennée
Sig
From: Stefan Weil
That TCG opcode is used by debian-buster (arm64) running ffmpeg:
qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reported-by: Alex Bennée
Signed-off-by: Stefan Weil
Message-Id: <20210128024814.2056958-1...@weilnetz
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index c3a8511dfe..e8023b5384 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,14 +117,6 @@ tci_write_r
Fixes INDEX_op_rotli_vec for aarch64 host, where the 3rd
argument is an integer, not a temporary, which now tickles
an assert added in e89b28a6350.
Previously, the value computed into v2 would be garbage for
rotli_vec, but as the value was unused it caused no harm.
Signed-off-by: Richard Henderso
The configure option was backward, and we failed to
pass the value on to meson.
Fixes: 23a77b2d18b ("build-system: clean up TCG/TCI configury")
Tested-by: Stefan Weil
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Philippe Mathieu-Da
From: Philippe Mathieu-Daudé
The code is currently comparing c2 to the type promotion of
uint32_t and int32_t. That is, the conversion rules are as:
(common_type) c2 == (common_type) (uint32_t)
(is_unsigned
? (uint32_t)c2
From: Stefan Weil
That TCG opcode is used by debian-buster (arm64) running ffmpeg:
qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reported-by: Alex Bennée
Signed-off-by: Stefan Weil
Message-Id: <20210128020425.2055454-1...@weilnetz
From: Philippe Mathieu-Daudé
"exec/cpu-defs.h" contains generic CPU definitions for the
TCG frontends (mostly related to TLB). TCG backends definitions
aren't relevant here.
See tcg/README description:
4) Backend
tcg-target.h contains the target specific definitions. tcg-target.c.inc
con
The following changes since commit d0dddab40e472ba62b5f43f11cc7dba085dabe71:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2021-02-05 15:27:02 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210205
On Fri, 5 Feb 2021 at 16:45, Stefan Hajnoczi wrote:
>
> The following changes since commit e2c5093c993ef646e4e28f7aa78429853bcc06ac:
>
> iotests: 30: drop from auto group (and effectively from make check)
> (2021-02-05 15:16:13 +)
>
> are available in the Git repository at:
>
> https://gi
Hi all,
I will try to give my two cents:
On Fri, Feb 05, 2021 at 03:31:40PM -0500, John Snow wrote:
> On 2/5/21 11:43 AM, Philippe Mathieu-Daudé wrote:
> > Cc'ing Avocado team & John (Python inferior exit delay?).
> >
> > On 1/28/21 11:10 AM, Thomas Huth wrote:
> > > On 28/01/2021 10.45, Claudio
> On Feb 5, 2021, at 3:49 PM, Michael S. Tsirkin wrote:
>
> On Fri, Feb 05, 2021 at 03:25:00PM -0500, Programmingkid wrote:
>> Hi, I'm noticing that my Windows XP Service Pack 3 VM is causing
>> qemu-system-i386 to experience 100% host cpu usage even when the guest is at
>> idle. I was wonde
On 2/5/21 11:43 AM, Philippe Mathieu-Daudé wrote:
Cc'ing Avocado team & John (Python inferior exit delay?).
On 1/28/21 11:10 AM, Thomas Huth wrote:
On 28/01/2021 10.45, Claudio Fontana wrote:
is it just me, or is the CI sometimes failing with timeout?
Fedora:
https://gitlab.com/hw-claudio/qe
On Fri, Feb 05, 2021 at 12:57:05PM -0600, Eric Blake wrote:
> Our default of a backlog of 1 connection is rather puny, particularly
> for scenarios where we expect multiple listeners to connect (such as
> qemu-nbd -e X). This is especially important for Unix sockets, as a
> definite benefit to cli
On 2/4/21 6:39 AM, Claudio Fontana wrote:
> overall, all devices' realize functions take an Error **errp, but return void.
>
> hw/core/qdev.c code, which realizes devices, therefore does:
>
> local_err = NULL;
> dc->realize(dev, &local_err);
> if (local_err != NULL) {
> goto fail;
> }
>
> Ho
On 2/4/21 6:39 AM, Claudio Fontana wrote:
> Claudio Fontana (18):
> target/riscv: remove CONFIG_TCG, as it is always TCG
> accel/tcg: split TCG-only code from cpu_exec_realizefn
> target/arm: do not use cc->do_interrupt for KVM directly
> cpu: move cc->do_interrupt to tcg_ops
> cpu: move
On 2/4/21 6:39 AM, Claudio Fontana wrote:
> move the check for phys_bits outside of host_cpu_adjust_phys_bits,
> because otherwise it is impossible to return an error condition
> explicitly.
>
> Signed-off-by: Claudio Fontana
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Alex Bennée
> --
On 2/5/21 1:37 AM, Thomas Huth wrote:
On 05/02/2021 01.40, John Snow wrote:
On 2/3/21 12:18 PM, Thomas Huth wrote:
This was only required for the pc-1.0 and earlier machine types.
Now that these have been removed, we can also drop the corresponding
code from the FDC device.
Signed-off-by: Thom
On 2/4/21 6:39 AM, Claudio Fontana wrote:
> @@ -6725,10 +6722,8 @@ static void x86_cpu_initfn(Object *obj)
> x86_cpu_load_model(cpu, xcc->model);
> }
>
> -/* if required, do the accelerator-specific cpu initialization */
> -if (cc->accel_cpu) {
> -cc->accel_cpu->cpu_
On 2/4/21 6:39 AM, Claudio Fontana wrote:
> +static void hvf_cpu_accel_class_init(ObjectClass *oc, void *data)
> +{
> +AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
> +
> +acc->cpu_realizefn = host_cpu_realizefn;
> +acc->cpu_instance_init = hvf_cpu_instance_init;
> +};
Watch the stray ; af
On Fri, Feb 5, 2021 at 8:57 PM Eric Blake wrote:
>
> Our default of a backlog of 1 connection is rather puny, particularly
> for scenarios where we expect multiple listeners to connect (such as
> qemu-nbd -e X). This is especially important for Unix sockets, as a
> definite benefit to clients: at
> On Feb 5, 2021, at 1:49 PM, Jonathan Cameron
> wrote:
>
> On Fri, 5 Feb 2021 09:19:36 -0800
> Ben Widawsky wrote:
>
>> On 21-02-05 16:09:54, Jonathan Cameron wrote:
>>> On Wed, 3 Feb 2021 23:53:53 -0500
>>> Chris Browy wrote:
>>>
Hi Jonathan,
Thanks for the review commen
On Fri, 5 Feb 2021 at 19:31, Philippe Mathieu-Daudé wrote:
>
> On Fri, Feb 5, 2021 at 8:21 PM Peter Maydell wrote:
> > On Fri, 5 Feb 2021 at 18:05, Philippe Mathieu-Daudé wrote:
> > > On 2/5/21 5:59 PM, Peter Maydell wrote:
> > > > (The selftest is part of the AN524
> > > > download so it's behi
On Fri, Feb 5, 2021 at 8:21 PM Peter Maydell wrote:
> On Fri, 5 Feb 2021 at 18:05, Philippe Mathieu-Daudé wrote:
> > On 2/5/21 5:59 PM, Peter Maydell wrote:
> > > (The selftest is part of the AN524
> > > download so it's behind a EULA click-through and we can't put it
> > > into an acceptance tes
On Mon, 26 Oct 2020 at 22:35, Peter Maydell wrote:
>
> So, I somehow ended up with this process still running on my
> local machine after a (probably failed) 'make check-acceptance':
>
> petmay01 13710 99.7 3.7 2313448 1235780 pts/16 Sl 16:10 378:00
> ./qemu-system-aarch64 -display none -vga non
On Fri, 5 Feb 2021 at 18:05, Philippe Mathieu-Daudé wrote:
> On 2/5/21 5:59 PM, Peter Maydell wrote:
> > (The selftest is part of the AN524
> > download so it's behind a EULA click-through and we can't put it
> > into an acceptance test. We might be able to get something
> > based on Zephyr or Arm
On Fri, 5 Feb 2021 at 18:07, Philippe Mathieu-Daudé wrote:
>
> On 2/5/21 6:14 PM, Peter Maydell wrote:
> > -/* This is a model of the Arm PrimeCell PL080/PL081 DMA controller:
> > +/*
> > + * This is a model of the Arm PrimeCell PL080/PL081 DMA controller:
> > * The PL080 TRM is:
> > - * http://
On 2/5/21 3:55 AM, Daniel P. Berrangé wrote:
>> +++ b/util/qemu-sockets.c
>> @@ -1059,7 +1059,7 @@ int unix_listen(const char *str, Error **errp)
>>
>> saddr = g_new0(UnixSocketAddress, 1);
>> saddr->path = g_strdup(str);
>> -sock = unix_listen_saddr(saddr, 1, errp);
>> +sock = u
Our default of a backlog of 1 connection is rather puny, particularly
for scenarios where we expect multiple listeners to connect (such as
qemu-nbd -e X). This is especially important for Unix sockets, as a
definite benefit to clients: at least on Linux, a client trying to
connect to a Unix socket
Hi,
I am running QEMU in TCG mode (my server doesn't have kvm support), and I
am getting the memory traces in a x86 guest machine of all memory accesses,
including the PCID (process-context identifier, and I need that for my
current research), on a linux host. I have seen the TCG PCID feature flag
On Fri, 5 Feb 2021 09:19:36 -0800
Ben Widawsky wrote:
> On 21-02-05 16:09:54, Jonathan Cameron wrote:
> > On Wed, 3 Feb 2021 23:53:53 -0500
> > Chris Browy wrote:
> >
> > > Hi Jonathan,
> > >
> > > Thanks for the review comments and we'll put out a v2 patch series
> > > based on a genuine
On 04/02/21 23:50, Philippe Mathieu-Daudé wrote:
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
index ed52fcd49ff..93aec483e88 100644
--- a/hw/scsi/scsi-disk.c
+++ b/hw/scsi/scsi-disk.c
@@ -1089,7 +1089,7 @@ static int scsi_emulate_mechanism_status(SCSIDiskState
*s, uint8_t *outbuf)
st
On 2/5/21 5:57 PM, Peter Maydell wrote:
> On Fri, 5 Feb 2021 at 14:43, Philippe Mathieu-Daudé wrote:
>>
>> The Xilinx CAN controller test is uses the ZCU102 board which is
>> based on a ZynqMP SoC. In the default configuration - used by this
>> test - this SoC creates 2 Cortex R5F cores. Such core
Patchew URL:
https://patchew.org/QEMU/20210205170019.25319-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210205170019.25319-1-peter.mayd...@linaro.org
Subject: [PATCH 00/24] hw/arm: New b
Thomas Huth writes:
> Use clang-10, so we can also use the --enable-tsan configure
> option instead of only passing the flag via --extra-cflags.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Alex Bennée
--
Alex Bennée
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the word "blacklist"
appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Reviewed-by: Daniel P. Berrangé
Acked-by: Eduardo Otubo
Signed-of
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the words "whitelist"
appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Daniel P. Berran
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the word "blacklist"
appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Reword (danpb)
---
Follow the inclusive terminology from the "Conscious Language in your
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[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Reviewed-by: Gerd Hoffmann
Signed-off-by: Philippe Mathieu-Daudé
On 2/5/21 5:59 PM, Peter Maydell wrote:
> The AN524 has a different SYSCLK frequency from the AN505 and AN521;
> make the SYSCLK frequency a field in the MPS2TZMachineClass rather
> than a compile-time constant so we can support the AN524.
>
> Signed-off-by: Peter Maydell
> ---
> hw/arm/mps2-tz.
On 2/5/21 5:59 PM, Peter Maydell wrote:
> This patchseries implements a new board model in the mps2/mps3 family,
> based on Application Note AN524:
> https://developer.arm.com/documentation/dai0524/latest/
>
> Like the other MPS models, this board is an FPGA image; the AN524
> image is based on th
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the words "blacklist"
and "whitelist" appropriately.
Since v1:
- dropped qemu-guest-agent patches
- addressed review comments
- added R-b tags
Missing review: PATCH #6 "qemu-opti
On 2/5/21 6:14 PM, Peter Maydell wrote:
> Update infocenter.arm.com URLs for various pieces of Arm
> documentation to the new developer.arm.com equivalents. (There is a
> redirection in place from the old URLs, but we might as well update
> our comments in case the redirect ever disappears in futu
On 1/26/21 3:31 AM, Markus Armbruster wrote:
> Eric Blake writes:
>
>> These cases require a bit more thought to review; in each case, the
>> code was appending to a list, but not with a FOOList **tail variable.
>>
>> Signed-off-by: Eric Blake
>> Reviewed-by: Vladimir Sementsov-Ogievskiy
>>
>>
Thomas Huth writes:
> Add it to the existing Clang job and also add a job that covers the
> linux-user code with this compiler flag. To make sure that the detected
> problems are not simply ignored, let's also use "-fno-sanitize-recover=..."
> now instead.
>
> Signed-off-by: Thomas Huth
> ---
Am 27.11.2020 um 15:45 hat Vladimir Sementsov-Ogievskiy geschrieben:
> Move bdrv_reopen_multiple to new paradigm of permission update:
> first update graph relations, then do refresh the permissions.
>
> We have to modify reopen process in file-posix driver: with new scheme
> we don't have prepare
On 21-02-05 16:09:54, Jonathan Cameron wrote:
> On Wed, 3 Feb 2021 23:53:53 -0500
> Chris Browy wrote:
>
> > Hi Jonathan,
> >
> > Thanks for the review comments and we'll put out a v2 patch series
> > based on a genuine git send-email flow in a day or so and plan to include
> > - functionally
Add brief documentation of the new mps3-an524 board.
Signed-off-by: Peter Maydell
---
docs/system/arm/mps2.rst | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
index 8c5b5f1fe07..601ccea15cb 100644
-
Thomas Huth writes:
> We already have similar jobs in the gitlab-CI ("build-some-softmmu" and
> "build-user-plugins"), so let's switch one of them to use --enable-debug
> instead of --enable-debug-tcg, then we can simply drop these jobs from
> the Travis-CI.
>
> Signed-off-by: Thomas Huth
Rev
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the word "blacklist"
appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Reviewed-by: Alex Williamson
Acked-by: Alex Williamson
Reviewed-b
The AN524 has a PL031 RTC, which we have a model of; provide it
rather than an unimplemented-device stub.
Signed-off-by: Peter Maydell
---
hw/arm/mps2-tz.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index db1afa
Thomas Huth writes:
> Simply add the flag to an existing job, no need for yet another
> job here.
>
> Reviewed-by: Wainer dos Santos Moschetta
> Signed-off-by: Thomas Huth
Reviewed-by: Alex Bennée
--
Alex Bennée
Follow the inclusive terminology from the "Conscious Language in your
Open Source Projects" guidelines [*] and replace the word "whitelist"
appropriately.
[*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Philippe Mathieu-Da
Hi Taylor,
+Eric in case I'm wrong.
On 1/30/21 12:15 AM, Taylor Simpson wrote:
On 1/20/21 4:28 AM, Taylor Simpson wrote:
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/attribs.h | 30 ++
> target/hexagon/attribs_def.h | 95
++
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