On 10/12/2020 20.04, Alex Bennée wrote:
> Hopefully this will guard against sloppy code getting into our tests.
>
> Suggested-by: Paolo Bonzini
> Signed-off-by: Alex Bennée
> ---
> tests/tcg/Makefile.target | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/tcg/Make
On 10/12/2020 20.04, Alex Bennée wrote:
> By default QEMU enables a lot of features if it can probe and find the
> support libraries. It also enables a bunch of features by default.
> This patch adds the ability to build --without-default-features which
> can be paired with a --without-default-devi
On Fri, Dec 11, 2020 at 2:35 AM Philippe Mathieu-Daudé
wrote:
>
> This code (introduced in commit 1d14ffa97ea, Oct 2005)
> is likely unused since years. Time to remove it. If
> the condition is true, simply call abort().
>
> Suggested-by: Gerd Hoffmann
> Signed-off-by: Philippe Mathieu-Daudé
I
On Dec 10 19:25, Dmitry Fomichev wrote:
> > -Original Message-
> > From: Klaus Jensen
> > Sent: Wednesday, December 9, 2020 4:58 AM
> > To: Dmitry Fomichev
> > Cc: Keith Busch ; Klaus Jensen
> > ; Kevin Wolf ; Philippe
> > Mathieu-Daudé ; Max Reitz ;
> > Maxim Levitsky ; Fam Zheng ;
> > N
From: Bin Meng
When write is disabled, the write to flash should be avoided
in flash_write8().
Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device")
Signed-off-by: Bin Meng
---
(no changes since v2)
Changes in v2:
- new patch: honor write enable flag in flash write
hw/
From: Xuzhou Cheng
Auto Address Increment (AAI) Word-Program is a special command of
SST flashes. AAI-WP allows multiple bytes of data to be programmed
without re-issuing the next sequential address location.
Signed-off-by: Xuzhou Cheng
Signed-off-by: Bin Meng
---
Changes in v3:
- initialize
From: Xuzhou Cheng
Auto Address Increment (AAI) Word-Program is a special command of
SST flashes. AAI-WP allows multiple bytes of data to be programmed
without re-issuing the next sequential address location.
Signed-off-by: Xuzhou Cheng
Signed-off-by: Bin Meng
---
Changes in v2:
- add aai_en
From: Bin Meng
When write is disabled, the write to flash should be avoided
in flash_write8().
Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device")
Signed-off-by: Bin Meng
---
Changes in v2:
- new patch: honor write enable flag in flash write
hw/block/m25p80.c | 1 +
1
On 10/12/2020 20.04, Alex Bennée wrote:
> We still build it but there is no point including it in the normal
> builds as it is ushered out of the door.
>
> Fixes: 4258c8e221 ("docs/system/deprecated: Mark the 'moxie' CPU as
> deprecated")
> Signed-off-by: Alex Bennée
> ---
> configure | 2
On 10/12/2020 20.04, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
>
> ---
> v2
> - move to centos8
> ---
> .gitlab-ci.yml | 7 +++
> .travis.yml| 8
> 2 files changed, 7 insertions(+), 8 deletions(-)
Reviewed-by: Thomas Huth
On 10/12/2020 20.04, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
>
> ---
> v2
> - swap with centos8, don't include --without-default-devuces
> ---
> .gitlab-ci.yml | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
> index 2134453717..229545bc0
On 10/12/2020 20.04, Alex Bennée wrote:
> Otherwise we miss coverage of KVM support in the cross build. To
> balance it out add arm-softmmu (no kvm, subset of aarch64),
> cris-softmmu and ppc-softmmu to the exclude list which do get coverage
> elsewhere.
>
> Signed-off-by: Alex Bennée
> ---
> .g
Hi Francisco,
On Thu, Dec 3, 2020 at 8:54 PM Francisco Iglesias
wrote:
>
> Hello Bin,
>
> On [2020 Dec 02] Wed 22:30:37, Bin Meng wrote:
> > From: Xuzhou Cheng
> >
> > Auto Address Increment (AAI) Word-Program is a special command of
> > SST flashes. AAI-WP allows multiple bytes of data to be pr
Hi Francisco,
On Fri, Dec 4, 2020 at 7:28 PM Francisco Iglesias
wrote:
>
> Hello Bin,
>
> On [2020 Dec 04] Fri 18:52:50, Bin Meng wrote:
> > Hi Francisco,
> >
> > On Fri, Dec 4, 2020 at 6:46 PM Francisco Iglesias
> > wrote:
> > >
> > > Hello Bin,
> > >
> > > On [2020 Dec 04] Fri 15:52:12, Bin Me
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic, it's implemented as a NOP.
Signed-off-by: Rebecca Cran
---
target/arm/cpu.h | 20 +-
target/arm/helper.c| 28 +
This series adds support for DIT (Data Independent Timing), and then
enables it for the "max" aarch64 CPU type.
Rebecca Cran (2):
target/arm: add support for FEAT_DIT, Data Independent Timing
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64
CPU
target/arm/cpu.h
Enable FEAT_DIT for the "max" AARCH64 CPU.
Signed-off-by: Rebecca Cran
---
target/arm/cpu64.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 649213082ff9..223e0bfd22c2 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -641,6 +641,
10.12.2020 16:47, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Since clang doesn't support gnu_printf, make that case explicitely and
drop GCC version check.
Not a technical comment, - spelling "explicitely", extra "e".
/mjt
From: Greg Kurz
This allows to drop a user of qdev_get_machine().
Signed-off-by: Greg Kurz
Message-Id: <20201209170052.1431440-4-gr...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/spapr_hcall.c | 7 ---
hw/ppc/spapr_pci.c | 3 +--
include/hw/ppc/spapr.h | 2 +-
3 files changed,
From: Stephane Duverger
The ppc_tr_init_disas_context() function currently checks whether the
MMU is 64-bit by ANDing its model type with POWERPC_MMU_64B. This is
wrong : POWERPC_MMU_64B isn't a mask, it is the generic MMU model for
pre-PowerISA-2.03 64-bit CPUs (ie. PowerPC 970 in QEMU).
Use PO
From: Daniel Henrique Barboza
spapr_kvm_type() is considering 'vm_type=NULL' as a valid input, where
the function returns 0. This is relying on the current QEMU machine
options handling logic, where the absence of the 'kvm-type' option
will be reflected as 'vm_type=NULL' in this function.
This i
From: Greg Kurz
Callers don't really need to know how 64-bit MMU model enums are
computed. Hide this in a helper.
Signed-off-by: Greg Kurz
Message-Id: <20201209173536.1437351-3-gr...@kaod.org>
Signed-off-by: David Gibson
---
target/ppc/cpu-qom.h| 5 +
target/ppc/excp_helper.c
From: Greg Kurz
spapr_phb_realize() passes the sPAPR machine state as opaque data
for the I/O callbacks:
memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
^
"msi", msi_windo
From: Greg Kurz
This property has been deprecated since QEMU 5.0 by commit 22062e54bb68.
We only kept a legacy hack that internally converts "compat" into the
official "max-cpu-compat" property of the pseries machine type.
According to our deprecation policy, we could have removed it for QEMU 5.
Greg has agreed to be co-maintainer of the ppc target and machines.
This should avoid repeats of the problem we had in qemu-5.2 where a
last minute fix was needed while I was on holiday.
Signed-off-by: David Gibson
Acked-by: Greg Kurz
---
MAINTAINERS | 17 -
1 file changed, 16 i
From: Gan Qixin
When running qom-test, a memory leak occurred in the ppce500_init function,
this patch free irqs array to fix it.
ASAN shows memory leak stack:
Direct leak of 40 byte(s) in 1 object(s) allocated from:
#0 0xfffc5ceee1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
From: Greg Kurz
Some functions in hw/ppc/spapr_events.c get a pointer to the machine
state using qdev_get_machine(). Convert them to get it from their
caller when possible.
Signed-off-by: Greg Kurz
Message-Id: <20201209170052.1431440-6-gr...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/sp
From: Greg Kurz
All users are passing &error_abort already. Document the fact
that spapr_drc_attach() should only be passed a free DRC, which
is supposedly the case if appropriate checking is done earlier.
Signed-off-by: Greg Kurz
Message-Id: <20201201113728.885700-5-gr...@kaod.org>
Signed-off-
From: Greg Kurz
This hack registers dummy VMState entries of ICPs in order to
support migration of old pseries machine types that used to
create all smp.max_cpus possible ICPs at machine init.
Part of the work is to unregister the dummy entries when plugging
an actual vCPU core, and to register
From: Greg Kurz
A guest with enough RAM, eg. 128G, is likely to detect savevm downtime
and to complain about stalled CPUs. This happens because we re-read
the timebase just before migrating it and we thus don't account for
all the time between VM stop and pre-save.
A very similar situation was a
From: Greg Kurz
When a CPU is hot-plugged, we set its compat mode to match the boot
CPU, which was either set by machine reset or by CAS. This is currently
handled in the plug handler after the core got realized. Potential errors
of ppc_set_compat() are propagated to the hot-plug logic.
Handling
From: Philippe Mathieu-Daudé
The '%u' conversion specifier is for decimal notation.
When prefixing a format with '0x', we want the hexadecimal
specifier ('%x').
Inspired-by: Dov Murik
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201103112558.2554390-4-phi...@redhat.com>
Reviewed-by: Gr
From: Greg Kurz
spapr_core_pre_plug() already guarantees that the slot for the given core
ID is available. It is thus safe to assume that spapr_find_cpu_slot()
returns a slot during plug. Turn the error path into an assertion.
It is also safe to assume that no device is attached to the correspond
From: LemonBoy
The PowerISA reference states that the comparison operators update the
FPCC, CR and FPSCR and, if VE=1, jump to the exception handler.
Moving the exception-triggering code after the CC update sequence solves
the problem.
Signed-off-by: Giuseppe Musacchio
Reviewed-by: Richard Hen
From: LemonBoy
Make the implementation match the lxvwsx one.
The code is now shorter smaller and potentially faster as the
translation will use the host SIMD capabilities if available.
No functional change.
Signed-off-by: Giuseppe Musacchio
Message-Id:
Reviewed-by: Richard Henderson
Signed-
From: Cédric Le Goater
I have been keeping those logging messages in an ugly form for
while. Make them clean !
Beware not to activate all of them, this is really verbose.
Signed-off-by: Cédric Le Goater
Message-Id: <20201123163717.1368450-1-...@kaod.org>
Signed-off-by: David Gibson
---
hw/in
From: LemonBoy
Since we always perform a comparison between the two operands avoid
checking for NaN unless the result states they're unordered.
Suggested-by: Richard Henderson
Signed-off-by: Giuseppe Musacchio
Reviewed-by: Richard Henderson
Message-Id: <20201112230130.65262-4-thatle...@gmail.
From: Greg Kurz
We currently detect that a PHB index is already in use at plug time.
But this can be decteted at pre-plug in order to error out earlier.
This allows to pass &error_abort to spapr_drc_attach() and to end
up with a plug handler that doesn't need to report errors anymore.
Signed-of
From: LemonBoy
According to the PowerISA v3.1 reference, Table 68 "Actions for xscmpudp
- Part 1: Compare Unordered", whenever one of the two operands is a NaN
the SO bit is set while the other three bits are cleared.
Apply the same change to xscmpuqp.
The respective ordered counterparts are un
From: Chen Qun
When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning:
hw/ppc/ppc.c: In function ‘ppc6xx_set_irq’:
hw/ppc/ppc.c:118:16: warning: this statement may fall through
[-Wimplicit-fallthrough=]
118 | if (level) {
|^
hw/ppc/ppc.c:
From: LemonBoy
Suggested-by: Richard Henderson
Signed-off-by: Giuseppe Musacchio
Reviewed-by: Richard Henderson
Message-Id: <20201112230130.65262-3-thatle...@gmail.com>
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 228 ++--
1 file changed, 123
From: Greg Kurz
There can be only one TPM proxy at a time. This is currently
checked at plug time. But this can be detected at pre-plug in
order to error out earlier.
This allows to get rid of error handling in the plug handler.
Signed-off-by: Greg Kurz
Message-Id: <20201120234208.683521-9-gr.
The following changes since commit 2ecfc0657afa5d29a373271b342f704a1a3c6737:
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-12-10' into
staging (2020-12-10 17:01:05 +)
are available in the Git repository at:
https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.0-20201211
From: Greg Kurz
Never used from the start.
Signed-off-by: Greg Kurz
Message-Id: <20201120174646.619395-6-gr...@kaod.org>
Reviewed-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics_kvm.c | 2 +-
hw/ppc/spapr_irq.c | 2 +-
include/hw/ppc/xics_spapr.h | 2 +-
3
From: Chen Qun
When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning:
target/ppc/mmu_helper.c: In function ‘dump_mmu’:
target/ppc/mmu_helper.c:1351:12: warning: this statement may fall through
[-Wimplicit-fallthrough=]
1351 | if (ppc64_v3_radix(env_archcpu(env)))
From: Greg Kurz
Pre-plug of a memory device, be it an NVDIMM or a PC-DIMM, ensures
that the memory slot is available and that addresses don't overlap
with existing memory regions. The corresponding DRCs in the LMB
and PMEM namespaces are thus necessarily attachable at plug time.
Pass &error_abor
From: Greg Kurz
Read documentation in "qapi/error.h" and changelog of commit
e3fe3988d785 ("error: Document Error API usage rules") for
rationale.
Signed-off-by: Greg Kurz
Message-Id: <20201120234208.683521-7-gr...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 40
From: Greg Kurz
The PHB acts as the hotplug handler for PCI devices. It does some
sanity checks on DR enablement, PCI bridge chassis numbers and
multifunction. These checks are currently performed at plug time,
but they would best sit in a pre-plug handler in order to error
out as early as possib
From: Greg Kurz
The sPAPR XIVE device is created by the machine in spapr_irq_init().
The latter overrides any value provided by the user with -global for
the "nr-irqs" and "nr-ends" properties with strictly positive values.
It seems reasonable to assume these properties should never be 0,
which
On Thu, Dec 10, 2020 at 05:51:49PM -0800, Hao Wu wrote:
> This patch series include a few more NPCM7XX devices including
>
> - Analog Digital Converter (ADC)
> - Pulse Width Modulation (PWM)
> - Keyboard Style Controller (KSC)
>
> To utilize these modules we also add two extra functionalities:
>
Hi, Rechard and Peter,
On Wed, Dec 2, 2020 at 5:32 PM Philippe Mathieu-Daudé wrote:
>
> On 12/2/20 2:14 AM, Huacai Chen wrote:
> > Hi, Phillippe,
> >
> > On Tue, Nov 24, 2020 at 6:25 AM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 11/6/20 5:21 AM, Huacai Chen wrote:
> >>> Preparing to add Loo
Kindly ping!
Hi folks,
Patch 1 to Patch 4 are not in the queue. Could someone help pick them up?
Patch1~Patch4:
hw/rdma/rdma_backend: fix uninitialized variable warning in
rdma_poll_cq()
util/qemu-timer: fix uninitialized variable warning in
timer_mod_anticipate_ns()
util/qemu-tim
Kindly ping!
Hi all,
Patch 1 to Patch 5 are not in the queue. Could someone pick them up？
Patch1~Patch5:
target/i386: silence the compiler warnings in gen_shiftd_rm_T1
hw/intc/arm_gicv3_kvm: silence the compiler warnings
accel/tcg/user-exec: silence the compiler warnings
target/sparc/t
On 2020/12/11 0:31, Markus Armbruster wrote:
> From: Zihao Chang
>
> Fix the example of add qmp hello-world example.
> Without ":", make will report error:
> ../qapi/misc.json:573:2: line should end with ':'
>
> Signed-off-by: Zihao Chang
> Message-Id: <20201201143308.1626-1-changzih...@huaw
The IPMI external host device works for Baseband Management Controller
(BMC) emulations. It works as a representation of a host class that
connects to a given BMC. It can connect to a real host hardware or a
emulated or simulated host device. In particular it can connect to a
host QEMU instance wi
Add a KCS module for NPCM7xx SoC. This module implements the IPMI
responder interface and is responsible to communicate with an external
host via the KCS channels in an NPCM7xx SoC.
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
docs/system/arm/nuvoton.rst | 2 +-
hw/arm/npcm7xx.c
The IPMI host interface is used to emulate IPMI related devices on a
System-on-Chip (SoC) used for Baseband Management Controller (BMC).
This interface consists of two components: IPMI host and IPMI responder.
An IPMI responder is a device to intercept reads and writes to the
system interface regis
The ADC is part of NPCM7XX Module. Its behavior is controled by the
ADC_CON register. It converts one of the eight analog inputs into a
digital input and stores it in the ADC_DATA register when enabled.
Reviewed-by: Havard Skinnemoen
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
docs/syst
This patch makes NPCM7XX Timer to use a the timer clock generated by the
CLK module instead of the magic nubmer TIMER_REF_HZ.
Reviewed-by: Havard Skinnemoen
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 5 +
hw/timer/npcm7xx_timer.c | 25 +++
This patch allows NPCM7XX CLK module to compute clocks that are used by
other NPCM7XX modules.
Add a new struct NPCM7xxClockConverterState which represents a
single converter. Each clock converter in CLK module represents one
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
ta
The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
two outputs: frequency and duty_cycle. Both are computed using inputs
from software side.
This module does not model detail pulse signals since it is expens
This patch series include a few more NPCM7XX devices including
- Analog Digital Converter (ADC)
- Pulse Width Modulation (PWM)
- Keyboard Style Controller (KSC)
To utilize these modules we also add two extra functionalities:
1. We modified the CLK module to generate clock values using qdev_clock
On 12/10/20 2:47 PM, Peter Maydell wrote:
>> With the shift, you're discarding the high 32 bits of the result. You'll
>> lose
>> those same bits if you shift one of the inputs left by 32, and use only the
>> high part of the result, e.g.
>>
>> mulu(&discard, &ret, clk->period, ticks << 32);
>
On Thu, Dec 10, 2020 at 09:00:41AM +0100, Thomas Huth wrote:
> On 09/12/2020 10.13, John Paul Adrian Glaubitz wrote:
> > Public bug reported:
> >
> > Trying to build QEMU on sparc64 fails with:
> [...]
> > /usr/bin/ld: libqemu-ppc64-softmmu.fa.p/hw_ppc_spapr_hcall.c.o: in function
> > `h_update_d
Enable this on i386 to restrict the set of input registers
for an 8-bit store, as required by the architecture. This
removes the last use of scratch registers for user-only mode.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h | 5 +
tcg/aarch64/tcg-target.h | 1 +
tcg/arm
Eliminating these cleans up the backend a bit, allows the
code generator more freedom to properly place the inputs.
r~
Richard Henderson (2):
tcg/i386: Adjust TCG_TARGET_HAS_MEMORY_BSWAP
tcg: Introduce INDEX_op_qemu_st8_i32
include/tcg/tcg-opc.h | 5 ++
tcg/aarch64/tcg-target.h |
Always true when movbe is available, otherwise leave
this to generic code.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 3 +-
tcg/i386/tcg-target.c.inc | 119 ++
2 files changed, 47 insertions(+), 75 deletions(-)
diff --git a/tcg/i386/tc
From: Claudio Fontana
split up the CpusAccel tcg_cpus into three TCG variants:
tcg_cpus_rr (single threaded, round robin cpus)
tcg_cpus_icount (same as rr, but with instruction counting enabled)
tcg_cpus_mttcg (multi-threaded cpus)
Suggested-by: Richard Henderson
Signed-off-by: Claudio Fontana
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20201015143217.29337-4-cfont...@suse.de>
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-cpus-icount.h | 6 +--
accel/tcg/tcg-cpus-rr.h | 2 +-
accel/tcg/tcg-cpus.h| 6 +--
On 2020/12/10 22:50, Peter Xu wrote:
> On Thu, Dec 10, 2020 at 10:53:23AM +0800, zhukeqian wrote:
>>
>>
>> On 2020/12/10 10:08, Peter Xu wrote:
>>> Keqian,
>>>
>>> On Thu, Dec 10, 2020 at 09:46:06AM +0800, zhukeqian wrote:
Hi,
I see that if start or size is not PAGE aligned, it als
The following changes since commit 2ecfc0657afa5d29a373271b342f704a1a3c6737:
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-12-10' into
staging (2020-12-10 17:01:05 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tc
From: Claudio Fontana
after the initial split into 3 tcg variants, we proceed to also
split tcg_start_vcpu_thread.
We actually split it in 2 this time, since the icount variant
just uses the round robin function.
Suggested-by: Richard Henderson
Signed-off-by: Claudio Fontana
Message-Id: <2020
On Thu, Dec 10, 2020 at 05:51:41PM +0100, Paolo Bonzini wrote:
> On 10/12/20 15:55, Daniel Henrique Barboza wrote:
> > changes from v2, all proposed by Greg:
> > * Handle 'NULL' value as default mode fallback in spapr_kvm_type()
> > * Do not allow for 'AUTO' to be a valid mode in spapr_kvm_type()
>
The following changes since commit 2ecfc0657afa5d29a373271b342f704a1a3c6737:
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-12-10' into
staging (2020-12-10 17:01:05 +)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/machine-next-pull-req
From: Luwei Kang
The current implementation will disable the guest Intel PT feature
if the Intel PT LIP feature is supported on the host, but the LIP
feature is comming soon(e.g. SnowRidge and later).
This patch will make the guest LIP feature configurable and Intel
PT feature can be enabled in
From: Tobin Feldman-Fitzthum
AMD SEV allows a guest owner to inject a secret blob
into the memory of a virtual machine. The secret is
encrypted with the SEV Transport Encryption Key and
integrity is guaranteed with the Transport Integrity
Key. Although QEMU facilitates the injection of the
launch
From: Ani Sinha
Object property insertion code iterates over an integer to get an unused
index that can be used as an unique name for an object property. This loop
increments the integer value indefinitely. Although very unlikely, this can
still cause an integer overflow.
In this change, we fix t
This code (introduced in commit 1d14ffa97ea, Oct 2005)
is likely unused since years. Time to remove it. If
the condition is true, simply call abort().
Suggested-by: Gerd Hoffmann
Signed-off-by: Philippe Mathieu-Daudé
---
audio/audio.c | 19 +--
1 file changed, 1 insertion(+), 1
On 12/10/20 8:04 PM, Alex Bennée wrote:
> Hopefully this will guard against sloppy code getting into our tests.
>
> Suggested-by: Paolo Bonzini
> Signed-off-by: Alex Bennée
> ---
> tests/tcg/Makefile.target | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-D
FYI. Same thing we saw on Fedora installing freeipa, this on ubuntu
with ceph. Identical bitmask report.
...
Fixing /var/run/ceph ownershipdone
Cannot set file attribute for '/var/log/journal', value=0x0080,
mask=0x0080, ignoring: Function not implemented
Cannot set file attribute
On Thu, Dec 03, 2020 at 06:29:02AM -0800, P J P wrote:
> From: Prasad J Pandit
>
> We are about to introduce a qemu-security mailing list to report
> and triage QEMU security issues.
>
> Update the security process web page with new mailing list address
> and triage details.
>
> Signed-off-by:
On Thu, 3 Dec 2020, P J P wrote:
> From: Prasad J Pandit
>
> We are about to introduce a qemu-security mailing list to report
> and triage QEMU security issues.
>
> Update the security process web page with new mailing list address
> and triage details.
>
> Signed-off-by: Prasad J Pandit
Acke
Patchew URL: https://patchew.org/QEMU/20201210121226.19822-1-cfont...@suse.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201210121226.19822-1-cfont...@suse.de
Subject: [PATCH v10 00/32] i386 cleanup
=== TEST SCR
On Tue, 8 Dec 2020 at 23:39, Richard Henderson
wrote:
>
> On 12/8/20 12:15 PM, Peter Maydell wrote:
> > +static inline uint64_t clock_ticks_to_ns(const Clock *clk, uint64_t ticks)
> > +{
> > +uint64_t ns_low, ns_high;
> > +
> > +/*
> > + * clk->period is the period in units of 2^-32 ns
Patchew URL:
https://patchew.org/QEMU/20201210161452.2813491-1-arm...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201210161452.2813491-1-arm...@redhat.com
Subject: [PATCH 00/10] Fix floating-point -> t
When we first converted our documentation to Sphinx, we split it into
multiple manuals (system, interop, tools, etc), which are all built
separately. The primary driver for this was wanting to be able to
avoid shipping the 'devel' manual to end-users. However, this is
working against the grain of
* Vivek Goyal (vgo...@redhat.com) wrote:
> On Thu, Dec 10, 2020 at 08:03:03PM +, Dr. David Alan Gilbert wrote:
> > * Vivek Goyal (vgo...@redhat.com) wrote:
> > > Currently lo_flush() is written in such a way that it expects to receive
> > > a FLUSH requests on a regular file (and not directorie
This is a lot smaller than v2 because most of that work made it
through review and is now in master. This series has the last few
patches that needed rework to address review comments, one new patch
(patch 2) which fixes a bug that I missed until this evening, and the
final "provide a Cortex-M55 m
In commit 64f863baeedc8659 we implemented the v8.1M FPCXT_S register,
but we got the write behaviour wrong. On read, this register reads
bits [27:0] of FPSCR plus the CONTROL.SFPA bit. On write, it doesn't
just write back those bits -- it writes a value to the whole FPSCR,
whose upper 4 bits are ze
Now that we have implemented all the features needed by the v8.1M
architecture, we can add the model of the Cortex-M55. This is the
configuration without MVE support; we'll add MVE later.
Signed-off-by: Peter Maydell
---
target/arm/cpu_tcg.c | 42 ++
1 fi
Implement the v8.1M FPCXT_NS floating-point system register. This is
a little more complicated than FPCXT_S, because it has specific
handling for "current FP state is inactive", and it only wants to do
PreserveFPState(), not the full set of actions done by
ExecuteFPCheck() which vfp_access_check()
The CCR is a register most of whose bits are banked between security
states but where BFHFNMIGN is not, and we keep it in the non-secure
entry of the v7m.ccr[] array. The logic which tries to handle this
bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS
is zero" requirement; cor
On Thu, Dec 10, 2020 at 08:39:32AM -0800, Alistair Francis wrote:
> On Thu, Dec 10, 2020 at 6:27 AM Philippe Mathieu-Daudé
> wrote:
> >
> > Malicious user can set the feedback divisor for the PLLs
> > to zero, triggering a floating-point exception (SIGFPE).
> >
> > As the datasheet [*] is not cle
On Thu, Dec 10, 2020 at 08:03:03PM +, Dr. David Alan Gilbert wrote:
> * Vivek Goyal (vgo...@redhat.com) wrote:
> > Currently lo_flush() is written in such a way that it expects to receive
> > a FLUSH requests on a regular file (and not directories). For example,
> > we call lo_fi_fd() which sea
* Vivek Goyal (vgo...@redhat.com) wrote:
> Currently lo_flush() is written in such a way that it expects to receive
> a FLUSH requests on a regular file (and not directories). For example,
> we call lo_fi_fd() which searches lo->fd_map. If we open directories
> using opendir(), we keep don't keep t
* Vivek Goyal (vgo...@redhat.com) wrote:
> If remote posix locks are not enabled (lo->posix_lock == false), then disable
> code paths taken to initialize inode->posix_lock hash table and corresponding
> destruction and search etc.
>
> lo_getlk() and lo_setlk() have been modified to return ENOSYS i
* Vivek Goyal (vgo...@redhat.com) wrote:
> We setup per inode hash table ->posix_lock to support remote posix locks.
> But we forgot to initialize this table for root inode.
>
> Laszlo managed to trigger an issue where he sent a FUSE_FLUSH request for
> root inode and lo_flush() found inode with i
On Thu, 10 Dec 2020 at 16:32, Markus Armbruster wrote:
>
> The following changes since commit 00ef48ff0de9c3e5834e7e3f6691bbc80d08c114:
>
> Merge remote-tracking branch
> 'remotes/kraxel/tags/microvm-20201210-pull-request' into staging (2020-12-10
> 12:53:01 +00
On Thu, Dec 10, 2020 at 5:11 PM Vivek Goyal wrote:
> Conclusion
> ---
> - virtiofs DAX seems to help a lot in many workloads.
>
> Note, DAX performance well only if data fits in cache window. My total
> data is 16G and cache window size is 16G as well. If data is larger
> than DAX c
> -Original Message-
> From: Klaus Jensen
> Sent: Wednesday, December 9, 2020 4:58 AM
> To: Dmitry Fomichev
> Cc: Keith Busch ; Klaus Jensen
> ; Kevin Wolf ; Philippe
> Mathieu-Daudé ; Max Reitz ;
> Maxim Levitsky ; Fam Zheng ;
> Niklas Cassel ; Damien Le Moal
> ; qemu-bl...@nongnu.org; q
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