I have just compiled a few version from source code:
4.1.1 worked: able to boot up with -bios ss20_v2.25.rom
5.0.0 worked: able to boot up with -bios ss20_v2.25.rom
5.1.0 not working. Stuck after "Power-On Reset"
SS5.bin worked for 5.1.0
--
You received this bug notification because you ar
Public bug reported:
I cannot boot up OBP using the current (5.1) version of qemu with
ss20_v2.25_rom. It just stuck at "Power-ON reset" and hanged. However
using the previous version from 2015 I can successfully both up the OBP.
qemu-system-sparc -M SS-20 -m 256 -bios ss20_v2.25.rom -nographic
OK, found my issue! :-). Still a bit odd, but virt-manager complaints about the
custom QEMU executable => but virsh still works. So I did get the VM running,
with,
QEMU emulator version 5.1.93 (v5.2.0-rc3)
Copyright (c) 2003-2020 Fabrice Bellard and the QEMU Project developers
But it still perfo
My apologies, but I'm somewhat stuck here :-(. Trying to run the latest
(upstream) version of QEMU, but no luck getting it to execute. I even tried
setting securit_driver = "none", as captured here,
https://gitlab.com/apparmor/apparmor/-/wikis/Libvirt
But no luck. Open to any suggestions.
Thank
This is the (statically linked) binary resulting from the source; with
it the problem can be demonstrated "standalone", without any other rv32
libraries or a complete chroot, just running the binary with qemu-
riscv32.
Generated with
(riscv-ilp32 chroot) farino /tmp # gcc -static -o wait-test-sho
On Fri, Dec 04, 2020 at 01:35:55PM -0600, Richard Henderson wrote:
Thank you Richard for your answer. I don't want to generate a debate,
or defend the way I've done things initially. Really want to clarify
these internals. Hope it will benefit to other QEMU enthusiasts.
> You can't just inject a
This patch adds a flag to enable/disable control flow integrity checks
on indirect function calls.
This feature only allows indirect function calls at runtime to functions
with compatible signatures.
This feature is only provided by LLVM/Clang, and depends on link-time
optimization which is curren
Document how to compile with CFI and how to maintain CFI-safe code
Signed-off-by: Daniele Buono
---
docs/devel/control-flow-integrity.rst | 137 ++
1 file changed, 137 insertions(+)
create mode 100644 docs/devel/control-flow-integrity.rst
diff --git a/docs/devel/control
This patch allows to compile QEMU with link-time optimization (LTO).
Compilation with LTO is handled directly by meson. This patch only
adds the option in configure and forwards the request to meson
Tested with all major versions of clang from 6 to 12
Signed-off-by: Daniele Buono
---
configure
cfi-icall is a form of Control-Flow Integrity for indirect function
calls implemented by llvm. It is enabled with a -fsanitize flag.
iotests are currently disabled when -fsanitize options is used, with the
exception of SafeStack.
This patch implements a generic filtering mechanism to allow iotest
LLVM/Clang, supports runtime checks for forward-edge Control-Flow
Integrity (CFI).
CFI on indirect function calls (cfi-icall) ensures that, in indirect
function calls, the function called is of the right signature for the
pointer type defined at compile time.
For this check to work, the code must
This patch adds supports for Control-Flow Integrity checks
on indirect function calls.
Requires the use of clang, and link-time optimizations
Since it's been a month, and some of the patches are being
merged independently, I thought of rebasing, retesting
and sending an updated version. Also, add
As gen_check_zero_element() already produces a boolean,
replace 'if (x) tcg_gen_setcondi_tl()' by tcg_gen_xori_tl(x)
which already contains the if (x).
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <20201202184415.1434484-1-f4...@amsat.org>
---
target/mips/
On 11/19/20 2:50 AM, Markus Armbruster wrote:
> Eric Blake writes:
>
>> These cases require a bit more thought to review; in each case, the
>> code was appending to a list, but not with a FOOList **tail variable.
>> +++ b/hw/core/machine-qmp-cmds.c
> [...]
>> @@ -294,41 +281,31 @@ void qmp_set_n
On 12/4/20 6:04 PM, Richard Henderson wrote:
> On 12/2/20 12:44 PM, Philippe Mathieu-Daudé wrote:
>> +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool
>> if_not)
>> +{
>> +check_msa_access(ctx);
>> +
>> +if (ctx->hflags & MIPS_HFLAG_BMASK) {
>> +generate_exc
On 12/4/20 5:28 PM, Richard Henderson wrote:
> On 12/2/20 12:44 PM, Philippe Mathieu-Daudé wrote:
>> Commits 863f264d10f ("add msa_reset(), global msa register") and
>> cb269f273fd ("fix multiple TCG registers covering same data")
>> removed the FPU scalar registers and replaced them by aliases to
Do not initialize MT-related config registers if the MT ASE
is not present. As some functions access the 'mvp' structure,
we still zero-allocate it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate_init.c.inc | 4
1 file changed, 4 insertions(+)
diff --git a/target/mips/tran
Instead of accessing CP0_Config3 directly and checking
the 'Multi-Threading Present' bit, introduce an helper
to simplify code review.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h| 7 +++
hw/mips/cps.c| 3 +--
target/mips/cp0_helper.c | 2 +-
target/mips/cp
On 12/4/20 5:57 PM, Philippe Mathieu-Daudé wrote:
> The NVMe driver does not support image creation.
> The full drive has to be passed to the guest.
>
> Before:
>
> $ qemu-img create -f raw nvme://:04:00.0/1 20G
> Formatting 'nvme://:04:00.0/1', fmt=raw size=21474836480
>
> $ qemu-
PTC field has 8 bits, PVPE has 4. We plan to use the
"hw/registerfields.h" API with MIPS CPU definitions
(target/mips/cpu.h). Meanwhile we use magic 8 and 4.
Signed-off-by: Philippe Mathieu-Daudé
---
We want to move that to mips_cpu_reset() later,
because this is not Malta specific but cpu-specif
Reviewing the MIPS code, ASE after ASE.
Time for MT ASE.
- Introduce/use ase_mt_available() helper to check
if MT ASE is present
- Avoid setting MT specific registers if MT ASE is absent
Philippe Mathieu-Daudé (5):
target/mips: Remove mips_def_t unused argument from mvp_init()
target/mips:
Do not initialize MT-related config register if the MT ASE
is not present.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 9d1a3b50b7a..350b92b4d79 100644
--- a/hw/mips/malta.
mvp_init() doesn't require any CPU definition (beside the
information accessible via CPUMIPSState). Remove the unused
argument.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 2 +-
target/mips/translate_init.c.inc | 2 +-
2 files changed, 2 insertions(+), 2 deletion
From: Andrey Shinkevich
This patch completes the series with the COR-filter applied to
block-stream operations.
Adding the filter makes it possible in future implement discarding
copied regions in backing files during the block-stream job, to reduce
the disk overuse (we need control on permissio
any solution? trying to emulate a closed source amd64 app on my
raspberry and i'm getting this error with qemu 5.2.0-rc4 and glibc 2.27.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1673976
Title:
From: Andrey Shinkevich
If the flag BDRV_REQ_PREFETCH was set, skip idling read/write
operations in COR-driver. It can be taken into account for the
COR-algorithms optimization. That check is being made during the
block stream job by the moment.
Add the BDRV_REQ_PREFETCH flag to the supported_re
Add a direct link to target bs for convenience and to simplify
following commit which will insert COR filter above target bs.
This is a part of original commit written by Andrey.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/stream.c | 23 ++-
1 file changed, 10 inse
From: Andrey Shinkevich
Avoid writing a filter JSON file name and a filter format name to QCOW2
image when the backing file is being changed after the block stream
job. It can occur due to a concurrent commit job on the same backing
chain.
A user is still able to assign the 'backing-file' paramet
test_stream_parallel run parallel stream jobs, intersecting so that top
of one is base of another. It's OK now, but it would be a problem if
insert the filter, as one job will want to use another job's filter as
above_base node.
Correct thing to do is move to new interface: "bottom" argument inste
From: Andrey Shinkevich
Add the new member supported_read_flags to the BlockDriverState
structure. It will control the flags set for copy-on-read operations.
Make the block generic layer evaluate supported read flags before they
go to a block driver.
Suggested-by: Vladimir Sementsov-Ogievskiy
S
From: Andrey Shinkevich
Create the BlockdevOptionsCor structure for COR driver specific options
splitting it off form the BlockdevOptionsGenericFormat. The only option
'bottom' node in the structure denotes an image file that limits the
COR operations in the backing chain.
We are going to use the
The code already don't freeze base node and we try to make it prepared
for the situation when base node is changed during the operation. In
other words, block-stream doesn't own base node.
Let's introduce a new interface which should replace the current one,
which will in better relations with the
From: Andrey Shinkevich
Provide API for insertion a node to backing chain.
Suggested-by: Max Reitz
Signed-off-by: Andrey Shinkevich
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
include/block/block.h | 2 ++
block.c | 25 +
2 files changed, 27 insertion
From: Andrey Shinkevich
Provide the possibility to pass the 'filter-node-name' parameter to the
block-stream job as it is done for the commit block job.
Signed-off-by: Andrey Shinkevich
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
qapi/block-core.json | 6 ++
include/block/bloc
From: Andrey Shinkevich
Provide API for the COR-filter removal. Also, drop the filter child
permissions for an inactive state when the filter node is being
removed.
To insert the filter, the block generic layer function
bdrv_insert_node() can be used.
The new function bdrv_cor_filter_drop() may b
From: Andrey Shinkevich
The test case #310 is similar to #216 by Max Reitz. The difference is
that the test #310 involves a bottom node to the COR filter driver.
Signed-off-by: Andrey Shinkevich
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/310 | 114 +++
From: Andrey Shinkevich
Add support for the recently introduced functions
bdrv_co_preadv_part()
and
bdrv_co_pwritev_part()
to the COR-filter driver.
Signed-off-by: Andrey Shinkevich
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
block/copy-on-read.c | 28
1 file ch
Hi all!
I decided to post v14 myself, to show how to keep the test with parallel
stream jobs.
So, main addition in v14 is "bottom" argument for stream job. Next week
I'll send a follow-up with deprecation for old "base" API.
Also, I already finished my work on updating permissions, so that we
do
The SEV FW >= 0.23 added a new command that can be used to query the
attestation report containing the SHA-256 digest of the guest memory
and VMSA encrypted with the LAUNCH_UPDATE and sign it with the PEK.
Note, we already have a command (LAUNCH_MEASURE) that can be used to
query the SHA-256 diges
I still think we should keep dropped iotest by introducing "bottom" interface
for stream job. And deprecate old interfaces.
Patch is better than arguing, so I decided to try it myself. Now I'm close to
complete v14, so, will send it soon.
02.12.2020 21:30, Andrey Shinkevich wrote:
The previous
On Fri, 4 Dec 2020 19:32:05 +0100
Greg Kurz wrote:
>
> That's all for now.
>
Just one last item. I'm observing failures with nvram in the guest:
[root@vir76 ~]# nvram --print-config
[ 88.179444] nvram[936]: unhandled signal 11 at 7fffc83a nip
00012d802110 lr 00012d802118 cod
On 12/4/20 10:53 AM, Sergio Lopez wrote:
> When switching between AIO contexts we need to me make sure that both
> recv_coroutine and send_coroutine are not scheduled to run. Otherwise,
> QEMU may crash while attaching the new context with an error like
> this one:
>
> aio_co_schedule: Co-routine
Alexander Graf writes:
> We will need more than a single field for hvf going forward. To keep
> the global vcpu struct uncluttered, let's allocate a special hvf vcpu
> struct, similar to how hax does it.
>
> Signed-off-by: Alexander Graf
> Reviewed-by: Roman Bolshakov
> Tested-by: Roman Bolsh
On Thu, Dec 03, 2020 at 10:18:14AM -0800, Peter Collingbourne wrote:
> On Thu, Dec 3, 2020 at 2:39 AM Roman Bolshakov wrote:
> >
> > On Wed, Dec 02, 2020 at 08:04:06PM +0100, Alexander Graf wrote:
> > > From: Peter Collingbourne
> > >
> > > Sleep on WFI until the VTIMER is due but allow ourselves
On 12/4/20 6:37 PM, Eduardo Habkost wrote:
> On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote:
>> On 11/30/20 3:35 AM, Claudio Fontana wrote:
>>> From: Eduardo Habkost
>>>
>>> Signed-off-by: Eduardo Habkost
>>> ---
>>> accel/tcg/cputlb.c | 6 +++---
>>> accel/
Alexander Graf writes:
> Now that we have all logic in place that we need to handle
> Hypervisor.framework
> on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we
> can build it.
>
> Signed-off-by: Alexander Graf
>
> ---
>
> v1 -> v2:
>
> - Fix build on 32bit arm
>
>
On 12/4/20 11:08 AM, Cornelia Huck wrote:
On Fri, 4 Dec 2020 11:05:34 -0300
Wainer dos Santos Moschetta wrote:
Hi,
On 12/4/20 9:14 AM, Cornelia Huck wrote:
Hotplug a virtio-net-ccw device, and then hotunplug it again.
Signed-off-by: Cornelia Huck
---
v1->v2:
- switch device id
- clear o
On 12/4/20 6:10 PM, Philippe Mathieu-Daudé wrote:
> On 11/30/20 3:35 AM, Claudio Fontana wrote:
>> From: Eduardo Habkost
>>
>> The TCG-specific CPU methods will be moved to a separate struct,
>> to make it easier to move accel-specific code outside generic CPU
>> code in the future. Start by movi
On 12/4/20 7:04 PM, Claudio Fontana wrote:
> On 12/4/20 6:28 PM, Eduardo Habkost wrote:
>> On Fri, Dec 04, 2020 at 06:10:49PM +0100, Philippe Mathieu-Daudé wrote:
>>> On 11/30/20 3:35 AM, Claudio Fontana wrote:
From: Eduardo Habkost
The TCG-specific CPU methods will be moved to a se
On Tue, 13 Oct 2020 13:19:11 +1100
Alexey Kardashevskiy wrote:
> The PAPR platform which describes an OS environment that's presented by
> a combination of a hypervisor and firmware. The features it specifies
> require collaboration between the firmware and the hypervisor.
>
> Since the beginnin
On 12/4/20 6:37 PM, Eduardo Habkost wrote:
> On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote:
>> On 11/30/20 3:35 AM, Claudio Fontana wrote:
>>> From: Eduardo Habkost
>>>
>>> Signed-off-by: Eduardo Habkost
>>> ---
>>> accel/tcg/cputlb.c | 6 +++---
>>> accel/
On 12/4/20 9:36 AM, Stephane Duverger wrote:
> Hello,
>
> While looking at tcg/i386/tcg-target.c.inc:tcg_out_qemu_st(), I
> discovered that the TCG generates a call to a store helper at the end
> of the TB which is executed on TLB miss and get back to the remaining
> translated ops. I tried to mim
On 12/4/20 6:28 PM, Eduardo Habkost wrote:
> On Fri, Dec 04, 2020 at 06:10:49PM +0100, Philippe Mathieu-Daudé wrote:
>> On 11/30/20 3:35 AM, Claudio Fontana wrote:
>>> From: Eduardo Habkost
>>>
>>> The TCG-specific CPU methods will be moved to a separate struct,
>>> to make it easier to move accel
On Fri, Dec 04, 2020 at 07:07:09PM +0100, Claudio Fontana wrote:
> On 12/4/20 7:04 PM, Claudio Fontana wrote:
> > On 12/4/20 6:28 PM, Eduardo Habkost wrote:
> >> On Fri, Dec 04, 2020 at 06:10:49PM +0100, Philippe Mathieu-Daudé wrote:
> >>> On 11/30/20 3:35 AM, Claudio Fontana wrote:
> From: Ed
On 12/4/20 7:14 PM, Claudio Fontana wrote:
> On 12/4/20 7:00 PM, Philippe Mathieu-Daudé wrote:
>> On 12/4/20 6:37 PM, Eduardo Habkost wrote:
>>> On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote:
On 11/30/20 3:35 AM, Claudio Fontana wrote:
> From: Eduardo Habkost
On 12/4/20 7:00 PM, Philippe Mathieu-Daudé wrote:
> On 12/4/20 6:37 PM, Eduardo Habkost wrote:
>> On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote:
>>> On 11/30/20 3:35 AM, Claudio Fontana wrote:
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
---
>>
On Fri, Dec 04, 2020 at 05:07:21PM +0100, Paolo Bonzini wrote:
> Il ven 4 dic 2020, 14:54 Claudio Fontana ha scritto:
>
> > On 11/30/20 3:35 AM, Claudio Fontana wrote:
> > > Hi all, this is v7 of the i386 cleanup,
> >
> > This is fairly broken still and I am fixing it up,
> >
> > but a question a
On 12/4/20 11:23 AM, Philippe Mathieu-Daudé wrote:
> On 12/4/20 5:30 PM, Richard Henderson wrote:
>> On 12/2/20 12:44 PM, Philippe Mathieu-Daudé wrote:
>>> Extract the logic initialization of the MSA registers from
>>> the generic initialization.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé
>>> -
On Fri, Dec 04, 2020 at 06:10:49PM +0100, Philippe Mathieu-Daudé wrote:
> On 11/30/20 3:35 AM, Claudio Fontana wrote:
> > From: Eduardo Habkost
> >
> > The TCG-specific CPU methods will be moved to a separate struct,
> > to make it easier to move accel-specific code outside generic CPU
> > code i
On 12/2/20 12:44 PM, Philippe Mathieu-Daudé wrote:
> Commits 863f264d10f ("add msa_reset(), global msa register") and
> cb269f273fd ("fix multiple TCG registers covering same data")
> removed the FPU scalar registers and replaced them by aliases to
> the MSA vector registers.
> While this might be
On 12/4/20 5:07 PM, Paolo Bonzini wrote:
> Il ven 4 dic 2020, 14:54 Claudio Fontana ha scritto:
>
>> On 11/30/20 3:35 AM, Claudio Fontana wrote:
>>> Hi all, this is v7 of the i386 cleanup,
>>
>> This is fairly broken still and I am fixing it up,
>>
>> but a question arises while hunting bugs here
On 12/4/20 12:17 AM, Pavel Dovgalyuk wrote:
> On 03.12.2020 19:14, Peter Maydell wrote:
>> On Thu, 3 Dec 2020 at 16:10, Pavel Dovgalyuk
>> wrote:
>>>
>>> On 03.12.2020 15:30, Philippe Mathieu-Daudé wrote:
Cc'ing Pavel
On 12/1/20 4:55 PM, Peter Maydell wrote:
> On Wed, 25 Nov 20
On Fri, Dec 04, 2020 at 12:48:53AM +0100, Alexander Graf wrote:
> With Apple Silicon available to the masses, it's a good time to add support
> for driving its virtualization extensions from QEMU.
>
> This patch adds all necessary architecture specific code to get basic VMs
> working. It's still p
ping againPatchwork page: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=212983 09.11.2020, 03:02, "Alexey Kirillov" :This patch series introduces a new QMP command "query-netdev" to getinformation about currently attached backend network devices (netdevs).Also, since the "info_str" fi
On Fri, Dec 04, 2020 at 06:14:07PM +0100, Philippe Mathieu-Daudé wrote:
> On 11/30/20 3:35 AM, Claudio Fontana wrote:
> > From: Eduardo Habkost
> >
> > Signed-off-by: Eduardo Habkost
> > ---
> > accel/tcg/cputlb.c | 6 +++---
> > accel/tcg/user-exec.c | 6 +++---
> > in
On 11/30/20 3:35 AM, Claudio Fontana wrote:
> From: Eduardo Habkost
>
> Signed-off-by: Eduardo Habkost
> ---
> accel/tcg/cputlb.c | 6 +++---
> accel/tcg/user-exec.c | 6 +++---
> include/hw/core/cpu.h | 9 -
> include/hw/core/tcg-cpu-ops.h | 12 +++
On 11/30/20 3:35 AM, Claudio Fontana wrote:
> From: Eduardo Habkost
>
> The TCG-specific CPU methods will be moved to a separate struct,
> to make it easier to move accel-specific code outside generic CPU
> code in the future. Start by moving tcg_initialize().
Good idea! One minor comment below
On 11/30/20 3:35 AM, Claudio Fontana wrote:
> From: Eduardo Habkost
>
> Signed-off-by: Eduardo Habkost
> ---
> accel/tcg/cpu-exec.c| 12 ++--
> include/hw/core/cpu.h | 6 --
> include/hw/core/tcg-cpu-ops.h | 9 +
> target/alpha/cpu.c |
On 12/4/20 5:30 PM, Richard Henderson wrote:
> On 12/2/20 12:44 PM, Philippe Mathieu-Daudé wrote:
>> Extract the logic initialization of the MSA registers from
>> the generic initialization.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> target/mips/translate.c | 35 ---
it will be reused by next patch to check validity of unplug
feature.
Signed-off-by: Igor Mammedov
---
hw/isa/lpc_ich9.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 087a18d04d..da80430144 100644
--- a/hw/isa/lpc_ich9.c
++
On 11/30/20 3:35 AM, Claudio Fontana wrote:
> From: Eduardo Habkost
>
> Signed-off-by: Eduardo Habkost
> ---
> accel/tcg/cpu-exec.c | 4 ++--
> include/hw/core/cpu.h | 8
> include/hw/core/tcg-cpu-ops.h | 14 +++---
> target/arm/cpu.c | 2 +-
>
On Fri, 4 Dec 2020 at 06:17, Pavel Dovgalyuk wrote:
>
> On 03.12.2020 19:14, Peter Maydell wrote:
> > On Thu, 3 Dec 2020 at 16:10, Pavel Dovgalyuk
> > wrote:
> >>
> >> On 03.12.2020 15:30, Philippe Mathieu-Daudé wrote:
> >>> Cc'ing Pavel
> >>>
> >>> On 12/1/20 4:55 PM, Peter Maydell wrote:
> >>>
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 21
tests/data/acpi/pc/DSDT | Bin 5060 -> 5067 bytes
tests/data/acpi/pc/DSDT.acpihmat| Bin 6385 -> 6392 bytes
tests/data/acpi/pc/DSDT.bridge | Bin 69
Change that will be introduced by following patch:
@@ -557,6 +557,8 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT",
0x0001)
CINS, 1,
CRMV, 1,
CEJ0, 1,
+, 1,
+CEJF, 1,
Off
On Fri, Dec 04, 2020 at 12:48:57AM +0100, Alexander Graf wrote:
> Now that we have working system register sync, we push more target CPU
> properties into the virtual machine. That might be useful in some
> situations, but is not the typical case that users want.
>
> So let's add a -cpu host optio
From: Cornelia Huck
Add 6.0 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
Signed-off-by: Igor Mammedov
---
include/hw/boards.h| 3 +++
include/hw/i386/pc.h | 3 +++
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/
On Fri, Dec 04, 2020 at 12:48:54AM +0100, Alexander Graf wrote:
> Now that we have all logic in place that we need to handle
> Hypervisor.framework
> on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we
> can build it.
>
Reviewed-by: Roman Bolshakov
on x86:
Tested-by: R
On Fri, Nov 20, 2020 at 5:04 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 11/19/20 12:35 PM, Richard Henderson wrote:
> > On 11/18/20 12:29 AM, frank.ch...@sifive.com wrote:
> >> +static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
> >> +{
> >> +REQUIRE_EXT(ctx, RVB);
Changelog:
since RFC:
- split one big patch on smaller chunks
- clear bit #4 in CPU eject
- drop bit #4 toggle semantics and let it set only to 1 from guest side
- do not allow unplug without hotplug
- update expected ACPI tables to let CI pass
It's QEMU side to support CPU hot-unplug w
Adds bit #4 to status/control field of CPU hotplug MMIO interface.
New bit will be used OSPM to mark CPUs as pending for removal by firmware,
when it calls _EJ0 method on CPU device node. Later on, when firmware
sees this bit set, it will perform CPU eject which will clear bit #4
as well.
Signed-o
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 1f5c211245..9036e5594c 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -96,6 +96,7 @@ typedef struct AcpiPmInfo {
bo
On Fri, Dec 04, 2020 at 12:48:46AM +0100, Alexander Graf wrote:
> Now that Apple Silicon is widely available, people are obviously excited
> to try and run virtualized workloads on them, such as Linux and Windows.
>
> This patch set implements a fully functional version to get the ball
> going on
if firmware and QEMU negotiated CPU hotunplug support, generate
_EJ0 method so that it will mark CPU for removal by firmware and
pass control to it by triggering SMI.
Signed-off-by: Igor Mammedov
---
include/hw/acpi/cpu.h | 1 +
hw/acpi/cpu.c | 15 +--
hw/i386/acpi-build.c
Keep CPU hotunplug with SMI disabled on 5.2 and older and enable
it by default on newer machine types.
Signed-off-by: Igor Mammedov
---
v1:
- ensure that unplug can't be enabled without hotplug (Laszlo)
---
hw/i386/pc.c | 4 +++-
hw/isa/lpc_ich9.c | 8 +++-
2 files changed, 10 inserti
On Fri, Dec 04, 2020 at 12:48:56AM +0100, Alexander Graf wrote:
> We currently only support GICv2 emulation. To also support GICv3, we will
> need to pass a few system registers into their respective handler functions.
>
> This patch adds handling for all of the required system registers, so that
On 12/2/20 12:44 PM, Philippe Mathieu-Daudé wrote:
> +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool
> if_not)
> +{
> +check_msa_access(ctx);
> +
> +if (ctx->hflags & MIPS_HFLAG_BMASK) {
> +generate_exception_end(ctx, EXCP_RI);
> +return true;
> +
On Fri, Dec 04, 2020 at 12:48:55AM +0100, Alexander Graf wrote:
> From: Peter Collingbourne
>
> Sleep on WFI until the VTIMER is due but allow ourselves to be woken
> up on IPI.
>
> In this implementation IPI is blocked on the CPU thread at startup and
> pselect() is used to atomically unblock t
On Fri, 4 Dec 2020 16:44:14 +1100
David Gibson wrote:
> The default behaviour for virtio devices is not to use the platforms normal
> DMA paths, but instead to use the fact that it's running in a hypervisor
> to directly access guest memory. That doesn't work if the guest's memory
> is protecte
The NVMe driver does not support image creation.
The full drive has to be passed to the guest.
Before:
$ qemu-img create -f raw nvme://:04:00.0/1 20G
Formatting 'nvme://:04:00.0/1', fmt=raw size=21474836480
$ qemu-img info nvme://:04:00.0/1
image: nvme://:04:00.0/1
file
On 12/4/20 10:53 AM, Sergio Lopez wrote:
> On dataplane start, acquire the new AIO context before calling
> 'blk_set_aio_context', releasing it immediately afterwards. This
> prevents reaching the AIO context attach/detach notifier functions
> without having acquired it first.
>
> It was also the
Previously if an interrupt occured during the claim process (after the
interrupt is claimed but before it's completed) it would never be
cleared.
This patch ensures that we also clear the hidden_pending bits as well.
Signed-off-by: Alistair Francis
---
hw/intc/ibex_plic.c | 13 ++---
1 f
On 12/2/20 12:44 PM, Philippe Mathieu-Daudé wrote:
> The gen_msa*() methods don't use the "CPUMIPSState *env"
> argument. Remove it to simplify.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.c | 57 -
> 1 file changed, 28 insertio
Hello,
While looking at tcg/i386/tcg-target.c.inc:tcg_out_qemu_st(), I
discovered that the TCG generates a call to a store helper at the end
of the TB which is executed on TLB miss and get back to the remaining
translated ops. I tried to mimick this behavior around the fast path
(right between tcg
On 12/2/20 12:44 PM, Philippe Mathieu-Daudé wrote:
> Extract the logic initialization of the MSA registers from
> the generic initialization.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.c | 35 ---
> 1 file changed, 20 insertions(+), 15
When switching between AIO contexts we need to me make sure that both
recv_coroutine and send_coroutine are not scheduled to run. Otherwise,
QEMU may crash while attaching the new context with an error like
this one:
aio_co_schedule: Co-routine was already scheduled in 'aio_co_schedule'
To achiev
On dataplane start, acquire the new AIO context before calling
'blk_set_aio_context', releasing it immediately afterwards. This
prevents reaching the AIO context attach/detach notifier functions
without having acquired it first.
It was also the only place where 'blk_set_aio_context' was called wit
Il ven 4 dic 2020, 14:54 Claudio Fontana ha scritto:
> On 11/30/20 3:35 AM, Claudio Fontana wrote:
> > Hi all, this is v7 of the i386 cleanup,
>
> This is fairly broken still and I am fixing it up,
>
> but a question arises while hunting bugs here.
>
> Silent bugs are introduced when trying to us
On Fri, Dec 04, 2020 at 12:48:52AM +0100, Alexander Graf wrote:
> The hooks we have that call us after reset, init and loadvm really all
> just want to say "The reference of all register state is in the QEMU
> vcpu struct, please push it".
>
> We already have a working pushing mechanism though cal
On Thu 03 Dec 2020 11:27:12 PM CET, Vladimir Sementsov-Ogievskiy wrote:
> Move bdrv_is_inserted() calls into callers.
>
> We are going to make bdrv_check_byte_request() a clean thing.
> bdrv_is_inserted() is not about checking the request, it's about
> checking the bs. So, it should be separate.
>
On Thu 03 Dec 2020 11:27:11 PM CET, Vladimir Sementsov-Ogievskiy wrote:
> This simplifies following commit.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Alberto Garcia
Berto
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