Re: [PATCH] drivers/virt: vmgenid: add vm generation id driver

On Sat, Oct 17, 2020 at 8:44 AM Willy Tarreau wrote: > On Sat, Oct 17, 2020 at 07:52:48AM +0200, Jann Horn wrote: > > On Sat, Oct 17, 2020 at 7:37 AM Willy Tarreau wrote: > > > On Sat, Oct 17, 2020 at 07:01:31AM +0200, Jann Horn wrote: > > > > Microsoft's documentation > > > > (http://go.microsof

Re: [PATCH v2 2/3] grackle: use qdev gpios for PCI IRQs

On Fri, Oct 16, 2020 at 07:53:10AM +0100, Mark Cave-Ayland wrote: > On 16/10/2020 07:45, Howard Spoelstra wrote: > > > Hi, > > > > I see compilation of the current ppc-for-5.2 branch fail with: > > > > ../hw/pci-host/grackle.c: In function ‘grackle_realize’: > > ../hw/pci-host/grackle.c:68:11: e

Re: [PATCH v2 1/3] macio: don't reference serial_hd() directly within the device

On Fri, Oct 16, 2020 at 08:00:06AM +0100, Mark Cave-Ayland wrote: > On 16/10/2020 01:16, David Gibson wrote: > > > On Tue, Oct 13, 2020 at 12:49:20PM +0100, Mark Cave-Ayland wrote: > > > Instead use qdev_prop_set_chr() to configure the ESCC serial chardevs at > > > the > > > Mac Old World and New

Re: [PATCH] drivers/virt: vmgenid: add vm generation id driver

On Sat, Oct 17, 2020 at 07:52:48AM +0200, Jann Horn wrote: > On Sat, Oct 17, 2020 at 7:37 AM Willy Tarreau wrote: > > On Sat, Oct 17, 2020 at 07:01:31AM +0200, Jann Horn wrote: > > > Microsoft's documentation > > > (http://go.microsoft.com/fwlink/?LinkId=260709) says that the VM > > > Generation I

Re: [PATCH] drivers/virt: vmgenid: add vm generation id driver

On Sat, Oct 17, 2020 at 07:01:31AM +0200, Jann Horn wrote: > Microsoft's documentation > (http://go.microsoft.com/fwlink/?LinkId=260709) says that the VM > Generation ID that we get after a fork "is a 128-bit, > cryptographically random integer value". If multiple people use the > same image, it gu

Re: [PATCH] drivers/virt: vmgenid: add vm generation id driver

On 16 Oct 2020, at 21:02, Jann Horn wrote: On Sat, Oct 17, 2020 at 5:36 AM Willy Tarreau wrote: But in userspace, we just need a simple counter. There's no need for us to worry about anything else, like timestamps or whatever. If we repeatedly fork a paused VM, the forked VMs will see the sam

Re: [PATCH] drivers/virt: vmgenid: add vm generation id driver

On Sat, Oct 17, 2020 at 03:40:08AM +0200, Jann Horn wrote: > [adding some more people who are interested in RNG stuff: Andy, Jason, > Theodore, Willy Tarreau, Eric Biggers. also linux-api@, because this > concerns some pretty fundamental API stuff related to RNG usage] > > On Fri, Oct 16, 2020 at

Re: [PATCH] drivers/virt: vmgenid: add vm generation id driver

On 16 Oct 2020, at 22:01, Jann Horn wrote: On Sat, Oct 17, 2020 at 6:34 AM Colm MacCarthaigh wrote: For user-space, even a single bit would do. We added MADVISE_WIPEONFORK so that userspace libraries can detect fork()/clone() robustly, for the same reasons. It just wipes a page as the in

Re: [PATCH] drivers/virt: vmgenid: add vm generation id driver

On Sat, Oct 17, 2020 at 7:37 AM Willy Tarreau wrote: > On Sat, Oct 17, 2020 at 07:01:31AM +0200, Jann Horn wrote: > > Microsoft's documentation > > (http://go.microsoft.com/fwlink/?LinkId=260709) says that the VM > > Generation ID that we get after a fork "is a 128-bit, > > cryptographically rando

[Bug 1891748] Re: qemu-arm-static 5.1 can't run gcc

This has been fixed in mainline, probably commit 8ef618859c379fdce81c91bc93e0574e36ea76ff. ** Changed in: qemu Status: New => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/18917

Re: [PATCH] drivers/virt: vmgenid: add vm generation id driver

On Sat, Oct 17, 2020 at 6:34 AM Colm MacCarthaigh wrote: > On 16 Oct 2020, at 21:02, Jann Horn wrote: > > On Sat, Oct 17, 2020 at 5:36 AM Willy Tarreau wrote: > > But in userspace, we just need a simple counter. There's no need for > > us to worry about anything else, like timestamps or whatever.

[PATCH v3 16/18] migration/rdma: add rdma_channel into Migrationstate field

Multifd RDMA is need to poll when we send data, record it. Signed-off-by: Chuan Zheng --- migration/migration.c | 1 + migration/migration.h | 1 + migration/rdma.c | 14 ++ 3 files changed, 16 insertions(+) diff --git a/migration/migration.c b/migration/migration.c index 706

[PATCH v3 18/18] migration/rdma: RDMA cleanup for multifd migration

Signed-off-by: Chuan Zheng --- migration/multifd.c | 6 ++ migration/multifd.h | 1 + migration/rdma.c| 16 +++- 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/migration/multifd.c b/migration/multifd.c index c4d90ef..f548122 100644 --- a/migration/multifd.c +

[PATCH v3 03/18] migration/rdma: create multifd_setup_ops for Tx/Rx thread

Create multifd_setup_ops for TxRx thread, no logic change. Signed-off-by: Chuan Zheng --- migration/multifd.c | 44 +++- migration/multifd.h | 7 +++ 2 files changed, 46 insertions(+), 5 deletions(-) diff --git a/migration/multifd.c b/migration/multi

[PATCH v3 05/18] migration/rdma: do not need sync main for rdma

Signed-off-by: Zhimin Feng Signed-off-by: Chuan Zheng --- migration/multifd.c | 8 1 file changed, 8 insertions(+) diff --git a/migration/multifd.c b/migration/multifd.c index 0d494df..8ccfd46 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -580,6 +580,10 @@ void multifd_

[PATCH v3 11/18] migration/rdma: record host_port for multifd RDMA

Signed-off-by: Chuan Zheng --- migration/migration.c | 1 + migration/migration.h | 3 +++ migration/rdma.c | 3 +++ 3 files changed, 7 insertions(+) diff --git a/migration/migration.c b/migration/migration.c index be6166a..7061410 100644 --- a/migration/migration.c +++ b/migration/migratio

[PATCH v3 12/18] migration/rdma: Create the multifd send channels for RDMA

Signed-off-by: Chuan Zheng --- migration/multifd.c | 4 ++-- migration/multifd.h | 2 ++ migration/rdma.c| 56 + 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/migration/multifd.c b/migration/multifd.c index 03f3a1e..9439b

[PATCH v3 13/18] migration/rdma: Add the function for dynamic page registration

Add the 'qemu_rdma_registration' function, multifd send threads call it to register memory. Signed-off-by: Zhimin Feng Signed-off-by: Chuan Zheng --- migration/rdma.c | 51 +++ 1 file changed, 51 insertions(+) diff --git a/migration/rdma.c b/migr

[PATCH v3 02/18] migration/rdma: judge whether or not the RDMA is used for migration

Add enabled_rdma_migration into MigrationState to judge whether or not the RDMA is used for migration. Signed-off-by: Zhimin Feng Signed-off-by: Chuan Zheng --- migration/migration.c | 13 + migration/migration.h | 6 ++ 2 files changed, 19 insertions(+) diff --git a/migration

[PATCH v3 10/18] migration/rdma: Create the multifd recv channels for RDMA

We still don't transmit anything through them, and we only build the RDMA connections. Signed-off-by: Zhimin Feng Signed-off-by: Chuan Zheng --- migration/rdma.c | 70 ++-- 1 file changed, 68 insertions(+), 2 deletions(-) diff --git a/migrati

[PATCH v3 09/18] migration/rdma: add multifd_rdma_load_setup() to setup multifd rdma

Signed-off-by: Chuan Zheng --- migration/rdma.c | 52 1 file changed, 52 insertions(+) diff --git a/migration/rdma.c b/migration/rdma.c index ad4e4ba..2baa933 100644 --- a/migration/rdma.c +++ b/migration/rdma.c @@ -4010,6 +4010,48 @@ static v

[PATCH v3 17/18] migration/rdma: send data for both rdma-pin-all and NOT rdma-pin-all mode

Signed-off-by: Zhimin Feng Signed-off-by: Chuan Zheng --- migration/rdma.c | 67 +++- 1 file changed, 62 insertions(+), 5 deletions(-) diff --git a/migration/rdma.c b/migration/rdma.c index 327f80f..519fa7a 100644 --- a/migration/rdma.c +++ b/

[PATCH v3 00/18] Support Multifd for RDMA migration

Now I continue to support multifd for RDMA migration based on my colleague zhiming's work:) The previous RFC patches is listed below: v1: https://www.mail-archive.com/qemu-devel@nongnu.org/msg669455.html v2: https://www.mail-archive.com/qemu-devel@nongnu.org/msg679188.html As descried in previous

[PATCH v3 15/18] migration/rdma: only register the memory for multifd channels

All data is sent by multifd Channels, so we only register its for multifd channels and main channel don't register its. Signed-off-by: Zhimin Feng Signed-off-by: Chuan Zheng --- migration/rdma.c | 8 1 file changed, 8 insertions(+) diff --git a/migration/rdma.c b/migration/rdma.c inde

[PATCH v3 08/18] migration/rdma: export getQIOChannel to get QIOchannel in rdma

Signed-off-by: Zhimin Feng Signed-off-by: Chuan Zheng --- migration/qemu-file.c | 5 + migration/qemu-file.h | 1 + 2 files changed, 6 insertions(+) diff --git a/migration/qemu-file.c b/migration/qemu-file.c index be21518..37f6201 100644 --- a/migration/qemu-file.c +++ b/migration/qemu-file

[PATCH v3 14/18] migration/rdma: register memory for multifd RDMA channels

Signed-off-by: Zhimin Feng Signed-off-by: Chuan Zheng --- migration/multifd.c | 3 ++ migration/rdma.c| 94 +++-- 2 files changed, 95 insertions(+), 2 deletions(-) diff --git a/migration/multifd.c b/migration/multifd.c index 9439b3c..c4d90ef

[PATCH v3 01/18] migration/rdma: add the 'migrate_use_rdma_pin_all' function

Signed-off-by: Zhimin Feng Signed-off-by: Chuan Zheng --- migration/migration.c | 9 + migration/migration.h | 1 + 2 files changed, 10 insertions(+) diff --git a/migration/migration.c b/migration/migration.c index 0575ecb..64ae417 100644 --- a/migration/migration.c +++ b/migration/migr

[PATCH v3 06/18] migration/rdma: export MultiFDSendParams/MultiFDRecvParams

MultiFDSendParams and MultiFDRecvParams is need for rdma, export it Signed-off-by: Zhimin Feng Signed-off-by: Chuan Zheng --- migration/multifd.c | 26 ++ migration/multifd.h | 2 ++ 2 files changed, 28 insertions(+) diff --git a/migration/multifd.c b/migration/multifd

[PATCH v3 04/18] migration/rdma: add multifd_setup_ops for rdma

Signed-off-by: Chuan Zheng --- migration/multifd.c | 6 migration/multifd.h | 4 +++ migration/rdma.c| 82 + 3 files changed, 92 insertions(+) diff --git a/migration/multifd.c b/migration/multifd.c index 1f82307..0d494df 100644 --- a

[PATCH v3 07/18] migration/rdma: add rdma field into multifd send/recv param

Note we do want to export any rdma struct, take void * instead. Signed-off-by: Chuan Zheng --- migration/multifd.h | 8 1 file changed, 8 insertions(+) diff --git a/migration/multifd.h b/migration/multifd.h index 2f4e585..ff80bd5 100644 --- a/migration/multifd.h +++ b/migration/multifd

Re: [PATCH] drivers/virt: vmgenid: add vm generation id driver

On Sat, Oct 17, 2020 at 5:36 AM Willy Tarreau wrote: > On Sat, Oct 17, 2020 at 03:40:08AM +0200, Jann Horn wrote: > > [adding some more people who are interested in RNG stuff: Andy, Jason, > > Theodore, Willy Tarreau, Eric Biggers. also linux-api@, because this > > concerns some pretty fundamental

[PATCH 3/4] target/s390x: Improve cc computation for SUBTRACT LOGICAL

The resulting cc is only dependent on the result and the borrow-out. So save those things rather than the inputs. Borrow-out for 64-bit inputs is had via tcg_gen_sub2_i64 directly into cc_src. Borrow-out for 32-bit inputs is had via extraction from a normal 64-bit sub (with zero-extended inputs)

[PATCH 2/4] target/s390x: Improve ADD LOGICAL WITH CARRY

Now that ADD LOGICAL outputs carry, we can use that as input directly. It also means we can re-use CC_OP_ZC and produce an output carry directly from ADD LOGICAL WITH CARRY. Signed-off-by: Richard Henderson --- target/s390x/internal.h| 2 -- target/s390x/cc_helper.c | 26 ---

[PATCH 4/4] target/s390x: Improve SUB LOGICAL WITH BORROW

Now that SUB LOGICAL outputs carry, we can use that as input directly. It also means we can re-use CC_OP_ZC and produce an output carry directly from SUB LOGICAL WITH BORROW. Signed-off-by: Richard Henderson --- target/s390x/internal.h| 2 -- target/s390x/cc_helper.c | 32

[PATCH 0/4] target/s390x: Improve carry computation

While testing the float128_muladd changes for s390x host, emulating under x86_64 of course, I noticed that the code we generate for strings of ALCGR and SLBGR is pretty awful. I realized that we were missing a trick: the output cc is based only on the output (result and carry) and so we don't need

[PATCH 1/4] target/s390x: Improve cc computation for ADD LOGICAL

The resulting cc is only dependent on the result and the carry-out. So save those things rather than the inputs. Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly into cc_src. Carry-out for 32-bit inputs is had via extraction from a normal 64-bit add (with zero-extended inputs).

Re: [PATCH] drivers/virt: vmgenid: add vm generation id driver

[adding some more people who are interested in RNG stuff: Andy, Jason, Theodore, Willy Tarreau, Eric Biggers. also linux-api@, because this concerns some pretty fundamental API stuff related to RNG usage] On Fri, Oct 16, 2020 at 4:33 PM Catangiu, Adrian Costin wrote: > - Background > > The VM Gen

[Bug 1891748] Re: qemu-arm-static 5.1 can't run gcc

Plz take a look at this issue please. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1891748 Title: qemu-arm-static 5.1 can't run gcc Status in QEMU: New Bug description: Issue discovered whil

Re: [PATCH v3 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode

On 10/16/20 3:11 PM, Alexey Baturo wrote: > Signed-off-by: Alexey Baturo > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 11 ++ > target/riscv/cpu_bits.h | 66 ++ > target/riscv/csr.c | 264 > 4 files changed, 342 insert

Re: [PATCH v3 1/5] [RISCV_PM] Add J-extension into RISC-V

On 10/16/20 3:11 PM, Alexey Baturo wrote: > Signed-off-by: Alexey Baturo > --- > target/riscv/cpu.c | 4 > target/riscv/cpu.h | 2 ++ > 2 files changed, 6 insertions(+) Reviewed-by: Richard Henderson r~

[Bug 1891748] Re: qemu-arm-static 5.1 can't run gcc

Anyone? Seriously, the problem really exists and we even made a case that reproduces it. Someone please take a look at this. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1891748 Title: qemu-arm-st

Re: [PATCH v3 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

On 10/16/20 3:11 PM, Alexey Baturo wrote: > Signed-off-by: Alexey Baturo > --- > target/riscv/insn_trans/trans_rva.c.inc | 3 +++ > target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ > target/risc

Re: [PATCH v3 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs

On 10/16/20 3:11 PM, Alexey Baturo wrote: > Signed-off-by: Alexey Baturo > --- > target/riscv/cpu.c | 19 +++ > 1 file changed, 19 insertions(+) Reviewed-by: Richard Henderson r~

Re: [PATCH v3 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

On 10/16/20 3:11 PM, Alexey Baturo wrote: > From: Anatoly Parshintsev > > Signed-off-by: Anatoly Parshintsev > --- > target/riscv/cpu.h | 19 +++ > target/riscv/translate.c | 34 -- > 2 files changed, 51 insertions(+), 2 deletions(-) Review

Re: HTIF tohost symbol size check always fails

On Fri, Oct 16, 2020 at 2:35 PM Peer Adelt wrote: > > The solution was even easier: I forgot to load the proxy kernel. As soon as I > replaced the command-line parameter "-kernel " with "-kernel > -append ", everything was working as expected. Even better, you can skip the proxy kernel. You c

Re: [PATCH v3 0/5] RISC-V Pointer Masking implementation

Patchew URL: https://patchew.org/QEMU/20201016221138.10371-1-space.monkey.deliv...@gmail.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20201016221138.10371-1-space.monkey.deliv...@gmail.com Subject: [PATCH v3 0/5

[PATCH v3 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/translate.c| 14 ++ 5 file

[PATCH v3 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d63031eb08..6ba3e98508 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -255,6 +255,25 @@ static void riscv_cpu_dum

[PATCH v3 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev --- target/riscv/cpu.h | 19 +++ target/riscv/translate.c | 34 -- 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 21e

[PATCH v3 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 11 ++ target/riscv/cpu_bits.h | 66 ++ target/riscv/csr.c | 264 4 files changed, 342 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/

[PATCH v3 0/5] RISC-V Pointer Masking implementation

Hi folks, This is third iteration of patches to support Pointer Masking for RISC-V. Most of suggestions have been addressed, however some of them not: - applying mask for return value while reading PM CSR has been kept to mask higher priv level bits - check_pm_current_disabled is not placed into

[PATCH v3 1/5] [RISCV_PM] Add J-extension into RISC-V

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 4 target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..fe6bab4a52 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -438,6 +438,9 @@ static void ris

Re: [PATCH v2 1/2] accel/tcg: Add tlb_flush_page_bits_by_mmuidx*

On Fri, 16 Oct 2020 at 22:07, Richard Henderson wrote: > > On ARM, the Top Byte Ignore feature means that only 56 bits of > the address are significant in the virtual address. We are > required to give the entire 64-bit address to FAR_ELx on fault, > which means that we do not "clean" the top byt

Re: HTIF tohost symbol size check always fails

The solution was even easier: I forgot to load the proxy kernel. As soon as I replaced the command-line parameter "-kernel " with "-kernel -append ", everything was working as expected. Without your hint about my possibly misconfigured toolchain I would have probably continued to search for t

[PATCH v2 1/2] accel/tcg: Add tlb_flush_page_bits_by_mmuidx*

On ARM, the Top Byte Ignore feature means that only 56 bits of the address are significant in the virtual address. We are required to give the entire 64-bit address to FAR_ELx on fault, which means that we do not "clean" the top byte early in TCG. This new interface allows us to flush all 256 pos

[PATCH v2 2/2] target/arm: Use tlb_flush_page_bits_by_mmuidx*

When TBI is enabled in a given regime, 56 bits of the address are significant and we need to clear out any other matching virtual addresses with differing tags. The other uses of tlb_flush_page (without mmuidx) in this file are only used by aarch32 mode. Fixes: 38d931687fa1 Reported-by: Jordan Fr

[PATCH v2 0/2] target/arm: Fix tlb flush page vs tbi

Since the FAR_ELx fix at 38d931687fa1, it is reported that page granularity flushing is broken. This makes sense, since TCG will record the entire virtual address in its TLB, not simply the 56 significant bits. With no other TCG support, the ARM backend should require 256 different page flushes to

Re: [PATCH] configure: actually disable 'git_update' mode with --disable-git-update

On Fri, Oct 2, 2020 at 9:11 AM Daniel P. Berrangé wrote: > > On Wed, Sep 30, 2020 at 09:28:54PM -0400, Dan Streetman wrote: > > On Tue, Sep 22, 2020 at 12:34 PM Daniel P. Berrangé > > wrote: > > > > > > On Wed, Jul 29, 2020 at 03:58:29PM -0400, Dan Streetman wrote: > > > > The --disable-git-upda

[PATCH] configure: replace --enable/disable-git-update with --with-git-submodules

Replace the --enable-git-update and --disable-git-update configure params with the param --with-git-submodules=(update|validate|ignore) to allow 3 options for building from a git repo. This is needed because downstream packagers, e.g. Debian, Ubuntu, etc, also keep the source code in git, but do n

Re: [PATCH 4/5] ppc405_boards: use qdev properties instead of legacy m48t59_init() function

On Fri, 16 Oct 2020, Mark Cave-Ayland wrote: Signed-off-by: Mark Cave-Ayland --- hw/ppc/ppc405_boards.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 6198ec1035..4687715b15 100644 --- a/hw/ppc/ppc405_boards.c ++

Re: [PATCH 0/5] m48t59: remove legacy init functions

Le 16/10/2020 à 20:27, Mark Cave-Ayland a écrit : This patchset is inspired by Philippe's "hw/rtc/m48t59: Simplify m48t59_init()" patchset at https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg04493.html but goes further: rather than tidy-up the legacy init functions, convert the callers to

Re: [PATCH v2 4/5] target/mips: Refactor helpers for fp comparison instructions

On 10/9/20 4:47 PM, Philippe Mathieu-Daudé wrote: Hi Aleksandar, On 10/7/20 10:37 PM, Aleksandar Markovic wrote: This change causes slighlty better performance of emulation of fp comparison instructions via better compiler optimization of refactored code. The functionality is otherwise unchange

Re: [PATCH] goldfish_rtc: re-arm the alarm after migration

On Fri, Oct 16, 2020 at 11:16 AM Laurent Vivier wrote: > > After a migration the clock offset is updated, but we also > need to re-arm the alarm if needed. > > Signed-off-by: Laurent Vivier Reviewed-by: Alistair Francis Alistair > --- > hw/rtc/goldfish_rtc.c | 2 ++ > 1 file changed, 2 inser

Re: [PULL 00/10] Block layer patches

On Thu, 15 Oct 2020 at 15:50, Kevin Wolf wrote: > > The following changes since commit 57c98ea9acdcef5021f5671efa6475a5794a51c4: > > Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201014-pull-request' > into staging (2020-10-14 13:56:06 +0100) > > are available in the Git repository at:

Re: [PATCH v11 00/12] linux-user: User support for AArch64 BTI

Patchew URL: https://patchew.org/QEMU/20201016184207.786698-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20201016184207.786698-1-richard.hender...@linaro.org Subject: [PATCH v11 00/12]

[PATCH v11 12/12] tests/tcg/aarch64: Add bti smoke tests

The note test requires gcc 10 for -mbranch-protection=standard. The mmap test uses PROT_BTI and does not require special compiler support. Acked-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v9: Expect and require gcc 10. v11: Squash mmap smoke test. --- tests

[PATCH v11 11/12] linux-user/elfload: Parse GNU_PROPERTY_AARCH64_FEATURE_1_AND

Use the new generic support for NT_GNU_PROPERTY_TYPE_0. Signed-off-by: Richard Henderson --- v11: Split out aarch64 bits from generic patch. --- linux-user/elfload.c | 48 ++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/linux-user/elflo

[PATCH v11 09/12] linux-user/elfload: Use Error for load_elf_interp

This is slightly clearer than just using strerror, though the different forms produced by error_setg_file_open and error_setg_errno isn't entirely convenient. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --g

[PATCH v11 10/12] linux-user/elfload: Parse NT_GNU_PROPERTY_TYPE_0 notes

This is generic support, with the code disabled for all targets. Signed-off-by: Richard Henderson --- v9: Only map the startup executable with BTI; anything else must be handled by the interpreter. v10: Split out preparatory patches (pmm). v11: Mirror(-ish) the kernel's code structure (pmm).

[PATCH v11 02/12] linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI

Transform the prot bit to a qemu internal page bit, and save it in the page tables. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v10: Add PAGE_BTI define (pmm). --- include/exec/cpu-all.h | 2 ++ linux-user/syscall_defs.h | 4 target/arm/cpu.h | 5 +

[PATCH v11 08/12] linux-user/elfload: Use Error for load_elf_image

This is a bit clearer than open-coding some of this with a bare c string. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 37 - 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 107a62

[PATCH v11 03/12] include/elf: Add defines related to GNU property notes for AArch64

These are all of the defines required to parse GNU_PROPERTY_AARCH64_FEATURE_1_AND, copied from binutils. Other missing defines related to other GNU program headers and notes are elided for now. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/elf.h | 22 ++

[PATCH v11 07/12] linux-user/elfload: Move PT_INTERP detection to first loop

For BTI, we need to know if the executable is static or dynamic, which means looking for PT_INTERP earlier. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 60 +++- 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/linux-user/elfl

[PATCH v11 05/12] linux-user/elfload: Fix coding style in load_elf_image

Fixing this now will clarify following patches. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 1a3150df7c..290ef70222 100644 --- a/linux-user/elfload.c ++

[PATCH v11 06/12] linux-user/elfload: Adjust iteration over phdr

The second loop uses a loop induction variable, and the first does not. Transform the first to match the second, to simplify a following patch moving code between them. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff

[PATCH v11 01/12] linux-user/aarch64: Reset btype for signals

The kernel sets btype for the signal handler as if for a call. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c ind

[PATCH v11 04/12] linux-user/elfload: Avoid leaking interp_name using GLib memory API

From: Philippe Mathieu-Daudé Fix an unlikely memory leak in load_elf_image(). Fixes: bf858897b7 ("linux-user: Re-use load_elf_image for the main binary.") Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201003174944.1972444-1-f4...@amsat.org> Signed-off-by: Richard Henderson --- linux-us

[PATCH v11 00/12] linux-user: User support for AArch64 BTI

The kernel abi for this was merged in v5.8, just as the qemu 5.1 merge window was closing, so this slipped to the next dev cycle. Changes from v10: * Include Phil's plug of interp_name memory leak. * Convert error reporting to Error api. * Mirror the kernel's code structure for parsing notes

[PATCH 5/5] m48t59: remove legacy m48t59_init() function

Now that all of the callers of this function have been switched to use qdev properties, this legacy init function can now be removed. Signed-off-by: Mark Cave-Ayland --- hw/rtc/m48t59.c | 35 --- include/hw/rtc/m48t59.h | 4 2 files changed, 39 delet

[PATCH 4/5] ppc405_boards: use qdev properties instead of legacy m48t59_init() function

Signed-off-by: Mark Cave-Ayland --- hw/ppc/ppc405_boards.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 6198ec1035..4687715b15 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -28,6 +28,8 @@

[PATCH 1/5] m48t59-isa: remove legacy m48t59_init_isa() function

This function is no longer used within the codebase. Signed-off-by: Mark Cave-Ayland --- hw/rtc/m48t59-isa.c | 25 - include/hw/rtc/m48t59.h | 2 -- 2 files changed, 27 deletions(-) diff --git a/hw/rtc/m48t59-isa.c b/hw/rtc/m48t59-isa.c index cae315e488..dc21fb10a5

[PATCH 2/5] sun4m: use qdev properties instead of legacy m48t59_init() function

Signed-off-by: Mark Cave-Ayland --- hw/sparc/sun4m.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 54a2b2f9ef..a9bb60f2b2 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -966,7 +966,13 @@ static void sun4m_hw_init(cons

[PATCH 3/5] sun4u: use qdev properties instead of legacy m48t59_init() function

Signed-off-by: Mark Cave-Ayland --- hw/sparc64/sun4u.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index ad5ca2472a..05e659c8a4 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -671,10 +671,13 @@ static void sun4uv_

[PATCH 0/5] m48t59: remove legacy init functions

This patchset is inspired by Philippe's "hw/rtc/m48t59: Simplify m48t59_init()" patchset at https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg04493.html but goes further: rather than tidy-up the legacy init functions, convert the callers to use qdev properties directly so they can simply be

[PATCH] goldfish_rtc: re-arm the alarm after migration

After a migration the clock offset is updated, but we also need to re-arm the alarm if needed. Signed-off-by: Laurent Vivier --- hw/rtc/goldfish_rtc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c index 0f4e8185a796..e07ff0164e0c 100644 --- a

Re: HTIF tohost symbol size check always fails

On Fri, Oct 16, 2020 at 7:59 AM Peer Adelt wrote: > > Hi, > > I have a problem with the RISC-V HTIF device. > > Every binary I have compiled for Spike on riscv32 fails with the following > error message: "HTIF tohost must be 8 bytes" > > This happens regardless of which program I have translated

Re: io_uring possibly the culprit for qemu hang (linux-5.4.y)

On 10/16/20 12:04 PM, Ju Hyung Park wrote: > A small update: > > As per Stefano's suggestion, disabling io_uring support from QEMU from > the configuration step did fix the problem and I'm no longer having > hangs. > > Looks like it __is__ an io_uring issue :( Would be great if you could try 5.4

Re: io_uring possibly the culprit for qemu hang (linux-5.4.y)

A small update: As per Stefano's suggestion, disabling io_uring support from QEMU from the configuration step did fix the problem and I'm no longer having hangs. Looks like it __is__ an io_uring issue :( Btw, I used liburing fe50048 for linking QEMU. Thanks. On Fri, Oct 2, 2020 at 4:35 PM Ste

Re: [PATCH v2] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry

On Fri, Oct 16, 2020 at 10:10 AM Ivan Griffin wrote: > > Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU > reporting a STORE/AMO Access Fault. > > This region is used by the PolarFire SoC port of U-Boot to > interact with the FPGA system controller. > > Signed-off-by: Ivan Griffin

Re: [RFC PATCH v3] target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)

On 10/16/20 6:33 AM, Philippe Mathieu-Daudé wrote: > Per "MIPS32 34K Processor Core Family Software User's Manual, > Revision 01.13" page 8 in "Joint TLB (JTLB)" section: > > "The JTLB is a fully associative TLB cache containing 16, 32, >or 64-dual-entries mapping up to 128 virtual pages to

Re: [PATCH v3 00/15] raspi: add the bcm2835 cprman clock manager

On 10/10/20 3:57 PM, Luc Michel wrote: [...] Hi, This series add the BCM2835 CPRMAN clock manager peripheral to the Raspberry Pi machine. Series: Tested-by: Philippe Mathieu-Daudé

[PATCH v3 11/13] block/qcow2: read_cache_sizes: return status value

It's better to return status together with setting errp. It allows to reduce error propagation. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Greg Kurz Reviewed-by: Alberto Garcia --- block/qcow2.c | 19 +-- 1 file changed, 9 insertions(+), 10 deletions(-) diff --gi

[PATCH v3 12/13] block/qcow2: simplify qcow2_co_invalidate_cache()

qcow2_do_open correctly sets errp on each failure path. So, we can simplify code in qcow2_co_invalidate_cache() and drop explicit error propagation. Add ERRP_GUARD() as mandated by the documentation in include/qapi/error.h so that error_prepend() is actually called even if errp is &error_fatal. S

[PATCH v3 13/13] block/qed: bdrv_qed_do_open: deal with errp

Set errp always on failure. Generic bdrv_open_driver supports driver functions which can return negative value and forget to set errp. That's a strange thing.. Let's improve bdrv_qed_do_open to not behave this way. This allows to simplify code in bdrv_qed_co_invalidate_cache(). Signed-off-by: Vlad

[PATCH v3 09/13] block/qcow2-bitmap: improve qcow2_load_dirty_bitmaps() interface

It's recommended for bool functions with errp to return true on success and false on failure. Non-standard interfaces don't help to understand the code. The change is also needed to reduce error propagation. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Alberto Garcia Reviewed-by: Gre

Re: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property

On 10/15/20 11:56 AM, Victor Kamensky (kamensky) via wrote: > Is possible to come back to 34Kf route, doing > very small localized very well defined change > of bumping TLBs number for model that we know > works well for us? Yes, thanks for testing. I think we should also add a property to enable

[PATCH v3 06/13] block/mirror: drop extra error propagation in commit_active_start()

Let's check return value of mirror_start_job to check for failure instead of local_err. Rename ret to job, as ret is usually integer variable. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Greg Kurz Reviewed-by: Alberto Garcia --- block/mirror.c | 12 +--- 1 file changed, 5

[PATCH v3 10/13] block/qcow2-bitmap: return status from qcow2_store_persistent_dirty_bitmaps

It's better to return status together with setting errp. It makes possible to avoid error propagation. While being here, put ERRP_GUARD() to fix error_prepend(errp, ...) usage inside qcow2_store_persistent_dirty_bitmaps() (see the comment above ERRP_GUARD() definition in include/qapi/error.h) Sig

Re: [PATCH v2 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode

On 10/15/20 11:05 AM, Alexey Baturo wrote: > Meanwhile, do you think applying **MTE *masks while reading CSR values is a > good solution for now? Yes. r~

[PATCH v3 05/13] block: drop extra error propagation for bdrv_set_backing_hd

bdrv_set_backing_hd now returns status, let's use it. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Greg Kurz Reviewed-by: Alberto Garcia --- block.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/block.c b/block.c index 7b6818c681..a35dc80dd4 100644 --- a

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