On 8/12/20 11:32 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana
> ---
> softmmu/cpus.c | 7 ---
> 1 file changed, 7 deletions(-)
Reviewed-by: Richard Henderson
r~
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +CpusAccel hvf_cpus = {
> +.create_vcpu_thread = hvf_start_vcpu_thread,
> +
> +.synchronize_post_reset = hvf_cpu_synchronize_post_reset,
> +.synchronize_post_init = hvf_cpu_synchronize_post_init,
> +.synchronize_state = hvf_cpu_synchroni
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +CpusAccel whpx_cpus = {
> +.create_vcpu_thread = whpx_start_vcpu_thread,
> +.kick_vcpu_thread = whpx_kick_vcpu_thread,
> +
> +.synchronize_post_reset = whpx_cpu_synchronize_post_reset,
> +.synchronize_post_init = whpx_cpu_synchronize_po
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +CpusAccel hax_cpus = {
> +.create_vcpu_thread = hax_start_vcpu_thread,
> +.kick_vcpu_thread = hax_kick_vcpu_thread,
> +
> +.synchronize_post_reset = hax_cpu_synchronize_post_reset,
> +.synchronize_post_init = hax_cpu_synchronize_post_in
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +
> +CpusAccel kvm_cpus = {
> +.create_vcpu_thread = kvm_start_vcpu_thread,
> +
> +.synchronize_post_reset = kvm_cpu_synchronize_post_reset,
> +.synchronize_post_init = kvm_cpu_synchronize_post_init,
> +.synchronize_state = kvm_cpu_synch
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +CpusAccel qtest_cpus = {
> +.create_vcpu_thread = qtest_start_vcpu_thread,
> +.get_virtual_clock = qtest_get_virtual_clock,
> +};
const.
Do you need to fill in the other methods, even if they do nothing but
g_assert_not_reached()?
> -
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +static int64_t tcg_get_virtual_clock(void)
> +{
> +if (icount_enabled()) {
> +return icount_get();
> +}
> +return cpu_get_clock();
> +}
> +
> +static int64_t tcg_get_elapsed_ticks(void)
> +{
> +if (icount_enabled()) {
> +
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> uint64_t cpu_get_tsc(CPUX86State *env)
> {
> -return cpu_get_ticks();
> +return cpus_get_elapsed_ticks();
What has this change got to do with creating the interface?
You said the interface wasn't used yet...
> diff --git a/stubs/cpu-synchro
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +/*
> + * Return the icount enablement state:
> + *
> + * 0 = Disabled - Do not count executed instructions.
> + * 1 = Enabled - Fixed conversion of insn to ns via "shift" option
> + * 2 = Enabled - Runtime adaptive algorithm to compute shift
> + */
> +
Can confirm this fixed the build in our configuration. Thank you.
Shu-Chun
On Thu, Aug 13, 2020 at 1:40 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> This has no functional change.
>
> The current function structure is:
>
> inline QEMU_ALWAYSINLINE
> store_memop() {
>
** Changed in: kunpeng920/ubuntu-18.04-hwe
Status: Triaged => Fix Committed
** Changed in: kunpeng920/ubuntu-18.04
Status: Triaged => Fix Committed
** Changed in: kunpeng920
Status: Triaged => Fix Committed
--
You received this bug notification because you are a member of q
On 8/11/20 9:49 AM, Andrew Jones wrote:
> Yes, except you need to drop the ARM_FEATURE_SPE define and use the ID
> register bit instead like "sve_supported" does.
On a related note, I think we have a latent bug, or at least a mis-feature:
sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION,
On 8/7/20 1:10 AM, Haibo Xu wrote:
> Signed-off-by: Haibo Xu
> ---
> target/arm/kvm.c | 5 +
> target/arm/kvm_arm.h | 13 +
> 2 files changed, 18 insertions(+)
Reviewed-by: Richard Henderson
r~
On 8/7/20 1:10 AM, Haibo Xu wrote:
> +static void arm_set_spe(Object *obj, bool value, Error **errp)
> +{
> +ARMCPU *cpu = ARM_CPU(obj);
> +
> +if (value) {
> +if (kvm_enabled() && !kvm_arm_spe_supported()) {
> +error_setg(errp, "'spe' feature not supported by KVM on thi
On 8/10/20 3:50 AM, Andrew Jones wrote:
>> @@ -1959,6 +1961,7 @@ enum arm_features {
>> ARM_FEATURE_VBAR, /* has cp15 VBAR */
>> ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
>> ARM_FEATURE_M_MAIN, /* M profile Main Extension */
>> +ARM_FEATURE_SPE, /* has SPE suppor
On 8/10/20 12:50 PM, Peter Maydell wrote:
> Some of our documentation is auto-generated from documentation
> comments in the JSON schema.
>
> For Sphinx, rather than creating a file to include, the most natural
> way to handle this is to have a small custom Sphinx extension which
> processes the J
On 8/10/20 12:50 PM, Peter Maydell wrote:
> In commit 26ec4e53f2 and similar commits we fixed the indentation
> for doc comments in our qapi json files to follow a new stricter
> standard for indentation, which permits only:
> @arg: description line 1
> description line 2
>
> or:
>
On 8/10/20 12:50 PM, Peter Maydell wrote:
> Commit eed8b6917832 added some new text to the nbd-server-start
> documentation in the wrong place. Since this is after the 'Returns:'
> line it's parsed as if it were part of the documentation of the
> "Returns:' information. Move it up to join the res
On 8/13/20 7:48 PM, Frank Chang wrote:
> esz is passed from e.g. GEN_VEXT_LD_STRIDE() macro:
>
>> #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \
>> void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
>> target_ulong stride, CPURISCVState *env, \
>>
v3 will come soon, don't look at this.
14.08.2020 16:03, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
Here is a filter, which does preallocation on write.
In Virtuozzo we have to deal with some custom distributed storage
solution, where allocation is relatively expensive operation. We have to
w
Patchew URL:
https://patchew.org/QEMU/1597423256-14847-1-git-send-email-bmeng...@gmail.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIP
14.08.2020 17:57, Alberto Garcia wrote:
Since commit c8bb23cbdbe32f5c326365e0a82e1b0e68cdcd8a when a write
request results in a new allocation QEMU first tries to see if the
rest of the cluster outside the written area contains only zeroes.
In that case, instead of doing a normal copy-on-write o
Hi!
14.08.2020 17:57, Alberto Garcia wrote:
Hi,
the patch is self-explanatory, but I'm using the cover letter to raise
a couple of related questions.
Since commit c8bb23cbdbe / QEMU 4.1.0 (and if the storage backend
allows it) writing to an image created with preallocation=metadata can
be slow
On 8/14/20 12:26 AM, Eduardo Habkost wrote:
> The existing type check macros all unconditionally drop const
> qualifiers from their arguments. Keep this behavior in the
> macros generated by DECLARE_*CHECKER* by now.
>
> In the future, we might use _Generic to preserve const-ness of
> the cast fu
On 8/14/20 12:26 AM, Eduardo Habkost wrote:
> Move typedef closer to the type check macros, to make it easier
> to convert the code to OBJECT_DEFINE_TYPE() in the future.
>
> Signed-off-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
> ---
> include/hw/timer/i8254.h | 2 ++
>
On 8/14/20 12:26 AM, Eduardo Habkost wrote:
> CanBusClass doesn't exist. This will break when we automatically
> convert the code to use OBJECT_DEFINE_TYPE(). Delete the macros
> that reference the non-existing typedef.
>
> Signed-off-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
>
On 8/14/20 12:26 AM, Eduardo Habkost wrote:
> The macro never worked because the NubusBridge typedef doesn't
> exist. Delete it.
>
> Signed-off-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
> ---
> include/hw/nubus/nubus.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/in
ping :)
10.06.2020 15:04, Vladimir Sementsov-Ogievskiy wrote:
v5: rebase on coroutine-wrappers series, 02 changed correspondingly
Based on series "[PATCH v7 0/7] coroutines: generate wrapper code", or
in other words:
Based-on: <20200610100336.23451-1-vsement...@virtuozzo.com>
Hi all!
These se
On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> Move typedef closer to the type check macros, to make it easier
> to convert the code to OBJECT_DEFINE_TYPE() in the future.
>
> Signed-off-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/net/tulip.h | 1 +
> hw/net/tulip.c | 4
On 8/14/20 12:26 AM, Eduardo Habkost wrote:
> Move typedef closer to the type check macros, to make it easier
> to convert the code to OBJECT_DEFINE_TYPE() in the future.
>
> Signed-off-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
> ---
> include/block/throttle-groups.h | 1 +
> bl
On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> Rename the DWC2_CLASS to DWC2_USB_CLASS and DWC2_GET_CLASS to
> DWC2_USB_GET_CLASS, for consistency with the DWC2_USB macro.
>
> Signed-off-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/usb/hcd-dwc2.h | 4 ++--
> hw/usb/hcd-dw
On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> Signed-off-by: Eduardo Habkost
> ---
> hw/pci-host/versatile.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c
> index 616882a80d..7e4aa467a2 100644
> --- a/hw/pci-host/versat
On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> Some of the enum constant names conflict with the QOM type check
> macros. This needs to be addressed to allow us to transform the
> QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
>
> Rename all the constants to IBEX_DEV_*,
+Niek as maintainer.
On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> Some of the enum constant names conflict with the QOM type check
> macros. This needs to be addressed to allow us to transform the
> QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
>
> Rename all the co
On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> The macro definition had an extra semicolon. This was never
> noticed because the macro was only being used where it didn't
> make a difference.
>
> Signed-off-by: Eduardo Habkost
> ---
> include/hw/timer/aspeed_timer.h | 2 +-
> 1 file changed, 1 i
On 8/14/20 12:25 AM, Eduardo Habkost wrote:
> The PL1110 enum value name will conflict with the PL1110 type
> cast checker, when we replace the existing macro with an inline
> function. Rename it to PL1110_STOCK.
typo s/PL1110/PL110/ in subject and description.
>
> Signed-off-by: Eduardo Habkos
On Fri, Aug 14, 2020 at 10:12 PM Bin Meng wrote:
>
> From: Bin Meng
>
> This adds support for Microchip PolarFire SoC Icicle Kit board.
> The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
> E51 plus four U54 cores and many on-chip peripherals and an FPGA.
Nice Work !!! This is v
On 8/14/20 9:39 AM, Philippe Mathieu-Daudé wrote:
> +static void avr_usart_update_baudrate(AVRUsartState *s)
> +{
> +unsigned baudrate = (clock_get_hz(s->clkin) / USART_CLOCK_DIVISOR)
> +/ (((s->brrh << 8) | s->brrl) + 1);
> +
> +trace_avr_usart_update_baudrate((s->b
On 8/14/20 6:14 AM, Yoshinori Sato wrote:
> RX's ELF machine not defined elf.h.
> Added it.
>
> Signed-off-by: Yoshinori Sato
> ---
> include/elf.h | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Richard Henderson
r~
On 8/14/20 5:55 AM, Philippe Mathieu-Daudé wrote:
> Allow the device to execute the DMA transfers in a different
> AddressSpace.
>
> We keep using the system_memory address space, but via the
> proper dma_memory_access() API.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/musicpal.c |
On 8/14/20 5:29 AM, Philippe Mathieu-Daudé wrote:
> Allow the device to execute the DMA transfers in a different
> AddressSpace.
>
> The H3 SoC keeps using the system_memory address space,
> but via the proper dma_memory_access() API.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Tested with
On 8/14/20 2:23 AM, Philippe Mathieu-Daudé wrote:
> Introduce sdbus_read_data() and sdbus_write_data() methods to
> access multiple bytes on the data line of a SD bus.
>
> I haven't named then sdbus_access_block() because I expect a
> block to be a power of 2, while there is no such restriction
>
On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Use self-explicit definitions instead of magic '512' value.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/scsi/scsi-disk.c | 44 +++-
> 1 file changed, 23 insertions(+), 21 deletions(-)
Reviewed-b
> I found out recently that XIVE support was
> merged into FreeBSD and with that it also came some good comments
> about xive...
cool ! Does it run in a QEMU PowerNV machine ?
C.
On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Use self-explicit definitions instead of magic '512' value.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/ide/pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Use self-explicit definitions instead of magic '512' value.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/ide/ahci.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Use self-explicit definitions instead of magic '512' value.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/ide/atapi.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
> diff --git a/hw/i
On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Use self-explicit definitions instead of magic '512' value.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/ide/core.c | 23 ---
> 1 file changed, 12 insertions(+), 11 deletions(-)
Reviewed-by: Richard Henderson
r~
On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/ide/core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote:
> As it is not obvious the default size for the null block driver
> is 1 GiB, replace the obfuscated '1 << 30' magic value by a
> definition using IEC binary prefixes.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> block/null.c | 4 +++-
> 1 f
From: Bin Meng
At present the CLINT timestamp is using a hard-coded timebase
frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
true for all boards.
Add a new 'timebase-freq' property to the CLINT device, and
update various functions to accept this as a parameter.
Signed-off-by: Bin
From: Bin Meng
Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
enough to create unimplemented devices to cover their register
spaces at this point.
With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
all the way to the Linux shell login prompt, with a modified HSS
(
From: Bin Meng
Microchip PolarFire SoC integrates a DMA engine that supports:
* Independent concurrent DMA transfers using 4 DMA channels
* Generation of interrupts on various conditions during execution
This creates a simple model to support polling mode which is
enough for firmware usage. Whil
From: Bin Meng
Microchip PolarFire SoC integrates 2 Candence GEMs to provide
IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.
On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
GEM1 connects to a PHY at address 9.
The 2nd stage bootloader (U-Boot) is using GEM1
From: Bin Meng
At present the function switch status data structure bit [399:376]
are wrongly pupulated. These 3 bytes encode function switch status
for the 6 function groups, with 4 bits per group, starting from
function group 6 at bit 399, then followed by function group 5 at
bit 395, and so on
From: Bin Meng
At present the PHY address of the PHY connected to GEM is hard-coded
to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
all boards. Add a new 'phy-addr' property so that board can specify
the PHY address for each GEM instance.
Signed-off-by: Bin Meng
---
hw/n
From: Bin Meng
Add some useful comments to document the software used for testing.
including how to patch HSS to bypass the DDR memory initialization,
HSS and Yocto BSP build instructions, etc.
To launch this machine for testing:
$ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
-bios p
From: Bin Meng
Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
wires 4 of them out. Let's connect all 5 MMUARTs.
Signed-off-by: Bin Meng
---
hw/riscv/Kconfig | 1 +
hw/riscv/microchip_pfsoc.c | 30 ++
include/hw/riscv/micr
From: Bin Meng
Connect a DMA controller to Microchip PolarFire SoC. Note interrupt
has not been connected due to missing information in the manual how
interrupts are routed to PLIC.
On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
controller to move the 2nd stage bootloader in
From: Bin Meng
sdhci_poweron_reset() might be needed for any SDHCI compatible
device that is built on top of the generic SDHCI device.
Signed-off-by: Bin Meng
---
hw/sd/sdhci-internal.h | 1 +
hw/sd/sdhci.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/sd/s
On 8/14/20 4:22 PM, no-re...@patchew.org wrote:
> Patchew URL: https://patchew.org/QEMU/20200814132118.12450-1-f4...@amsat.org/
> Hi,
>
> This series failed the docker-quick@centos7 build test. Please find the
> testing commands and
> their output below. If you have Docker installed, you can prob
From: Bin Meng
Microchip PolarFire SoC integrates one Cadence SDHCI controller.
On the Icicle Kit board, one eMMC chip and an external SD card
connect to this controller depending on different configuration.
As QEMU does not support eMMC yet, we just emulate the SD card
configuration. To test th
From: Bin Meng
Microchip PolarFire SoC MMUART is ns16550 compatible, with some
additional registers. Create a simple MMUART model built on top
of the existing ns16550 model.
Signed-off-by: Bin Meng
---
MAINTAINERS | 2 +
hw/char/Kconfig | 3 ++
hw
From: Bin Meng
Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.
Signed-off-by: Bin Men
From: Bin Meng
Per the SD spec, Standard Capacity SD Memory Card (SDSC) supports
capacity up to and including 2 GiB.
Signed-off-by: Bin Meng
---
hw/sd/sd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 51f5900..5e7fc3f 100644
--- a/hw/sd/sd.
From: Bin Meng
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.
This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model. C
From: Bin Meng
Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.
Normally reset vector address is a config
Expose the 'xck' clock source. Connect the MCU I/O clock to it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/char/avr_usart.h | 2 ++
hw/avr/atmega.c | 1 +
hw/char/avr_usart.c | 3 +++
3 files changed, 6 insertions(+)
diff --git a/include/hw/char/avr_usart.h b/inclu
From: Bin Meng
This is an initial support for Microchip PolarFire SoC Icicle Kit.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.
For more details about Microchip PolarFire Soc, please see:
https://www.microsemi
From: Bin Meng
RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.
Signed-off-by: Bin Meng
---
hw/riscv/riscv_hart.c | 3 ++
From: Bin Meng
This adds support for Microchip PolarFire SoC Icicle Kit board.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.
For more details about Microchip PolarFire Soc, please see:
https://www.microsemi.co
Nothing out of our model implementation is supposed to access its
registers. Keep the definitions local.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/char/avr_usart.h | 30 --
hw/char/avr_usart.c | 30 ++
2 files changed, 30
Expose the 'clkt' clock source. Connect the MCU I/O clock to it.
Drop the now unused 'cpu-frequency-hz' static property.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/timer/avr_timer16.h | 3 ++-
hw/avr/atmega.c| 3 +--
hw/timer/avr_timer16.c | 12
3
Use the Clock API to model the I/O clock. As we don't model
the Clock Control Unit, the XTAL is its unique clock source.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/avr/atmega.h | 2 ++
hw/avr/atmega.c | 4
2 files changed, 6 insertions(+)
diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
in
In this series we slowly start to use the recently added
Clock API in the AVR ATmega MCU.
As the Clock Control Unit is not yet modelled, we simply
connect the XTAL sink to the UART and Timer sources.
Philippe Mathieu-Daudé (5):
hw/avr/atmega: Introduce the I/O clock
hw/timer/avr_timer16: Use
Add a trace event to track baudrate changes.
Example when running the FreeRTOS acceptance test [1]:
$ qemu-system-avr -machine arduino-mega-2560-v3 -bios demo.elf -trace avr\*
2546@1597415281.399619:avr_usart_update_baudrate baudrate 0x0019 (38461 bauds)
2546@1597415281.400029:avr_usart_upd
Patchew URL:
https://patchew.org/QEMU/20200814130348.20625-1-vsement...@virtuozzo.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEG
Patchew URL:
https://patchew.org/QEMU/20200814130348.20625-1-vsement...@virtuozzo.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGI
On 8/14/20 1:59 AM, Chih-Min Chao wrote:
> By the way, the other patches have been queued in softfloat-next.
> Do I need to resend the other two patches in the next version or just this
> one ?
Just this one. Thanks.
r~
On 8/14/20 2:26 AM, Andrew Jones wrote:
>> +static uint64_t __attribute__((noinline))
>> +pauth_computepac_impdef(uint64_t data, uint64_t modifier, ARMPACKey key)
>
> Out of curiosity, why do we need to make these computepac functions
> noinline?
Oh, heh. Left over from profiling. Will remove.
Patchew URL:
https://patchew.org/QEMU/20200814043657.5815-1-rockcui...@zhaoxin.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN
On 10.08.2020 14:04, Vladimir Sementsov-Ogievskiy wrote:
10.08.2020 11:12, Max Reitz wrote:
On 07.08.20 12:29, Vladimir Sementsov-Ogievskiy wrote:
16.07.2020 17:59, Max Reitz wrote:
On 10.07.20 19:41, Andrey Shinkevich wrote:
On 10.07.2020 18:24, Max Reitz wrote:
On 09.07.20 16:52, Andrey Sh
On Thu, Aug 13, 2020 at 3:28 PM Eduardo Habkost wrote:
>
> Some of the enum constant names conflict with the QOM type check
> macros. This needs to be addressed to allow us to transform the
> QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
>
> Rename all the constants t
On Thu, Aug 13, 2020 at 3:37 PM Eduardo Habkost wrote:
>
> Some of the enum constant names conflict with the QOM type check
> macros. This needs to be addressed to allow us to transform the
> QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
>
> Rename all the constants t
On Wed, Aug 12, 2020 at 05:31:05PM -0700, Vikram Garhwal wrote:
> The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
> implementation. Bus connection and socketCAN connection for each CAN module
> can be set through command lines.
>
> Example for using single CAN:
>
From: Bin Meng
Upgrade OpenSBI from v0.7 to v0.8.
The v0.8 release includes the following commits:
1bb00ab lib: No need to provide default PMP region using platform callbacks
a9eac67 include: sbi_platform: Combine reboot and shutdown into one callback
6585fab lib: utils: Add SiFive test device
Once an interrupt has been claimed, but before it has been compelted we
shouldn't receive any more pending interrupts. This patche keeps track
of this to ensure that we don't see any more interrupts until it is
completed.
Signed-off-by: Alistair Francis
Message-Id:
<394c3f070615ff2b4fab61a1cf9cb
From: Bin Meng
Now we need to ship the OpenSBI fw_dynamic.elf image for the
RISC-V Spike machine, it requires us to create symbolic links
for pc-bios/*.elf files.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <1596439832-29238-2-git-send-email-bmeng...@gmail.com>
Signed-off
Patchew URL:
https://patchew.org/QEMU/20200814043657.5815-1-rockcui...@zhaoxin.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200814043657.5815-1-rockcui...@zhaoxin.com
Subject: [PATCH] ide:do nothing for identi
From: Bin Meng
The RISC-V generic platform is a flattened device tree (FDT) based
platform where all platform specific functionality is provided based
on FDT passed by previous booting stage. The support was added in
the upstream OpenSBI v0.8 release recently.
Update our Makefile to build the ge
After a claim or a priority change we need to update the pending
interrupts. This is based on the same patch for the SiFive PLIC:
55765822804f5a58594e "riscv: plic: Add a couple of mising
sifive_plic_update calls"
Signed-off-by: Alistair Francis
Cc: Jessica Clarke
Reviewed-by: Philippe Mathieu-D
On Thu, Aug 13, 2020 at 3:29 PM Eduardo Habkost wrote:
>
> Some of the enum constant names conflict with the QOM type check
> macros. This needs to be addressed to allow us to transform the
> QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
>
> Rename all the constants t
From: Hou Weiying
First, sizeof(target_ulong) equals to 4 on riscv32, so this change
does not change the function on riscv32. Second, sizeof(target_ulong)
equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal
pmp_index (we will explain later), which should be 'reg_index * 4 + i'.
If the
From: Bin Meng
It is enough to simply map the SiFive FU540 L2 cache controller
into the MMIO space using create_unimplemented_device(), with an
FDT fragment generated, to make the latest upstream U-Boot happy.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <1595227748-24720-
From: LIU Zhiwei
Use tcg_gen_extu_tl_i64 to avoid the ifdef.
Signed-off-by: LIU Zhiwei
Signed-off-by: Richard Henderson
Message-Id: <20200626205917.4545-7-zhiwei_...@c-sky.com>
Signed-off-by: Richard Henderson
Message-Id: <20200724002807.441147-7-richard.hender...@linaro.org>
Signed-off-by: A
On Fri, Aug 14, 2020 at 6:30 AM Philippe Mathieu-Daudé wrote:
>
> Most of the MDIOBus fields are unused. The ADVERTISE_10HALF
> definition is unused. Remove unused code.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/net/xilinx_axienet.c | 23 --
This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source
priorities" does and ensures that the highest priority interrupt will be
serviced first.
Signed-off-by: Alistair Francis
Cc: Jessica Clarke
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
---
hw/intc/ibex_plic.c | 15 ++
From: Richard Henderson
If a 32-bit input is not properly nanboxed, then the input is replaced
with the default qnan. The only inline expansion is for the sign-changing
set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Message-Id: <2020
From: Zong Li
The minimum granularity of PMP is 4 bytes, it is small than 4KB page
size, therefore, the pmp checking would be ignored if its range doesn't
start from the alignment of one page. This patch detects the pmp entries
and sets the small page size to TLB if there is a PMP entry which cov
From: Richard Henderson
Make sure that all results from single-precision scalar helpers
are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Message-Id: <20200724002807.441147-2-richard.hender...@linaro.org>
Signed-off-by: Alistair Francis
---
target/ri
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