Memory leak in spapr_machine_init()?

Either I'm confused (quite possible), or kvmppc_check_papr_resize_hpt() can leak an Error object on failure. Please walk through the code with me: kvmppc_check_papr_resize_hpt(&resize_hpt_err); This sets @resize_hpt_err on failure. if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAU

RE: Memory leak in transfer_memory_block()?

> -Original Message- > From: Markus Armbruster [mailto:arm...@redhat.com] > Sent: Thursday, June 18, 2020 1:36 PM > To: Zhanghailiang > Cc: qemu-devel@nongnu.org; Michael Roth > Subject: Memory leak in transfer_memory_block()? > > We appear to leak an Error object when ga_read_sysfs_file

Re: [PATCH] softmmu/vl: Do not recommend to use -M accel=... anymore

Patchew URL: https://patchew.org/QEMU/20200618055754.12154-1-th...@redhat.com/ Hi, This series failed the asan build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/bin/bash export

Re: [PATCH] tests: fix a memory in test_socket_unix_abstract_good

Ping.. Anyone queued this? Thanks, Li Qiang Li Qiang 于2020年6月4日周四 上午12:31写道： > After build qemu with '-fsanitize=address' extra-cflags, > 'make check' show following leak: > > = > ==44580==ERROR: LeakSanitizer: detected memory leak

[PATCH] softmmu/vl: Do not recommend to use -M accel=... anymore

The new -accel parameter can be used multiple times now, so we should recommend this new way instead. Signed-off-by: Thomas Huth --- softmmu/vl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/softmmu/vl.c b/softmmu/vl.c index f669c06ede..e2b2991a5f 100644 --- a/softmmu/vl.c

Re: [PATCH v2 000/100] target/arm: Implement SVE2

Patchew URL: https://patchew.org/QEMU/20200618042644.1685561-1-richard.hender...@linaro.org/ Hi, This series failed the asan build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/b

Re: [PATCH 1/7] qemu-common: Briefly document qemu_timedate_diff() unit

Philippe Mathieu-Daudé writes: > It is not obvious that the qemu_timedate_diff() and > qemu_ref_timedate() functions return seconds. Briefly > document it. > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/qemu-common.h | 1 + > softmmu/vl.c | 2 +- > 2 files changed, 2 inserti

Memory leak in transfer_memory_block()?

We appear to leak an Error object when ga_read_sysfs_file() fails with errno != ENOENT unless caller passes true @sys2memblk: static void transfer_memory_block(GuestMemoryBlock *mem_blk, bool sys2memblk, GuestMemoryBlockResponse *result,

qemu-pr-helper -v suppresses errors, isn't that weird?

prh_co_entry() reports reports errors reading requests / writing responses only when @verbose (command line -v); relevant code appended for you convenience. Sure these are *errors*? The program recovers and continues, and this is deemed normal enough to inform the user only when he specifically a

Re: [PATCH v2 000/100] target/arm: Implement SVE2

Patchew URL: https://patchew.org/QEMU/20200618042644.1685561-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v2 000/100] target/arm: Implement SVE2 Type: series Message-id: 20200618042644.1685561-

[Bug 1884017] Re: Intermittently erratic mouse under Windows 95

Weirdly, this problem doesn't occur when running qemu on macOS (10.15.5). It only happens on my PC running openSUSE Tumbleweed. However, even on that PC, it only affects Windows 95, and not Windows 98, or other operating systems. -- You received this bug notification because you are a member of

Re: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004

Hi Alistair, On Thu, Jun 18, 2020 at 8:41 AM Bin Meng wrote: > > Hi Alistair, > > On Thu, Jun 18, 2020 at 12:40 AM Alistair Francis > wrote: > > > > On Mon, Jun 15, 2020 at 5:51 PM Bin Meng wrote: > > > > > > From: Bin Meng > > > > > > Per the SiFive manual, all E/U series CPU cores' reset ve

[PATCH v2 096/100] target/arm: Share table of sve load functions

The table used by do_ldrq is a subset of the table used by do_ld_zpa; we can share them by passing dtype instead of msz to do_ldrq. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 120 ++--- 1 file changed, 58 insertions(+), 62 deletions(-) diff

[PATCH v2 095/100] tcg: Implement 256-bit dup for tcg_gen_gvec_dup_mem

We already support duplication of 128-bit blocks. This extends that support to 256-bit blocks. This will be needed by SVE2. Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 52 --- 1 file changed, 49 insertions(+), 3 deletions(-) diff --git

[PATCH v2 092/100] target/arm: Implement SVE2 FCVTXNT, FCVTX

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-4-stepl...@quicinc.com> [rth: Use do_frint_mode, which avoids a specific runtime helper.] Signed-off-by: Richard Henderson --- target/arm/sve.decode | 2 ++ target/arm/translate-sve.c | 49 ++

Re: Query Regarding Contribution

On 17/06/2020 20.25, khyati agarwal wrote: > Respected , > I am Khyati Agarwal, second-year undergraduate in CSE, IIT, Mandi, > India. I have good knowledge of git, Python, C/C++, php, machine > learning and databases like mongodb, mysql. I'm interested in > contributing to QEMU. I have worked with

[PATCH v2 089/100] target/arm: Implement SVE2 TBL, TBX

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428144352.9275-1-stepl...@quicinc.com> [rth: rearrange the macros a little and rebase] Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 10 + target/arm/sve.decode | 5 +++ target/arm/sve_helper.c|

Re: [PATCH v2 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines

On Wed, Jun 17, 2020 at 8:54 AM Cédric Le Goater wrote: > Hello, > > On 6/12/20 12:30 AM, Havard Skinnemoen wrote: > > This patch series models enough of the Nuvoton NPCM730 and NPCM750 SoCs > to boot > > an OpenBMC image built for quanta-gsj. This includes device models for: > > > > - Global C

[PATCH v2 086/100] target/arm: Implement SVE2 crypto unary operations

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 6 ++ target/arm/translate-sve.c | 11 +++ 2 files changed, 17 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 0be8a020f6..9b0d0f3a5d 100644 --- a/target/arm/sve.decode +++ b/target/arm/

[Bug 1884017] [NEW] Intermittently erratic mouse under Windows 95

Public bug reported: The mouse works fine maybe 75-80% of the time, but intermittently (every 20-30 seconds or so), moving the mouse will cause the pointer to fly around the screen at high speed, usually colliding with the edges, and much more problematically, click all the mouse buttons at random

[PATCH v2 084/100] target/arm: Implement SVE mixed sign dot product (indexed)

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++ target/arm/helper.h| 4 +++ target/arm/sve.decode | 4 +++ target/arm/translate-sve.c | 18 +++ target/arm/vec_helper.c| 66 ++ 5 files changed, 97 insertions(+

Re: [PATCH] hw/audio/gus: Fix registers 32-bit access

On 18/06/2020 00.25, Allan Peramaki wrote: > On 17/06/2020 23:23, Peter Maydell wrote: >> >> This patch is quite difficult to read because it mixes some >> whitespace only changes with some actual changes of >> behaviour. > > Sorry about that. I had to put some whitespace in the two lines I > modi

[PATCH v2 099/100] target/arm: Implement SVE2 bitwise shift immediate

From: Stephen Long Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU Signed-off-by: Stephen Long Message-Id: <20200430194159.24064-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 33 + target/arm/sve.decode | 5 target/arm

[PATCH v2 091/100] target/arm: Implement SVE2 FCVTLT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-3-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 23 +++ target/arm/translate

[PATCH v2 082/100] target/arm: Implement SVE2 multiply-add long (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 17 + target/arm/sve.decode | 18 ++ target/arm/sve_helper.c| 16 target/arm/translate-sve.c | 20 4 files changed, 71 insertions(+) diff --git a/targe

Re: [PATCH] hw/audio/gus: Fix registers 32-bit access

On 15/06/2020 22.17, Allan Peramaki wrote: > Fix audio on software that accesses DRAM above 64k via register peek/poke > and some cases when more than 16 voices are used. > > Fixes: 135f5ae1974c ("audio: GUSsample is int16_t") > Signed-off-by: Allan Peramaki > --- > hw/audio/gusemu_hal.c | 6 +

[PATCH v2 098/100] target/arm: Implement 128-bit ZIP, UZP, TRN

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 3 ++ target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 29 +-- target/arm/translate-sve.c | 58 ++ 4 files changed, 90 insertions(+), 8 deletions(-) diff --g

[PATCH v2 097/100] target/arm: Implement SVE2 LD1RO

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 4 ++ target/arm/translate-sve.c | 95 ++ 2 files changed, 99 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 6808ff4194..e0d093c5d7 100644 --- a/target/arm/sve.d

[PATCH v2 100/100] target/arm: Implement SVE2 fp multiply-add long

From: Stephen Long Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT Signed-off-by: Stephen Long Message-Id: <20200504171240.11220-1-stepl...@quicinc.com> [rth: Rearrange to use float16_to_float32_by_bits.] Signed-off-by: Richard Henderson --- target/arm/helper.h| 5

[PATCH v2 080/100] target/arm: Use helper_neon_sq{, r}dmul_* for aa64 advsimd

Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 target/arm/translate-a64.c | 33 + target/arm/vec_helper.c| 49 ++ 3 files changed, 82 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.h b/

[PATCH v2 090/100] target/arm: Implement SVE2 FCVTNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-2-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 4 target/arm/sve_helper.c| 20 target/arm/translate-

[PATCH v2 087/100] target/arm: Implement SVE2 crypto destructive binary operations

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/sve.decode | 7 +++ target/arm/translate-sve.c | 38 ++ 3 files changed, 50 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df0a3e201b..37fc86

[PATCH v2 094/100] target/arm: Implement SVE2 FLOGB

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200430191405.21641-1-stepl...@quicinc.com> [rth: Fixed esz index and c++ comments] Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 4 target/arm/sve.decode | 3 +++ target/arm/sve_helper.c| 49 +

[PATCH v2 081/100] target/arm: Implement SVE2 saturating multiply high (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper.h| 14 ++ target/arm/sve.decode | 8 target/arm/translate-sve.c | 8 target/arm/vec_helper.c| 88 ++ 4 files changed, 118 insertions(+) diff --git a/target/arm/helper.h b/t

[PATCH v2 079/100] target/arm: Implement SVE2 signed saturating doubling multiply high

Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 + target/arm/sve.decode | 4 ++ target/arm/translate-sve.c | 18 target/arm/vec_helper.c| 84 ++ 4 files changed, 116 insertions(+) diff --git a/target/arm/helper.h b/

[PATCH v2 093/100] softfloat: Add float16_is_normal

From: Stephen Long This float16 predicate was missing from the normal set. Signed-off-by: Stephen Long Signed-off-by: Richard Henderson --- include/fpu/softfloat.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 16ca697a73..cd1f

[PATCH v2 085/100] target/arm: Implement SVE mixed sign dot product

Signed-off-by: Richard Henderson --- target/arm/helper.h| 2 ++ target/arm/sve.decode | 4 target/arm/translate-sve.c | 16 target/arm/vec_helper.c| 18 ++ 4 files changed, 40 insertions(+) diff --git a/target/arm/helper.h b/target/arm/hel

[PATCH v2 077/100] target/arm: Implement SVE2 integer multiply long (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 16 target/arm/sve_helper.c| 23 +++ target/arm/translate-sve.c | 24 4 files changed, 64 insertions(+), 4 deletions(-) diff

[PATCH v2 076/100] target/arm: Implement SVE2 saturating multiply-add (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 9 + target/arm/sve.decode | 18 ++ target/arm/sve_helper.c| 30 ++ target/arm/translate-sve.c | 32 4 files changed, 81 insertions(+),

[PATCH v2 088/100] target/arm: Implement SVE2 crypto constructive binary operations

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/sve.decode | 4 target/arm/translate-sve.c | 16 3 files changed, 25 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 37fc866cf8..1be8f51162 100644 --- a/target/

[PATCH v2 078/100] target/arm: Implement SVE2 saturating multiply (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 6 ++ target/arm/sve_helper.c| 3 +++ target/arm/translate-sve.c | 5 + 4 files changed, 19 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 91cce

[PATCH v2 074/100] target/arm: Use helper_gvec_ml{a, s}_idx_* for aa64 advsimd

Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 34 ++ 1 file changed, 34 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a3135754ce..5ef6ecfbf1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/tra

[PATCH v2 071/100] target/arm: Implement SVE2 integer multiply (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper.h| 4 target/arm/sve.decode | 7 +++ target/arm/translate-sve.c | 30 ++ target/arm/vec_helper.c| 29 + 4 files changed, 66 insertions(+), 4 deletions(-) dif

[PATCH v2 067/100] target/arm: Pass separate addend to {U, S}DOT helpers

For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Signed-off-by: Richard Henderson --- target/arm/helper.h | 20 +++--- target/arm/sve.decode | 7 +- target/arm/translate

[PATCH v2 083/100] target/arm: Implement SVE2 complex integer multiply-add (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 9 +++ target/arm/sve.decode | 12 target/arm/sve_helper.c| 142 +++-- target/arm/translate-sve.c | 38 +++--- 4 files changed, 169 insertions(+), 32 deletions(-) diff --git a/

[PATCH v2 069/100] target/arm: Split out formats for 2 vectors + 1 index

Currently only used by FMUL, but will shortly be used more. Signed-off-by: Richard Henderson --- target/arm/sve.decode | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 5815ba9b1c..a121e55f07 100644 --- a/tar

[PATCH v2 070/100] target/arm: Split out formats for 3 vectors + 1 index

Used by FMLA and DOT, but will shortly be used more. Split FMLA from FMLS to avoid an extra sub field; similarly for SDOT from UDOT. Signed-off-by: Richard Henderson --- target/arm/sve.decode | 29 +++-- target/arm/translate-sve.c | 38 ---

[PATCH v2 075/100] target/arm: Implement SVE2 saturating multiply-add high (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 + target/arm/sve.decode | 8 target/arm/sve_helper.c| 40 ++ target/arm/translate-sve.c | 8 4 files changed, 70 insertions(+) diff --git a/target/ar

[PATCH v2 066/100] target/arm: Fix sve_punpk_p vs odd vector lengths

Wrote too much with punpk1 with vl % 512 != 0. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index dc23a9b3e0..24c733fea1 10064

[PATCH v2 064/100] target/arm: Fix sve_uzp_p vs odd vector lengths

Missed out on compressing the second half of a predicate with length vl % 512 > 256. Adjust all of the x + (y << s) to x | (y << s) as a general style fix. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 30 +- 1 file ch

[PATCH v2 063/100] target/arm: Implement SVE2 SPLICE, EXT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200423180347.9403-1-stepl...@quicinc.com> [rth: Rename the trans_* functions to *_sve2.] Signed-off-by: Richard Henderson --- target/arm/sve.decode | 11 +-- target/arm/translate-sve.c | 35 +

[PATCH v2 065/100] target/arm: Fix sve_zip_p vs odd vector lengths

Wrote too much with low-half zip (zip1) with vl % 512 != 0. Adjust all of the x + (y << s) to x | (y << s) as a style fix. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 25 ++--- 1 file changed, 14 insertions(+), 11 deletions(

[PATCH v2 073/100] target/arm: Implement SVE2 integer multiply-add (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper.h| 14 ++ target/arm/sve.decode | 8 target/arm/translate-sve.c | 23 +++ target/arm/vec_helper.c| 25 + 4 files changed, 70 insertions(+) diff --git a/target

[PATCH v2 061/100] target/arm: Implement SVE2 gather load insns

From: Stephen Long Add decoding logic for SVE2 64-bit/32-bit gather non-temporal load insns. 64-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1SW * LDNT1W (vector plus scalar) * LDNT1D (vector plus scalar) 32-bit * LDNT1SB * LDNT1B (vector plus scalar

[PATCH v2 060/100] target/arm: Implement SVE2 scatter store insns

From: Stephen Long Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal store insns. 64-bit * STNT1B (vector plus scalar) * STNT1H (vector plus scalar) * STNT1W (vector plus scalar) * STNT1D (vector plus scalar) 32-bit * STNT1B (vector plus scalar) * STNT1H (vector plus scalar) * STNT

[PATCH v2 072/100] target/arm: Use helper_gvec_mul_idx_* for aa64 advsimd

Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 16 1 file changed, 16 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 341b11f98d..a3135754ce 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1

[PATCH v2 058/100] target/arm: Implement SVE2 HISTCNT, HISTSEG

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200416173109.8856-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix overlap between output and input vectors. --- target/arm/helper-sve.h| 7 +++ target/arm/sve.decode | 6 ++ target/arm/sve_helper.c

[PATCH v2 055/100] target/arm: Implement SVE2 RADDHNB, RADDHNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-3-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix round bit type (laurent desnogues) --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c

[PATCH v2 057/100] target/arm: Implement SVE2 RSUBHNB, RSUBHNT

From: Stephen Long This completes the section 'SVE2 integer add/subtract narrow high part' Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-5-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix round bit type (laurent desnogues) --- target/arm/helper-sve.h| 8

[PATCH v2 068/100] target/arm: Pass separate addend to FCMLA helpers

For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Signed-off-by: Richard Henderson --- target/arm/helper.h | 20 ++--- target/arm/translate-a64.c | 27 ++

[PATCH v2 056/100] target/arm: Implement SVE2 SUBHNB, SUBHNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-4-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 10 ++ target/arm/translate-sve.c |

[PATCH v2 054/100] target/arm: Implement SVE2 ADDHNB, ADDHNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-2-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 5 + target/arm/sve_helper.c| 36 t

[PATCH v2 062/100] target/arm: Implement SVE2 FMMLA

From: Stephen Long Signed-off-by: Stephen Long Fixed the errors Richard pointed out. Message-Id: <20200422165503.13511-1-stepl...@quicinc.com> [rth: Fix indexing in helpers, expand macro to straight functions.] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++ targe

[PATCH v2 053/100] target/arm: Implement SVE2 complex integer multiply-add

Signed-off-by: Richard Henderson --- v2: Fix do_sqrdmlah_d (laurent desnogues) --- target/arm/helper-sve.h| 18 target/arm/vec_internal.h | 5 + target/arm/sve.decode | 5 + target/arm/sve_helper.c| 42 ++ target/arm/tra

[PATCH v2 052/100] target/arm: Implement SVE2 integer multiply-add long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 28 ++ target/arm/sve.decode | 11 ++ target/arm/sve_helper.c| 18 + target/arm/translate-sve.c | 76 ++ 4 files changed, 133 insertions(+) diff --git a/target/a

[PATCH v2 047/100] target/arm: Implement SVE2 bitwise ternary operations

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 6 ++ target/arm/sve.decode | 12 +++ target/arm/sve_helper.c| 50 + target/arm/translate-sve.c | 213 + 4 files changed, 281 insertions(+) diff --git a/target/arm/helper-sv

[PATCH v2 059/100] target/arm: Implement SVE2 XAR

In addition, use the same vector generator interface for AdvSIMD. This fixes a bug in which the AdvSIMD insn failed to clear the high bits of the SVE register. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 4 ++ target/arm/helper.h| 2 + target/arm/translate-a64.h

[PATCH v2 051/100] target/arm: Implement SVE2 saturating multiply-add high

SVE2 has two additional sizes of the operation and unlike NEON, there is no saturation flag. Create new entry points for SVE2 that do not set QC. Signed-off-by: Richard Henderson --- target/arm/helper.h| 17 target/arm/sve.decode | 5 ++ target/arm/translate-sve.c | 18 +++

[PATCH v2 049/100] target/arm: Implement SVE2 saturating multiply-add long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 ++ target/arm/sve.decode | 14 ++ target/arm/sve_helper.c| 30 + target/arm/translate-sve.c | 54 ++ 4 files changed, 112 insertions(+) diff --gi

[PATCH v2 041/100] target/arm: Implement SVE2 SHRN, RSHRN

Signed-off-by: Richard Henderson --- v2: Fix typo in gen_shrnb_vec (laurent desnogues) --- target/arm/helper-sve.h| 16 target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 45 ++- target/arm/translate-sve.c | 160 + 4 files chan

[PATCH v2 050/100] target/arm: Generalize inl_qrdmlah_* helper functions

Unify add/sub helpers and add a parameter for rounding. This will allow saturating non-rounding to reuse this code. Signed-off-by: Richard Henderson --- target/arm/vec_helper.c | 80 +++-- 1 file changed, 29 insertions(+), 51 deletions(-) diff --git a/target/

[PATCH v2 046/100] target/arm: Implement SVE2 WHILERW, WHILEWR

Signed-off-by: Richard Henderson --- v2: Fix decodetree typo --- target/arm/sve.decode | 3 ++ target/arm/translate-sve.c | 62 ++ 2 files changed, 65 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index b7038f9f57..19d503e2f4 1

[PATCH v2 048/100] target/arm: Implement SVE2 MATCH, NMATCH

From: Stephen Long Reviewed-by: Richard Henderson Signed-off-by: Stephen Long Message-Id: <20200415145915.2859-1-stepl...@quicinc.com> [rth: Expanded comment for do_match2] Signed-off-by: Richard Henderson --- v2: Apply esz_mask to input pg to fix output flags. --- target/arm/helper-sve.h

[PATCH v2 045/100] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS

Rename the existing sve_while (less-than) helper to sve_whilel to make room for a new sve_whileg helper for greater-than. Signed-off-by: Richard Henderson --- v2: Use a new helper function to implement this. --- target/arm/helper-sve.h| 3 +- target/arm/sve.decode | 2 +- target/arm/s

[PATCH v2 035/100] target/arm: Implement SVE2 integer add/subtract long with carry

Signed-off-by: Richard Henderson --- v2: Fix sel indexing and argument order (laurent desnogues). --- target/arm/helper-sve.h| 3 +++ target/arm/sve.decode | 6 ++ target/arm/sve_helper.c| 34 ++ target/arm/translate-sve.c | 23 ++

[PATCH v2 043/100] target/arm: Implement SVE2 UQSHRN, UQRSHRN

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 +++ target/arm/sve.decode | 4 ++ target/arm/sve_helper.c| 24 ++ target/arm/translate-sve.c | 93 ++ 4 files changed, 137 insertions(+) diff --git a/target/arm/helper-

[PATCH v2 038/100] target/arm: Implement SVE2 integer absolute difference and accumulate

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 6 ++ target/arm/translate-sve.c | 21 + 2 files changed, 27 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 90a9d6552a..b5450b1d4d 100644 --- a/target/arm/sve.decode +++ b/t

[PATCH v2 042/100] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 +++ target/arm/sve.decode | 4 ++ target/arm/sve_helper.c| 24 ++ target/arm/translate-sve.c | 98 ++ 4 files changed, 142 insertions(+) diff --git a/target/arm/helper-

[PATCH v2 034/100] target/arm: Implement SVE2 integer absolute difference and accumulate long

Signed-off-by: Richard Henderson --- v2: Fix select offsetting and argument order (laurent desnogues). --- target/arm/helper-sve.h| 14 ++ target/arm/sve.decode | 12 + target/arm/sve_helper.c| 23 target/arm/translate-sve.c | 55 +

[PATCH v2 037/100] target/arm: Implement SVE2 bitwise shift and insert

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 5 + target/arm/translate-sve.c | 10 ++ 2 files changed, 15 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 7783e9f0d3..90a9d6552a 100644 --- a/target/arm/sve.decode +++ b/target/arm/sv

[PATCH v2 033/100] target/arm: Implement SVE2 complex integer add

Signed-off-by: Richard Henderson --- v2: Fix subtraction ordering (laurent desnogues). --- target/arm/helper-sve.h| 10 + target/arm/sve.decode | 9 target/arm/sve_helper.c| 42 ++ target/arm/translate-sve.c | 31 +

[PATCH v2 044/100] target/arm: Implement SVE2 SQSHRN, SQRSHRN

This completes the section "SVE2 bitwise shift right narrow". Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 ++ target/arm/sve.decode | 4 ++ target/arm/sve_helper.c| 24 + target/arm/translate-sve.c | 105 + 4 f

[PATCH v2 040/100] target/arm: Implement SVE2 floating-point pairwise

From: Stephen Long Signed-off-by: Stephen Long Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- v2: Load all inputs before writing any output (laurent desnogues) --- target/arm/helper-sve.h| 35 + target/arm/sve.decode | 8 +++ targ

Re: [PATCH 0/2] use helper when using abstract QOM parent functions

Hi, On 10/14/19 5:12 PM, Auger Eric wrote: Hi, On 10/12/19 11:43 AM, Mao Zhongyi wrote: Philippe introduced a series of helpers to make the device class_init() easier to understand when a device class change the parent hooks, some devices in the source tree missed helper, so convert it. Cc: e

[PATCH v2 026/100] target/arm: Implement SVE2 integer add/subtract wide

Signed-off-by: Richard Henderson --- v2: Fix select offsets (laurent desnogues). --- target/arm/helper-sve.h| 16 target/arm/sve.decode | 12 target/arm/sve_helper.c| 30 ++ target/arm/translate-sve.c | 20

[PATCH v2 039/100] target/arm: Implement SVE2 saturating extract narrow

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 24 target/arm/sve.decode | 12 ++ target/arm/sve_helper.c| 56 + target/arm/translate-sve.c | 248 - 4 files changed, 335 insertions(+), 5 deletions(-) diff --git a/tar

[PATCH v2 032/100] target/arm: Implement SVE2 bitwise permute

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++ target/arm/helper-sve.h| 15 target/arm/sve.decode | 6 target/arm/sve_helper.c| 73 ++ target/arm/translate-sve.c | 36 +++ 5 files changed, 1

[PATCH v2 025/100] target/arm: Implement SVE2 integer add/subtract interleaved long

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 6 ++ target/arm/translate-sve.c | 4 2 files changed, 10 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 84fc0ade2c..91e45f2d32 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decod

[PATCH v2 029/100] target/arm: Tidy SVE tszimm shift formats

Rather than require the user to fill in the immediate (shl or shr), create full formats that include the immediate. Signed-off-by: Richard Henderson --- target/arm/sve.decode | 35 --- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/target/arm/sve.

[PATCH v2 030/100] target/arm: Implement SVE2 bitwise shift left long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 8 ++ target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 26 ++ target/arm/translate-sve.c | 159 + 4 files changed, 201 insertions(+) diff --git a/target/arm/helper-sve.h

[PATCH v2 036/100] target/arm: Implement SVE2 bitwise shift right and accumulate

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 8 target/arm/translate-sve.c | 34 ++ 2 files changed, 42 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index f4f0c2ade6..7783e9f0d3 100644 --- a/target/arm/sve

[PATCH v2 018/100] target/arm: Implement SVE2 integer unary operations (predicated)

Signed-off-by: Richard Henderson --- v2: Fix sqabs, sqneg (laurent desnogues) --- target/arm/helper-sve.h| 13 +++ target/arm/sve.decode | 7 ++ target/arm/sve_helper.c| 29 +++ target/arm/translate-sve.c | 47 ++ 4

[PATCH v2 024/100] target/arm: Implement SVE2 integer add/subtract long

Signed-off-by: Richard Henderson --- v2: Fix select offsets (laurent desnogues). --- target/arm/helper-sve.h| 24 target/arm/sve.decode | 19 target/arm/sve_helper.c| 43 +++ target/arm/translate-sve.c | 46 +++

[PATCH v2 027/100] target/arm: Implement SVE2 integer multiply long

Exclude PMULL from this category for the moment. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 15 +++ target/arm/sve.decode | 9 + target/arm/sve_helper.c| 31 +++ target/arm/translate-sve.c | 9 + 4 files ch

[PATCH v2 031/100] target/arm: Implement SVE2 bitwise exclusive-or interleaved

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 5 + target/arm/sve_helper.c| 20 target/arm/translate-sve.c | 19 +++ 4 files changed, 49 insertions(+) diff --git a/target/arm/helper-sve.h b/t

[PATCH v2 016/100] target/arm: Implement SVE2 Integer Multiply - Unpredicated

For MUL, we can rely on generic support. For SMULH and UMULH, create some trivial helpers. For PMUL, back in a21bb78e5817, we organized helper_gvec_pmul_b in preparation for this use. Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 target/arm/sve.decode | 10 +++

[PATCH v2 021/100] target/arm: Implement SVE2 integer halving add/subtract (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 54 ++ target/arm/sve.decode | 11 target/arm/sve_helper.c| 39 +++ target/arm/translate-sve.c | 8 ++ 4 files changed, 112 insertions(+) diff --gi

[PATCH v2 028/100] target/arm: Implement PMULLB and PMULLT

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++ target/arm/helper-sve.h| 1 + target/arm/sve.decode | 2 ++ target/arm/translate-sve.c | 22 ++ target/arm/vec_helper.c| 24 5 files changed, 59 insertions(

[PATCH v2 023/100] target/arm: Implement SVE2 saturating add/subtract (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 54 +++ target/arm/sve.decode | 11 +++ target/arm/sve_helper.c| 194 ++--- target/arm/translate-sve.c | 7 ++ 4 files changed, 210 insertions(+), 56 deletions(-) diff --git a/t

[PATCH v2 015/100] target/arm: Enable SVE2 and some extensions

Sort to the end of the patch series for final commit. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 778cecc2e6..7389b6e5ab 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu

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