On Fri, May 29, 2020 at 4:48 AM Anup Patel wrote:
>
> We extend RISC-V spike machine to allow creating a multi-socket
> machine. Each RISC-V spike machine socket is a NUMA node having
> a set of HARTs, a memory instance, and a CLINT instance. Other
> devices are shared between all sockets. We also
On Fri, May 29, 2020 at 4:50 AM Anup Patel wrote:
>
> We extend RISC-V virt machine to allow creating a multi-socket
> machine. Each RISC-V virt machine socket is a NUMA node having
> a set of HARTs, a memory instance, a CLINT instance, and a PLIC
> instance. Other devices are shared between all s
On Fri, May 29, 2020 at 4:48 AM Anup Patel wrote:
>
> We add common helper routines which can be shared by RISC-V
> multi-socket NUMA machines.
>
> We have two types of helpers:
> 1. riscv_socket_xyz() - These helper assist managing multiple
>sockets irrespective whether QEMU NUMA is enabled/d
Patchew URL: https://patchew.org/QEMU/20200613042029.22321-1-...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20200613042029.22321-1-...@linux.ibm.com
Subject: [PATCH 0/6] Add several Power ISA 3.1 32/64-bit vector
vmulhsd: Vector Multiply High Signed Doubleword
vmulhud: Vector Multiply High Unsigned Doubleword
Signed-off-by: Lijun Pan
---
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 24
target/ppc/translate/vmx-impl.inc.c | 2 ++
target/ppc/t
This patch series add several newly introduced 32/64-bit vector
instructions in Power ISA 3.1. The newly added instructions are
flagged as ISA300 temporarily in vmx-ops.inc.c and vmx-impl.inc.c
to make them compile and function since Power ISA 3.1, together
with next generation processor, has not b
vmulhsw: Vector Multiply High Signed Word
vmulhuw: Vector Multiply High Unsigned Word
Signed-off-by: Lijun Pan
---
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 14 ++
target/ppc/translate/vmx-impl.inc.c | 6 ++
target/ppc/translate/vmx-ops.i
vdivsw: Vector Divide Signed Word
vdivuw: Vector Divide Unsigned Word
vdivsd: Vector Divide Signed Doubleword
vdivud: Vector Divide Unsigned Doubleword
vmodsw: Vector Modulo Signed Word
vmoduw: Vector Modulo Unsigned Word
vmodsd: Vector Modulo Signed Doubleword
vmodud: Vector Modulo Unsigned Double
The prototypes of muls64/mulu64 in host-utils.h should match the
definitions in host-utils.c
Signed-off-by: Lijun Pan
---
include/qemu/host-utils.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index 4cd170e6cd..cdca
vmulld: Vector Multiply Low Doubleword.
Signed-off-by: Lijun Pan
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 1 +
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 1 +
4 files changed, 4 insertions(+)
diff --git a/target/p
POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form
Signed-off-by: Lijun Pan
---
target/ppc/translate.c | 62 ++
1 file changed, 62 insertions(+)
vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
VA-form.
vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned
Doubleword VA-form.
Signed-off-by: Lijun Pan
---
v2: move vmsumcudm() to qemu/int128.h as Richard Henderson suggested,
also rename addu1
On Fri, 2020-06-12 at 17:52 -0700, Alistair Francis wrote:
> On Thu, Jun 11, 2020 at 6:11 AM Anup Patel
> wrote:
> >
> >
> > > -Original Message-
> > > From: Qemu-riscv > > bounces+anup.patel=wdc@nongnu.org> On Behalf Of Alistair
> > > Francis
> > > Sent: 11 June 2020 04:59
> > > To
The G3 beige machine has a machine ID register that is accessed by the
firmware to deternine the board config. Add basic emulation of it.
Signed-off-by: BALATON Zoltan
---
hw/ppc/mac_oldworld.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac
The G3 beige machine has a 4MB firmware ROM. Fix the size of the rom
region and allow loading a binary image with -bios. This makes it
possible to test emulation with a ROM image from real hardware.
Signed-off-by: BALATON Zoltan
---
hw/ppc/mac_oldworld.c | 24 +++-
1 file cha
Based on https://github.com/dingusdev/dingusppc this series allows
experimenting with binary ROM image from a G3 beige machine. It does
not get very far though. Running with
-bios 78F57389.rom -d unimp,guest_errors -trace enable="pci*" | uniq -c
I get the logs below and hangs reading the last reg
On Thu, Jun 11, 2020 at 6:11 AM Anup Patel wrote:
>
>
>
> > -Original Message-
> > From: Qemu-riscv > bounces+anup.patel=wdc@nongnu.org> On Behalf Of Alistair Francis
> > Sent: 11 June 2020 04:59
> > To: Anup Patel
> > Cc: Peter Maydell ; open list:RISC-V > ri...@nongnu.org>; Sagar
On Thu, Jun 11, 2020 at 3:30 PM Havard Skinnemoen
wrote:
> @@ -57,18 +72,30 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState
> *machine)
> static void npcm750_evb_init(MachineState *machine)
> {
> NPCM7xxState *soc;
> +DriveInfo *dinfo;
>
> soc = npcm7xx_create_soc(machine)
> +child_tid = atomic_fetch_or(&mgr->managed_tid, 0);
> +/*
> + * Check if the child has already terminated by this point. If not, wait
> + * for the child to exit. As long as the trampoline is not killed by
> + * a signal, the kernel guarantees that the memory at &mgr->managed_
Philippe Mathieu-Daudé writes:
> On 6/12/20 9:44 PM, no-re...@patchew.org wrote:
>> Patchew URL:
>> https://patchew.org/QEMU/20200612190237.30436-1-alex.ben...@linaro.org/
>> CC x86_64-softmmu/fpu/softfloat.o
>> CC x86_64-softmmu/disas.o
>> /usr/bin/ld:
>> /usr/lib64/clang/10.0.
On Fri, 12 Jun 2020 at 15:51, Michael S. Tsirkin wrote:
>
> changes from v1:
> - printf format fixed for 32 bit hosts
> - a couple of bugfixes added
>
> The following changes since commit 49ee11555262a256afec592dfed7c5902d5eefd2:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/linux-us
On 6/12/20 9:44 PM, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20200612190237.30436-1-alex.ben...@linaro.org/
> CC x86_64-softmmu/fpu/softfloat.o
> CC x86_64-softmmu/disas.o
> /usr/bin/ld:
> /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_
While there isn't any easy way to make the inline counts thread safe
we can ensure the callback based ones are. While we are at it we can
reduce introduce a new option ("idle") to dump a report of the current
bb and insn count each time a vCPU enters the idle state.
Signed-off-by: Alex Bennée
Cc:
Patchew URL:
https://patchew.org/QEMU/20200612190237.30436-1-alex.ben...@linaro.org/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
From: Robert Foley
This allows us to see the name of the thread in tsan
warning reports such as this:
Thread T7 'CPU 1/TCG' (tid=24317, running) created by main thread at:
Signed-off-by: Robert Foley
Reviewed-by: Emilio G. Cota
Signed-off-by: Alex Bennée
Message-Id: <20200609200738.445-12-
From: Robert Foley
Disable a few tests under CONFIG_TSAN, which
run into a known TSan issue that results in a hang.
https://github.com/google/sanitizers/issues/1116
The disabled tests under TSan include all the qtests as well as
the test-char, test-qga, and test-qdev-global-props.
Signed-off-by
From: "Emilio G. Cota"
Signed-off-by: Emilio G. Cota
Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
Message-Id: <20200609200738.445-9-robert.fo...@linaro.org>
---
include/qemu/thread.h | 39 ---
1 file changed, 36 insertion
From: Robert Foley
Adds TSan details to testing.rst.
This includes background and reference details on TSan,
and details on how to build and test with TSan
both with and without docker.
Signed-off-by: Robert Foley
Reviewed-by: Emilio G. Cota
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
From: "Emilio G. Cota"
I was after adding qemu_spin_destroy calls, but while at
it I noticed that we are leaking some memory.
Signed-off-by: Emilio G. Cota
Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
Message-Id: <20200609200738.445-5-robert.fo...@linaro.or
We do this on our other platforms to make it easier to see what has
broken.
Signed-off-by: Alex Bennée
---
.cirrus.yml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/.cirrus.yml b/.cirrus.yml
index ce7850a320e..69342ae031b 100644
--- a/.cirrus.yml
+++ b/.cirrus.yml
@@
From: "Emilio G. Cota"
Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
Message-Id: <20200609200738.445-6-robert.fo...@linaro.org>
---
util/qht.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/util/qht.c b/util/qht.c
index aa51be3c52f..67e5d5b9163 100644
--
This reverts commit 12d43b5ae916809aad9ccf8aa2a0a06260527340.
Signed-off-by: Alex Bennée
---
.shippable.yml | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/.shippable.yml b/.shippable.yml
index 10cf219bff4..2cce7b56890 100644
--- a/.shippable.yml
+++ b/.shippable
From: "Emilio G. Cota"
It will be used for TSAN annotations.
Signed-off-by: Emilio G. Cota
Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
Message-Id: <20200609200738.445-4-robert.fo...@linaro.org>
---
include/qemu/thread.h | 3 +++
1 file changed, 3 insertio
From: Robert Foley
These annotations will allow us to give tsan
additional hints. For example, we can inform
tsan about reads/writes to ignore to silence certain
classes of warnings.
We can also annotate threads so that the proper thread
naming shows up in tsan warning results.
Signed-off-by: R
From: "Emilio G. Cota"
Signed-off-by: Emilio G. Cota
Signed-off-by: Robert Foley
Signed-off-by: Alex Bennée
[RF: minor changes + remove tb_destroy_func]
Message-Id: <20200609200738.445-7-robert.fo...@linaro.org>
---
include/tcg/tcg.h | 1 +
accel/tcg/translate-all.c | 8
tcg/
From: Lingfeng Yang
We tried running QEMU under tsan in 2016, but tsan's lack of support for
longjmp-based fibers was a blocker:
https://groups.google.com/forum/#!topic/thread-sanitizer/se0YuzfWazw
Fortunately, thread sanitizer gained fiber support in early 2019:
https://reviews.llvm.org/D54
From: "Emilio G. Cota"
The radix tree is append-only, but we can fail to insert
a PageDesc if the insertion races with another thread.
Signed-off-by: Emilio G. Cota
Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
Message-Id: <20200609200738.445-8-robert.fo...@
From: Claudio Fontana
dtc submodule update, now call the libfdt target from the new
dtc Makefile, which has been changed to not require bison, flex, etc.
This removes warnings during the build.
scripts/ symlink and tests directory creation are not necessary,
and neither is calling the clean rule
From: Robert Foley
Added a new docker for ubuntu 20.04.
This docker has support for Thread Sanitizer
including one patch we need in one of the header files.
https://github.com/llvm/llvm-project/commit/a72dc86cd
This command will build with tsan enabled:
make docker-test-tsan-ubuntu2004 V=1
Also
We should be keeping this up to date as Fedora goes out of support
quite quickly.
Signed-off-by: Alex Bennée
---
tests/docker/dockerfiles/fedora.docker | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/docker/dockerfiles/fedora.docker
b/tests/docker/dockerfiles/fedora.do
From: "Emilio G. Cota"
We convert queued work to a QSIMPLEQ, instead of
open-coding it.
While at it, make sure that all accesses to the list are
performed while holding the list's lock.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by:
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
Message-Id: <20200518160319.18861-3-cfont...@suse.de>
---
Makefile | 6 --
1 file changed, 6 deletions(-)
Hi,
This is the current testing/next queue. Aside from the minor bumps and
updates this returns --enable-tsan to the build.
This can help with debugging race conditions. You need a fairly recent
clang to enable it but configure will bug out if it can't be turned
on. Thanks to Robert Foley for pic
Am 12.06.20 um 19:54 schrieb Philippe Mathieu-Daudé:
> A LED device can be connected to a GPIO output.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/misc/led.h | 30
> hw/misc/led.c | 84 +++
> MAINTAINERS
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/tosa.c | 7 +++
hw/arm/Kconfig | 1 +
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 5dee2d76c6..86d7e0283a 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -24,6 +24,7 @@
#include "hw/irq.
We were using an AVR based Arduino to use this device, but since
the port is not merged, the microbit is the easiest board to use
with Zephyr.
Note the microbit doesn't have a such LED, this is simply a proof
of concept.
How to test:
- Apply this patch on zephyr-v2.3.0
diff --git a/boards/arm/
Allow LED devices to emit STATUS_CHANGED events on a QMP chardev.
QMP event examples:
{
"timestamp": {
"seconds": 1591704274,
"microseconds": 520850
},
"event": "LED_STATUS_CHANGED",
"data": {
"name": "Green LED #0",
"status": "on"
}
}
{
"ti
Add create_led_by_gpio_id() to easily connect a LED to
a GPIO output.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/misc/led.h | 14 ++
hw/misc/led.c | 20
2 files changed, 34 insertions(+)
diff --git a/include/hw/misc/led.h b/include/hw/misc/led.
Hello,
These patches are part of the GSoC unselected 'QEMU visualizer'
project. As the AVR port is not merged, I switched to microbit
to keep working on it.
This series presents a proof of concept of LED device that can
be easily connected to a GPIO.
The LED emit QMP events, so an external visua
A LED device can be connected to a GPIO output.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/misc/led.h | 30
hw/misc/led.c | 84 +++
MAINTAINERS | 6
hw/misc/Kconfig | 3 ++
hw/misc/Makefile.objs |
Yeah, I can reproduce the same exact behavior outside of QEMU with sway
and it's consistent to what I observed in QEMU.
> Hmm, happens with xorg only.
I think you were right all along about this, sorry.
Thanks for fixing this bug, feel free to close this bug as fixed.
--
You received this bug
** Tags added: arm testcase
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1883268
Title:
random errors on aarch64 when executing __aarch64_cas8_acq_rel
Status in QEMU:
New
Bug description:
He
It looks like sway requires swayidle to wake up from sleep[1].
This works:
swayidle timeout 2 'swaymsg "output * dpms off"' resume 'swaymsg "output
* dpms on"'
1. https://github.com/swaywm/sway/issues/2914
** Bug watch added: github.com/swaywm/sway/issues #2914
https://github.com/swaywm/sway
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 4 ++-
target/mips/msa_helper.c | 67
target/mips/translate.c | 12 ++-
3 files changed, 68 insertions(+), 15 deletions(-)
diff
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 4 ++-
target/mips/msa_helper.c | 67
target/mips/translate.c | 12 ++-
3 files changed, 68 insertions(+), 15 deletions(-)
diff
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 4 +-
target/mips/msa_helper.c | 90
target/mips/translate.c | 12 +-
3 files changed, 78 insertions(+), 28 deletions(-)
diff -
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 5 ++-
target/mips/msa_helper.c | 66
target/mips/translate.c | 12 +++-
3 files changed, 69 insertions(+), 14 deletions(-)
dif
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 4 ++-
target/mips/msa_helper.c | 65
target/mips/translate.c | 12 +++-
3 files changed, 67 insertions(+), 14 deletions(-)
dif
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 79
target/mips/translate.c | 19 --
3 files changed, 92 insertions(+), 12 deletions(-)
d
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 4 ++-
target/mips/msa_helper.c | 67
target/mips/translate.c | 12 ++-
3 files changed, 68 insertions(+), 15 deletions(-)
diff
This series contains some patches that split heprers in msa_helper.c.
It will make easier for debugging tools to display involved source
code, and also introduces some modest performance improvements gains
for all involved MSA instructions.
v6->v7:
- excluded patches that have been already upst
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 79
target/mips/translate.c | 19 --
3 files changed, 93 insertions(+), 11 deletions(-)
d
From: Filip Bozuta
This series introduces the functionality in strace to print arguments for
ioctls. This is gonna be a useful adittion as it indroduces a good debugging
and diagnostic mechanism for user programs cross compiled for different
architectures.
The first patch in the series introduce
On 10/06/20 15:47, Michael S. Tsirkin wrote:
> Memory API documentation documents valid .min_access_size and .max_access_size
> fields and explains that any access outside these boundaries is blocked.
>
> This is what devices seem to assume.
>
> However this is not what the implementation does: i
From: Filip Bozuta
This patch implements functionality for strace argument printing for ioctls.
When running ioctls through qemu with "-strace", they get printed in format:
"ioctl(fd_num,0x*,0x*) = ret_value"
where the request code an the ioctl's third argument get printed in a
hexadicemal
From: Filip Bozuta
Socket ioctls SIOCGSTAMP and SIOCGSTAMPNS, used for timestamping the socket
connection, are defined in file "ioctls.h" differently from other ioctls.
The reason for this difference is explained in the comments above their
definition.
These ioctls didn't have defined thunk argu
On 08/06/20 18:54, Joseph Myers wrote:
> The x87 floating-point emulation of the fprem and fprem1 instructions
> works via conversion to and from double. This is inherently
> unsuitable for a good emulation of any floatx80 operation. This patch
> series adapts the softfloat floatx80_rem implement
On 12/06/20 01:45, Joseph Myers wrote:
> The x87 f2xm1 emulation is currently based around conversion to
> double. This is inherently unsuitable for a good emulation of any
> floatx80 operation, even before considering that it is a particularly
> naive implementation using double (computing with p
Hi Philippe,
On Fri, Jun 12, 2020 at 6:35 AM Philippe Mathieu-Daudé
wrote:
> Hi Havard
>
> On 6/12/20 12:30 AM, Havard Skinnemoen wrote:
> > Add a config symbol for the NPCM7xx BMC SoC family that subsequent
> > patches can use in Makefiles.
> >
> > Change-Id: I6e4d5c58716cb6fe4ea5d06f148beeafda
On Fri, Jun 12, 2020 at 08:51:46AM -0700, no-re...@patchew.org wrote:
> Patchew URL: https://patchew.org/QEMU/20200612141917.9446-1-...@redhat.com/
>
>
>
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Message-id: 20200612141917.9446
On Thu, Jun 11, 2020 at 07:13:35PM +0100, Peter Maydell wrote:
> On Wed, 10 Jun 2020 at 05:26, Michael S. Tsirkin wrote:
> >
> > The following changes since commit 49ee11555262a256afec592dfed7c5902d5eefd2:
> >/tmp/par8snSu.par
>
> > Merge remote-tracking branch
> > 'remotes/vivier2/tags/linux-
From: Joseph Myers
This corrects a bug introduced in my previous fix for SSE4.2 pcmpestri
/ pcmpestrm / pcmpistri / pcmpistrm substring search, commit
ae35eea7e4a9f21dd147406dfbcd0c4c6aaf2a60.
That commit fixed a bug that showed up in four GCC tests with one libc
implementation. The tests in qu
The following changes since commit 31d321c2b3574dcc74e9f6411af06bca6b5d10f4:
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sparc-next-20200609'
into staging (2020-06-09 17:29:47 +0100)
are available in the Git repository at:
git://github.com/bonzini/qemu.git tags/for-upstream
fo
From: Roman Bolshakov
There's no similar field in CPUX86State, but it's needed for MMIO traps.
Signed-off-by: Roman Bolshakov
Message-Id: <20200528193758.51454-13-r.bolsha...@yadro.com>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 1 +
target/i386/hvf/hvf.c | 5 +
ta
From: Roman Bolshakov
The lazy flags are still needed for instruction decoder.
Signed-off-by: Roman Bolshakov
Message-Id: <20200528193758.51454-12-r.bolsha...@yadro.com>
[Move struct to target/i386/cpu.h - Paolo]
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 6
target/i
From: Roman Bolshakov
They're either declared elsewhere or have no use.
While at it, rename _hvf_cpu_synchronize_post_init() to
do_hvf_cpu_synchronize_post_init().
Signed-off-by: Roman Bolshakov
Message-Id: <20200528193758.51454-3-r.bolsha...@yadro.com>
Signed-off-by: Paolo Bonzini
Reviewed-b
On Thu, Jun 11, 2020 at 04:27:44PM +0100, Stefan Hajnoczi wrote:
On Fri, Jun 05, 2020 at 07:35:34AM +0800, Coiby Xu wrote:
v8
- re-try connecting to socket server to fix asan error
- fix license naming issue
Great, thanks for posting these patches!
I have posted feedback. I'd like to merge
Patchew URL: https://patchew.org/QEMU/20200612141917.9446-1-...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20200612141917.9446-1-...@redhat.com
Subject: [PULL v2 00/58] virtio,acpi,pci: features, fixes, cleanups, tes
Hi Eric,
On 6/9/20 4:29 PM, Eric Blake wrote:
> On 6/9/20 7:34 AM, Philippe Mathieu-Daudé wrote:
>> Allow LED devices to emit STATUS_CHANGED events on a QMP chardev.
>>
>> QMP event examples:
>>
>> {
>> "timestamp": {
>> "seconds": 1591704274,
>> "microseconds": 520850
>>
Hi,
On 6/12/20 3:43 PM, Wu, Wentong wrote:
> Hi,
> Can any body help review this patch ? Thanks in advance!
You just sent this patch yesterday... Please give reviewers more time.
See:
https://wiki.qemu.org/Contribute/SubmitAPatch#Participating_in_Code_Review
In particular:
https://wiki.qemu.org/
Sway log after the crash.
** Attachment added: "swaylog.txt"
https://bugs.launchpad.net/qemu/+bug/1882851/+attachment/5383276/+files/swaylog.txt
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https://bugs.launchpad.net/bugs/1882
On 12/06/20 16:53, Roman Bolshakov wrote:
> It seems rebase is not needed. The queue doesn't include the patch:
> https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg08076.html
Thanks, it had a conflict with
commit f291cf54148e5b9e51c55b9056e4be546492a9ca
Author: Philippe Mathieu-Daudé
Date
On Fri, 2020-06-12 at 14:54 +0100, Lorenzo Pieralisi wrote:
> On Thu, Jun 11, 2020 at 09:16:48PM +, Derrick, Jonathan wrote:
>
> [...]
>
> > > > > Hi Jon,
> > > > >
> > > > > it looks like I can take this patch for v5.8 whereas patch 2 depends
> > > > > on the QEMU changes acceptance and sho
Gerd, thanks. I can confirm your patch fixes the problem with X, but
Wayland (sway) is still affected.
I tested X and wayland, and while the "Guest disabled display" no longer
hangs on X, it still does hangs under wayland.
Should I bisect again?
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From: Stefano Garzarella
This patch prepares the introduction of vhost-user-vsock, moving
the common code usable for both vhost-vsock and vhost-user-vsock
devices, in the new vhost-vsock-common parent class.
While moving the code, fixed checkpatch warnings about block comments.
Signed-off-by: S
From: Philippe Mathieu-Daudé
memory_region_set_size() handle the 16 Exabytes limit by
special-casing the UINT64_MAX value. This is not a problem
for the 32-bit maximum, 4 GiB.
By using the UINT32_MAX value, the bm-raven MemoryRegion
ends up missing 1 byte:
$ qemu-system-ppc -M prep -S -monitor
From: Stefano Garzarella
Add the PCI version of vhost-user-vsock
Launch QEMU like this:
qemu -chardev socket,path=/tmp/vm.vsock,id=chr0 \
-device vhost-user-vsock-pci,chardev=chr0
Signed-off-by: Stefano Garzarella
Message-Id: <20200522122512.87413-4-sgarz...@redhat.com>
Reviewed-by:
From: Philippe Mathieu-Daudé
IEC binary prefixes ease code review: the unit is explicit.
Reviewed-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20200601142930.29408-5-f4...@amsat.org>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Reviewed-by: Richar
From: Eric Auger
Include sockets and channel headers to that the header is
self-contained.
Signed-off-by: Eric Auger
Reviewed-by: Stefan Berger
Message-Id: <20200609125409.24179-2-eric.au...@redhat.com>
---
tests/qtest/tpm-emu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/qte
From: Alexander Duyck
We need to make certain to advertise support for page poison reporting if
we want to actually get data on if the guest will be poisoning pages.
Add a value for reporting the poison value being used if page poisoning is
enabled in the guest. With this we can determine if we
From: Stefano Garzarella
This patch introduces a vhost-user device for vsock, using the
vhost-vsock-common parent class.
The vhost-user-vsock device can be used to implement the virtio-vsock
device emulation in user-space.
Signed-off-by: Stefano Garzarella
Message-Id: <20200522122512.87413-3-s
From: Eric Auger
Add placeholders for TPM and DSDT reference tables for
Q35 TPM-TIS tests and ignore them for the time being.
Signed-off-by: Eric Auger
Reviewed-by: Stefan Berger
Reviewed-by: Igor Mammedov
Message-Id: <20200609125409.24179-3-eric.au...@redhat.com>
Reviewed-by: Michael S. Tsi
From: Jason Wang
Spec said: The driver uses this to selectively prevent the device from
executing requests from this virtqueue. 1 - enabled; 0 - disabled.
Though write 0 to queue_enable is forbidden by the spec, we should not
assume that the value is 1.
Fix this by ignore the write value other
From: Peter Xu
Sometimes it would be good to be able to read the pin number along
with the IRQ number allocated. Since we'll dump the IRQ number, no
reason to not dump the pin information. For example, the vfio-pci
device will overwrite the pin with the hardware pin number. It would
be nice to
From: Vishal Verma
In anticipation of a change to the SRAT generation in qemu, add the AML
file to diffs-allowed.
Signed-off-by: Vishal Verma
Message-Id: <20200606000911.9896-2-vishal.l.ve...@intel.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-ta
On Fri, Jun 12, 2020 at 03:33:38PM +0200, Paolo Bonzini wrote:
> On 12/06/20 15:09, Peter Maydell wrote:
> > Hi; I'm afraid this fails to build on OSX, and has a check-tcg
> > failure on x86-64 Linux.
> >
> > OSX:
> >
> > In file included from
> > /Users/pm215/src/qemu-for-merges/target/i386/hvf
From: Eric Auger
In preparation of its move to the generic acpi code,
let's convert build_tpm2() to use build_append API. This
latter now is prefered in place of direct ACPI struct field
settings with manual endianness conversion.
Signed-off-by: Eric Auger
Message-Id: <20200601095737.32671-2-er
From: Vishal Verma
Update expected SRAT files for the change to account for NVDIMM NUMA
nodes in the SRAT.
AML diffs:
tests/data/acpi/pc/SRAT.dimmpxm:
Message-Id: <20200606000911.9896-4-vishal.l.ve...@intel.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtes
From: Gerd Hoffmann
Needed for microvm.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Igor Mammedov
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20200520132003.9492-8-kra...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/i386/acpi-common.h | 3 ++-
hw
From: Gerd Hoffmann
Remove PCMachineState dependency from build_madt().
Pass AcpiDeviceIf as separate argument instead of
depending on PCMachineState->acpi_dev.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
Message-Id: <20200520132003.9492-6-kra..
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