Re: [PATCH 5/5] riscv: Suppress the error report for QEMU testing with riscv_find_firmware()

On Fri, May 1, 2020 at 9:25 PM Bin Meng wrote: > > From: Bin Meng > > We only ship plain binary bios images in the QEMU source. With Spike > machine that uses ELF images as the default bios, running QEMU test > will complain hence let's suppress the error report for QEMU testing. > > Signed-off-b

Re: [PATCH 3/5] riscv: Use pre-built bios image of generic platform for virt & sifive_u

On Fri, May 1, 2020 at 9:26 PM Bin Meng wrote: > > From: Bin Meng > > Update virt and sifive_u machines to use the opensbi bios image > built for the generic FDT platform. > > Remove the out-of-date no longer used bios images. > > Signed-off-by: Bin Meng > --- > > hw/riscv/sifive_u.c

Re: [PATCH 4/5] riscv/spike: Change the default bios to use generic platform image

On Fri, May 1, 2020 at 9:25 PM Bin Meng wrote: > > From: Bin Meng > > To keep sync with other RISC-V machines, change the default bios > to use generic platform image. > > While we are here, add some comments to mention that keeping ELF > files here was intentional. > > Signed-off-by: Bin Meng >

Re: [PATCH 2/5] gitlab-ci/opensbi: Update GitLab CI to build generic platform

On Fri, May 1, 2020 at 9:24 PM Bin Meng wrote: > > From: Bin Meng > > This updates the GitLab CI opensbi job to build opensbi bios images > for the generic platform. > > Signed-off-by: Bin Meng > --- > > .gitlab-ci-opensbi.yml | 26 -- > 1 file changed, 8 insertions(+),

Re: [PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform

On Fri, May 1, 2020 at 9:26 PM Bin Meng wrote: > > From: Bin Meng > > The RISC-V generic platform is a flattened device tree (FDT) based > platform where all platform specific functionality is provided based > on FDT passed by previous booting stage. The support was added in > upstream opensbi re

[Bug 1876373] Re: segfault mremap 4096

FYI, first patch in the previous comment was wrong. This new patch is the correct one: https://lists.gnu.org/archive/html/qemu- devel/2020-05/msg00183.html -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bu

Re: [PATCH] linux-user/mmap.c: fix integer underflow in target_mremap

FYI, I applied this patch to the qemu build that zig uses to run non-native tests ( https://github.com/ziglang/qemu-static/blob/master/patch/mremap-underflow.diff ) After applying it, my new code that calls mremap now passes, whereas before the fix I was getting a segfault. On Sat, May 2, 2020 at

Re: [INFO] Some preliminary performance data

[correcting some email addresses] нед, 3. мај 2020. у 01:20 Aleksandar Markovic < aleksandar.qemu.de...@gmail.com> је написао/ла: > Hi, all. > > I just want to share with you some bits and pieces of data that I got > while doing some preliminary experimentation for the GSoC project "TCG > Continu

[INFO] Some preliminary performance data

Hi, all. I just want to share with you some bits and pieces of data that I got while doing some preliminary experimentation for the GSoC project "TCG Continuous Benchmarking", that Ahmed Karaman, a student of the fourth final year of Electical Engineering Faculty in Cairo, will execute. *User Mod

[PATCH v2 11/15] target/arm: Wrap vector qrdmla/qrdmls in GVecGen3Fn

Provide a functional interface for the vector expansion. This fits better with the existing set of helpers that we provide for other operations. Signed-off-by: Richard Henderson --- target/arm/translate.h | 5 target/arm/translate-a64.c | 34 ++-- target/arm/transla

[PATCH v2 13/15] target/arm: Clear tail in gvec_fmul_idx_*, gvec_fmla_idx_*

Must clear the tail for AdvSIMD when SVE is enabled. Fixes: ca40a6e6e39 Signed-off-by: Richard Henderson --- target/arm/vec_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 6aa2ca0827..a483841add 100644 --- a/target/arm/vec_he

[PATCH v2 05/15] target/arm: Tidy handle_vec_simd_shri

Now that we've converted all cases to gvec, there is quite a bit of dead code at the end of the function. Remove it. Sink the call to gen_gvec_fn2i to the end, loading a function pointer within the switch statement. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 56 +

[PATCH v2 10/15] target/arm: Remove fp_status from helper_{recpe, rsqrte}_u32

These operations do not touch fp_status. Signed-off-by: Richard Henderson --- target/arm/helper.h| 4 ++-- target/arm/translate-a64.c | 5 ++--- target/arm/translate.c | 12 ++-- target/arm/vfp_helper.c| 4 ++-- 4 files changed, 8 insertions(+), 17 deletions(-) diff -

[PATCH v2 15/15] target/arm: Vectorize SABA/UABA

Include 64-bit element size in preparation for SVE2. Signed-off-by: Richard Henderson --- target/arm/helper.h| 17 +++-- target/arm/translate.h | 5 ++ target/arm/neon_helper.c | 10 --- target/arm/translate-a64.c | 17 ++--- target/arm/translate.c | 134 ++

[PATCH v2 14/15] target/arm: Vectorize SABD/UABD

Include 64-bit element size in preparation for SVE2. Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 +++ target/arm/translate.h | 5 ++ target/arm/translate-a64.c | 8 ++- target/arm/translate.c | 133 - target/arm/vec_helper

[PATCH v2 09/15] target/arm: Wrap vector uqadd/sqadd/uqsub/sqsub GVecGen4 in GVecGen3Fn

Provide a functional interface for the vector expansion. This fits better with the existing set of helpers that we provide for other operations. Signed-off-by: Richard Henderson --- target/arm/translate.h | 13 +- target/arm/translate-a64.c | 22 ++-- target/arm/translate.c | 248 +

[PATCH v2 03/15] target/arm: Create gen_gvec_{sri,sli}

The functions eliminate duplication of the special cases for this operation. They match up with the GVecGen2iFn typedef. Add out-of-line helpers. We got away with only having inline expanders because the neon vector size is only 16 bytes, and we know that the inline expansion will always succeed

[PATCH v2 08/15] target/arm: Wrap vector cmtst/ushl/sshl GVecGen3 in GVecGen3Fn

Provide a functional interface for the vector expansion. This fits better with the existing set of helpers that we provide for other operations. Signed-off-by: Richard Henderson --- target/arm/translate.h | 10 ++- target/arm/translate-a64.c | 18 ++--- target/arm/translate.c | 159 +++

[PATCH v2 00/15] target/arm: partial vector cleanup

This is not complete, but shows the direction I'd like to go. It may well help what Peter is doing with the neon decodetree conversion. It may be helpful to apply before the conversion in order to reduce the number of special cases. As may continuing with the cleanup; I'll probably work on that

[PATCH v2 07/15] target/arm: Wrap vector mla/mls GVecGen3 in GVecGen3Fn

Provide a functional interface for the vector expansion. This fits better with the existing set of helpers that we provide for other operations. Signed-off-by: Richard Henderson --- target/arm/translate.h | 7 ++- target/arm/translate-a64.c | 4 +- target/arm/translate.c | 124 ++

[PATCH v2 12/15] target/arm: Pass pointer to qc to qrdmla/qrdmls

Pass a pointer directly to env->vfp.qc[0], rather than env. This will allow SVE2, which does not modify QC, to pass a pointer to dummy storage. Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 --- target/arm/vec_helper.c | 70 +++-- 2

[PATCH v2 04/15] target/arm: Remove unnecessary range check for VSHL

In 1dc8425e551, while converting to gvec, I added an extra range check against the shift count. This was unnecessary because the encoding of the shift count produces 0 to the element size - 1. Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 ++-- 1 file changed, 2 inser

[PATCH v2 01/15] target/arm: Create gen_gvec_[us]sra

The functions eliminate duplication of the special cases for this operation. They match up with the GVecGen2iFn typedef. Add out-of-line helpers. We got away with only having inline expanders because the neon vector size is only 16 bytes, and we know that the inline expansion will always succeed

[PATCH v2 02/15] target/arm: Create gen_gvec_{u,s}{rshr,rsra}

Create vectorized versions of handle_shri_with_rndacc for shift+round and shift+round+accumulate. Add out-of-line helpers in preparation for longer vector lengths from SVE. Signed-off-by: Richard Henderson --- target/arm/helper.h| 20 ++ target/arm/translate.h | 9 + target/arm/t

[PATCH v2 06/15] target/arm: Wrap vector compare zero GVecGen2 in GVecGen2Fn

Provide a functional interface for the vector expansion. This fits better with the existing set of helpers that we provide for other operations. Macro-ize the 5 nearly identical comparisons. Signed-off-by: Richard Henderson --- target/arm/translate.h | 16 ++- target/arm/translate-a64.c |

Re: [PATCH v25 00/10] Add ARMv8 RAS virtualization support in QEMU

> > On Thu, 30 Apr 2020 11:56:24 +0800 > gengdongjiu wrote: > > > On 2020/4/17 21:32, Peter Maydell wrote: > > > On Fri, 10 Apr 2020 at 12:46, Dongjiu Geng wrote: > > >> > > >> In the ARMv8 platform, the CPU error types includes synchronous > > >> external abort(SEA) and SError Interrupt (SEI).

Re: [PATCH 0/2] vTPM/aarch64 ACPI support

Patchew URL: https://patchew.org/QEMU/20200502203536.15011-1-eric.au...@redhat.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN =

Re: [PATCH RFC 0/4] vl: Sync dirty bitmap when system resets

On Wed, Apr 29, 2020 at 10:32:27AM -0400, Peter Xu wrote: > On Wed, Apr 29, 2020 at 02:26:07PM +0100, Dr. David Alan Gilbert wrote: > > * Peter Xu (pet...@redhat.com) wrote: > > > This RFC series starts from the fact that we will sync dirty bitmap when > > > removing a memslot for KVM. IIUC that w

[PATCH 2/2] arm/acpi: Add the TPM2.0 device under the DSDT

In case it is dynamically instantiated, add the TPM 2.0 device object under the DSDT table in the ACPI namespace. Its HID is MSFT0101 while its current resource settings (CRS) property is initialized with the guest physical address and MMIO size of the device. Signed-off-by: Eric Auger --- hw/ar

[PATCH 1/2] arm/acpi: TPM2 ACPI table support

Add a TPM2 ACPI table if a TPM2.0 sysbus device has been dynamically instantiated. Signed-off-by: Eric Auger --- include/sysemu/tpm.h | 2 ++ hw/arm/virt-acpi-build.c | 36 2 files changed, 38 insertions(+) diff --git a/include/sysemu/tpm.h b/include/sy

[PATCH 0/2] vTPM/aarch64 ACPI support

Those 2 patches bring MMIO TPM TIS ACPI support in machvirt. The TPM2.0 table is added and the TPM2 device object is described in the DSDT. Many thanks to Ard for his support. Tested with LUKS partition automatic decryption. Best Regards Eric This series can be found at: https://github.com/

[PATCH] linux-user, alpha: fix oldumount syscall

When we try to bootstrap debian/lenny for alpha, it fails because it cannot umount /.root directory: ... Setting up initscripts (2.86.ds1-61) ... umount: /.root: Function not implemented dpkg: error processing initscripts (--configure): subprocess post-installation script returned error

[Qemu-devel] [PULL 0/1] RDMA queue

The following changes since commit 1c47613588ccff44422d4bdeea0dc36a0a308ec7: Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2020-04-30 19:25:41 +0100) are available in the Git repository at: https://github.com/marcel-apf/qemu tags/rdma-pull-request for you to

[Qemu-devel] [PULL 1/1] hw/rdma: Destroy list mutex when list is destroyed

From: Yuval Shaia List mutex should be destroyed when gs list gets destroyed. Reported-by: Peter Maydell Signed-off-by: Yuval Shaia Message-Id: <20200413085738.11145-1-yuval.shaia...@gmail.com> Reviewed-by: Marcel Apfelbaum Signed-off-by: Marcel Apfelbaum --- hw/rdma/rdma_utils.c | 1 + 1 fi

Re: [PATCH 00/10] Cadence GEM Fixes

Patchew URL: https://patchew.org/QEMU/1588441994-21447-1-git-send-email-sai.pavan.bo...@xilinx.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TES

Re: [PATCH 3/4] softfloat: fix floatx80 pseudo-denormal comparisons

Joseph Myers writes: > On Fri, 1 May 2020, Alex Bennée wrote: > >> OK - so these only turn up in i386? > > Patch 1, silencing sNaN, is about generic semantics of IEEE floating-point > conversions (which are implemented correctly in various other cases in > QEMU), and would be equally applicab

[PATCH 10/10] net: cadence_gem: Fix RX address filtering

From: Tong Ho Two defects are fixed: 1/ Detection of multicast frames 2/ Treating drop of mis-addressed frames as non-error Signed-off-by: Tong Ho Signed-off-by: Edgar E. Iglesias Signed-off-by: Sai Pavan Boddu --- hw/net/cadence_gem.c | 26 +++--- 1 file changed, 11 ins

[PATCH 00/10] Cadence GEM Fixes

Hi, Following patch series fixes issues with priority queues, Adds JUMBO Frame support, Makes Debug statements compilable & Fixes related to multicast frames. Sai Pavan Boddu (9): net: cadence_gem: Fix debug statements net: cadence_gem: Fix the queue address update during wrap around net: c

[PATCH 05/10] net: cadence_gem: Set ISR according to queue in use

Set ISR according to queue in use, added interrupt support for all queues. Signed-off-by: Sai Pavan Boddu --- hw/net/cadence_gem.c | 31 ++- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index e745d60..cc9e7

[PATCH 06/10] net: cadence_gem: Add support for jumbo frames

Jumbo frames of size 10240 bytes is added. Signed-off-by: Sai Pavan Boddu --- hw/net/cadence_gem.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index cc9e735..75fdb00 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_ge

[PATCH 08/10] net: cadence_gem: Update the reset value for interrupt mask register

Mask all interrupt on reset. Signed-off-by: Sai Pavan Boddu --- hw/net/cadence_gem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index e6a3d6c..68df92d 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1347,6 +1347,7 @@ static vo

[PATCH 07/10] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg

Advertise support of clear-on-read for ISR registers. Signed-off-by: Sai Pavan Boddu --- hw/net/cadence_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 75fdb00..e6a3d6c 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cade

[PATCH 03/10] net: cadence_gem: Fix irq update w.r.t queue

Set irq's specific to a queue, present implementation is setting q1 irq based on q0 status. Signed-off-by: Sai Pavan Boddu --- hw/net/cadence_gem.c | 25 +++-- 1 file changed, 3 insertions(+), 22 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 074

[PATCH 04/10] net: cadence_gem: Define access permission for interrupt registers

Q1 to Q7 ISR's are clear-on-read, IER/IDR registers are write-only, mask reg are read-only. Signed-off-by: Sai Pavan Boddu --- hw/net/cadence_gem.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 7782d6d..e745d60 100644 --- a/

[PATCH 09/10] net: cadence_gem: TX_LAST bit should be set by guest

TX_LAST bit should not be set by hardware, its set by guest to inform the last bd of the frame. Signed-off-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias --- hw/net/cadence_gem.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 68d

[PATCH 01/10] net: cadence_gem: Fix debug statements

Enabling debug breaks the build, Fix them and make debug statements always compilable. Signed-off-by: Sai Pavan Boddu --- hw/net/cadence_gem.c | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 22a0b1b

[PATCH 02/10] net: cadence_gem: Fix the queue address update during wrap around

During wrap around and reset, queues are pointing to initial base address of queue 0, irrespective of what queue we are dealing with. Fix it by assigning proper base address every time. Signed-off-by: Sai Pavan Boddu --- hw/net/cadence_gem.c | 29 + 1 file changed, 25

[PATCH] linux-user/mmap.c: fix integer underflow in target_mremap

Fixes: https://bugs.launchpad.net/bugs/1876373 This code path in mmap occurs when a page size is decreased with mremap. When a section of pages is shrunk, qemu calls mmap_reserve on the pages that were released. However, it has the diff operation reversed, subtracting the larger old_size from

Re: [PATCH] linux-user/mmap.c: fix integer underflow in target_mremap

Yes the first patch was incorrect. The second patch should be the correct one. Thanks for the guidance. I have created a new patch with a "Fixes: ..." and a description of the fix, and have sent that patch to qemu-devel@nongnu.org On Sat, May 2, 2020 at 2:38 AM Laurent Vivier wrote: > Hi, > >

Re: [PATCH] target/m68k: Allow movec only on 68010+

Le 02/05/2020 à 03:38, BALATON Zoltan a écrit : > On Fri, 1 May 2020, Laurent Vivier wrote: >> Le 01/05/2020 à 15:11, BALATON Zoltan a écrit : >>> Ping? >> >> I sent a comment: >> >> https://lists.gnu.org/archive/html/qemu-devel/2020-01/msg02840.html > > Thanks, I've somehow missed that, did not s

Re: [PATCH 08/17] s390x/cpumodel: Fix UI to CPU features pcc-cmac-{aes,eaes}-256

On 02.05.20 08:26, Markus Armbruster wrote: > David Hildenbrand writes: > >> On 30.04.20 20:22, Markus Armbruster wrote: >>> David Hildenbrand writes: >>> On 28.04.20 18:34, Markus Armbruster wrote: > Both s390_features[S390_FEAT_PCC_CMAC_AES_256].name and > s390_features[S390_FEAT_

Re: [PATCH] linux-user/mmap.c: fix integer underflow in target_mremap

Hi, does this patch replace your previous one? Please add more details in the description, as you did in the launchpad bug. You can also add: Fixes: https://bugs.launchpad.net/bugs/1876373 You must also send the patch to qemu-devel@nongnu.org Thanks, Laurent Le 02/05/2020 à 09:49, Jonathan Ma