Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 182
1 file changed, 111 insertions(+), 71 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index a33699adf8..e8b8f2560d 100644
--- a/target/arm/sve_helper.c
+++ b/t
10.03.2020 18:47, Markus Armbruster wrote:
Vladimir Sementsov-Ogievskiy writes:
09.03.2020 12:56, Markus Armbruster wrote:
Suggest
scripts: Coccinelle script to use auto-propagated errp
or
scripts: Coccinelle script to use ERRP_AUTO_PROPAGATE()
Vladimir Sementsov-Ogievskiy wr
With sve_cont_ldst_pages, the differences between first-fault and no-fault
are minimal, so unify the routines. With cpu_probe_watchpoint, we are able
to make progress through pages with TLB_WATCHPOINT set when the watchpoint
does not actually fire.
Signed-off-by: Richard Henderson
---
target/ar
>-Original Message-
>From: Laurent Vivier [mailto:laur...@vivier.eu]
>Sent: Tuesday, March 10, 2020 11:01 PM
>To: Chenqun (kuhn) ; qemu-
>de...@nongnu.org; qemu-triv...@nongnu.org
>Cc: Fam Zheng ; Hannes Reinecke ;
>Zhanghailiang ; qemu-bl...@nongnu.org;
>Euler Robot ; Paolo Bonzini
>
>Subj
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 223 ++--
1 file changed, 79 insertions(+), 144 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 2c0e838ed3..56407446eb 100644
--- a/target/arm/sve_helper.c
+++ b/t
None of the sve helpers use TCGMemOpIdx any longer, so we can
stop passing it.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 5 -
target/arm/sve_helper.c| 14 +++---
target/arm/translate-sve.c | 17 +++--
3 files changed, 10 insertions(+), 26 dele
The current interface includes a loop; change it to load a
single element. We will then be able to use the function
for ld{2,3,4} where individual vector elements are not adjacent.
Replace each call with the simplest possible loop over active
elements.
Signed-off-by: Richard Henderson
---
targ
This avoids the need for a separate set of helpers to implement
no-fault semantics, and will enable MTE in the future.
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 323
1 file changed, 127 insertions(+), 196 deletions(-)
diff --git a/ta
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 208 +---
1 file changed, 109 insertions(+), 99 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index e8b8f2560d..4ad870f1ee 100644
--- a/target/arm/sve_helper.c
+++ b/t
Handle all of the watchpoints for active elements all at once,
before we've modified the vector register. This removes the
TLB_WATCHPOINT bit from page[].flags, which means that we can
use the normal fast path via RAM.
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 70 ++
First use of the new helper functions, so we can remove the
unused markup. No longer need a scratch for user-only, as
we completely probe the page set before reading; system mode
still requires a scratch for MMIO.
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 188 ++
For contiguous predicated memory operations, we want to
minimize the number of tlb lookups performed. We have
open-coded this for sve_ld1_r, but for correctness with
MTE we will need this for all of the memory operations.
Create a structure that holds the bounds of active elements,
and metadata f
Allow probing of a watchpoint *without* raising an exception.
This is of most use for no-fault loads, which should indicate
via some architectural means that the load did not occur.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 7 +++
exec.c| 19 ++
Use the "normal" memory access functions, rather than the
softmmu internal helper functions directly.
Since fb901c905dc3, cpu_mem_index is now a simple extract
from env->hflags and not a large computation. Which means
that it's now more work to pass around this value than it
is to recompute it.
Since we converted back to cpu_*_data_ra, we do not need to
do this ourselves.
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 38 --
1 file changed, 38 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index f8b310a16
Follow the model set up for contiguous loads. This handles
watchpoints correctly for contiguous stores, recognizing the
exception before any changes to memory.
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 288 ++--
1 file changed, 162 insert
The goal here is to support MTE, but there's some cleanup to do.
Technically, we have sufficient interfaces in cputlb.c now, but it
requires multiple tlb lookups on different interfaces to do so.
Adding probe_access_flags() allows probing the tlb and getting out
some of the flags buried in the tl
This new interface will allow targets to probe for a page
and then handle watchpoints themselves. This will be most
useful for vector predicated memory operations, where one
page lookup can be used for many operations, and one test
can avoid many watchpoint checks.
Signed-off-by: Richard Henderso
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 350c4b451b..d656a1f05c 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -330,6 +330,23 @
Hi Eric,
On 2020/3/10 22:54, Eric Auger wrote:
Allocate the LPI configuration and per re-distributor pending table.
Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled
by default in the config table.
Also introduce a helper routine that allows to set the pending table
bit for a gi
On 3/9/20 2:58 PM, Peter Maydell wrote:
> Currently we put 'docs/foo/*.rst' in the Make list of dependencies
> for the Sphinx 'foo' manual, which means all the files must be
> in the top level of that manual's directory. We'd like to be
> able to have subdirectories inside some of the manuals, so a
On 3/9/20 8:44 AM, Peter Maydell wrote:
> We don't need texinfo to build the docs any more, so we can
> drop that dependency from our docker and other CI configs.
>
> Signed-off-by: Peter Maydell
> ---
> .travis.yml| 1 -
> tests/docker/dockerfiles/debian10.docker
On 3/9/20 8:44 AM, Peter Maydell wrote:
> We don't need the texinfo and pod2man programs to build our documentation
> any more, so remove them from configure's tests.
>
> Signed-off-by: Peter Maydell
> ---
> configure | 12 ++--
> 1 file changed, 2 insertions(+), 10 deletions(-)
Reviewe
On 3/9/20 8:44 AM, Peter Maydell wrote:
> We no longer need the texi2pod script, so we can delete it, and
> the special-casing it had in the checkpatch script.
>
> Signed-off-by: Peter Maydell
> ---
> scripts/checkpatch.pl | 2 +-
> scripts/texi2pod.pl | 536 -
On 3/9/20 8:44 AM, Peter Maydell wrote:
> We don't use Texinfo any more; we can remove the references to the
> .texi source files and the generated output files from our
> .gitignore and git.orderfile.
>
> Signed-off-by: Peter Maydell
> ---
> .gitignore| 15 ---
> scripts
On Wed, Mar 11, 2020 at 12:19:59AM +0200, Liran Alon wrote:
>
> On 11/03/2020 0:00, Michael S. Tsirkin wrote:
> > On Tue, Mar 10, 2020 at 11:57:49PM +0200, Liran Alon wrote:
> > > On 10/03/2020 23:44, Michael S. Tsirkin wrote:
> > > > On Tue, Mar 10, 2020 at 02:29:42PM -0700, Liran Alon wrote:
> >
On 3/9/20 8:44 AM, Peter Maydell wrote:
> We now don't build anything from Texinfo, so we can remove
> some redundant Makefile pattern rules and the rule for
> generating the version.texi file that used to be included
> from many Texinfo source files.
>
> Signed-off-by: Peter Maydell
> ---
> Mak
On 3/9/20 8:44 AM, Peter Maydell wrote:
> Update the documentation of QAPI document comment syntax to match
> the new rST backend requirements. The principal changes are:
> * whitespace is now significant, and multiline definitions
>must have their second and subsequent lines indented to
>
On 3/9/20 8:43 AM, Peter Maydell wrote:
> We no longer use the generated texinfo format documentation,
> so delete the code that generates it, and the test case for
> the generation.
>
> Signed-off-by: Peter Maydell
> ---
> Makefile| 1 -
> tests/Makefile.include
On 3/9/20 8:43 AM, Peter Maydell wrote:
> Add some section headings to the QGA json; this is purely so that we
> have some H1 headings, as otherwise each command ends up being
> visible in the interop/ manual's table of contents. In an ideal
> world there might be a proper 'Introduction' section t
On 3/9/20 8:43 AM, Peter Maydell wrote:
> There are exactly two places in our json doc comments where we
> use the markup accepted by the texi doc generator where a '|' in
> the first line of a doc comment means the line should be emitted
> as a literal block (fixed-width font, whitespace preserved
10.03.2020 20:17, Max Reitz wrote:
On 06.03.20 08:45, Vladimir Sementsov-Ogievskiy wrote:
26.02.2020 16:13, Max Reitz wrote:
On 05.02.20 12:20, Vladimir Sementsov-Ogievskiy wrote:
Hi!
The main feature here is improvement of _next_dirty_area API, which I'm
going to use then for backup / block-
On 3/9/20 8:43 AM, Peter Maydell wrote:
> Convert qemu-qmp-ref to rST format. This includes dropping
> the plain-text, pdf and info format outputs for this document;
> as with all our other Sphinx-based documentation, we provide
> HTML and manpage only.
>
> The qemu-qmp-ref.rst is somewhat more st
On 3/9/20 8:43 AM, Peter Maydell wrote:
> Convert qemu-ga-ref to rST format. This includes dropping
> the plain-text, pdf and info format outputs for this document;
> as with all our other Sphinx-based documentation, we provide
> HTML and manpage only.
>
> The qemu-ga-ref.rst is somewhat more stri
On 3/9/20 8:43 AM, Peter Maydell wrote:
> Make the handling of indentation in doc comments more sophisticated,
> so that when we see a section like:
>
> Notes: some text
>some more text
> indented line 3
>
> we save it for the doc-comment processing code as:
>
> some text
> som
On 3/9/20 8:43 AM, Peter Maydell wrote:
> As we accumulate lines from doc comments when parsing the JSON, the
> QAPIDoc class generally strips leading and trailing whitespace using
> line.strip() when it calls _append_freeform(). This is fine for
> texinfo, but for rST leading whitespace is signif
On 3/9/20 8:43 AM, Peter Maydell wrote:
> doc-good.json tests some oddities of markup that we don't want to
> accept. Make them match the more restrictive rST syntax:
>
> * in a single list the bullet types must all match
> * lists must have leading and following blank lines
> * indentation is
On 3/9/20 8:43 AM, Peter Maydell wrote:
> For rST, '*' is a kind of inline markup (for emphasis), so
> "*-softmmu" is a syntax error because of the missing closing '*'.
> Escape the '*' with a '\'.
>
> The texinfo document generator will leave the '\' in the
> output, which is not ideal, but that
On 3/9/20 8:43 AM, Peter Maydell wrote:
> Our current QAPI doc-comment markup allows section headers
> (introduced with a leading '=' or '==') anywhere in any documentation
> comment. This works for texinfo because the texi generator simply
> prints a texinfo heading directive at that point in the
On 3/9/20 8:43 AM, Peter Maydell wrote:
> Commits 6a9ad1542065ca0bd54c6 and 9004db48c080632aef23 added some
> new text to qapi/migration.json which doesn't fit the stricter
> indentation requirements imposed by the rST documentation generator.
> Reindent those lines to the new standard.
>
> Signed
Patchew URL:
https://patchew.org/QEMU/20200311052145.14004-1-richard.hender...@linaro.org/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin
On 3/6/20 9:17 AM, Peter Maydell wrote:
> Peter Maydell (7):
> Makefile: Remove redundant Texinfo related code
> Update comments in .hx files that mention Texinfo
> hxtool: Remove Texinfo generation support
> docs/sphinx/hxtool.py: Remove STEXI/ETEXI support
> Makefile: Make all Sphinx do
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 84 +
4 files changed, 119 insertions(+)
diff --
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 131
target/riscv/vector_helper.c| 77 ++
4 files changed, 233 insertions(
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16 +
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 7
target/riscv/vector_helper.c| 48 +
4 files changed, 76 insertions(+)
dif
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 128
4 files changed, 155 insertions(+)
diff --g
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 16 ++
target/riscv/vector_helper.c| 278
4 files changed, 337 insertions(+)
diff --gi
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 +++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c| 103
4 files changed, 118 insertions(+)
diff --git
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++
target/riscv/vector_helper.c| 129
4 files changed, 158 insertions(+)
diff --g
A given RISU testcase for SVE can produce
tcg-op-vec.c:511: do_shifti: Assertion `i >= 0 && i < (8 << vece)' failed.
because expand_vec_sari gave a shift count of 32 to a MO_32
vector shift.
In 44f1441dbe1, we changed from direct expansion of vector opcodes
to re-use of the tcg expanders. So wh
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 107
target/riscv/vector_helper.c| 89
4 files changed, 217 inse
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 22
target/riscv/insn32.decode | 7
target/riscv/insn_trans/trans_rvv.inc.c | 9 +
target/riscv/vector_helper.c| 45 +
4 files changed, 83 insertions(+)
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 22 +++
target/riscv/insn32.decode | 7 +
target/riscv/insn_trans/trans_rvv.inc.c | 9 ++
target/riscv/vector_helper.c| 180
4 files changed, 218 insertions(+)
diff --gi
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 88 +
4 files changed, 139 insertions(+)
di
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 74 +
4 files changed, 125 insertions(+)
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 109
4 files changed, 140 insertions(+)
diff --
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 37 +++
target/riscv/vector_helper.c| 40 +
4 files changed, 84 insert
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 71 +
4 files changed, 122 insertions(+)
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 108 ++
target/riscv/vector_helper.c| 140
4 files changed, 291 inse
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 24 ++
target/riscv/vector_helper.c| 58 +
4 files changed, 94 insertions(+)
dif
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 49 +
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvv.inc.c | 18 ++
target/riscv/vector_helper.c| 228
4 files changed, 311 insertions(+)
diff -
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 91 +
target/riscv/vector_helper.c| 14
4 files changed, 124 insertions(+)
diff --g
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
target/riscv/vector_helper.c| 147
4 files changed, 198 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 19 +
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvv.inc.c | 8
target/riscv/vector_helper.c| 51 +
4 files changed, 84 insertions(+)
dif
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvv.inc.c | 44 +
target/riscv/vector_helper.c| 82 +
4 files changed, 160 insertion
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 57 +++
target/riscv/insn32.decode | 20
target/riscv/insn_trans/trans_rvv.inc.c | 66
target/riscv/vector_helper.c| 130
4 files changed, 273 ins
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 22 ++
4 files changed, 33 insertions(+)
diff --git
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++
target/riscv/vector_helper.c| 51 +
4 files changed, 96 insertions(
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 49
target/riscv/insn32.decode | 16 +++
target/riscv/insn_trans/trans_rvv.inc.c | 154
target/riscv/vector_helper.c| 112 +
4 files changed, 331 in
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu.
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 35 +++
target/riscv/insn32.decode
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in memory
starting from
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 21 +++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 220
target/riscv/vector_helper.c| 122 +
4 files changed, 373 insertions(+
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
target/riscv/Makefile.objs |
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
This patchset implements the vector extension for RISC-V on QEMU.
You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v3).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode pro
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
On Thu, Feb 20, 2020 at 09:44:13AM +0100, Philippe Mathieu-Daudé wrote:
> Hello,
>
> On 2/20/20 6:40 AM, Wayne Li wrote:
> > Dear QEMU list members,
>
> No subject: it is unlikely your question get noticed...
>
> Also you didn't Cc'ed the people who might help you (doing that for you):
>
> ./sc
On Tue, Mar 10, 2020 at 08:48:49PM +0800, 罗勇刚(Yonggang Luo) wrote:
> I have already debugging it. I have infinite interrupt after calling to
> motTsecGracefulStop,
What interrupt is it, and what instruction is triggering it?
> I am simulating wrSbc834x using etsec with PPC.
Unfortunately the fr
On Mon, Mar 09, 2020 at 10:32:34PM -0400, Cleber Rosa wrote:
>
>
> - Original Message -
> > From: "David Gibson"
> > To: "Alex Bennée"
> > Cc: qemu-devel@nongnu.org, "Wainer dos Santos Moschetta"
> > , "Kamil Rytarowski"
> > , "Hervé Poussineau" , "Cleber
> > Rosa" ,
> > qemu-...@nong
Patchew URL: https://patchew.org/QEMU/20200311040923.29115-1-gs...@redhat.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
export
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1656927
Title:
Network (TC
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
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https://bugs.launchpad.net/bugs/1657841
Title:
QEMU Intel
The depth of TxFIFO can be 1 or 16 depending on LCR[4]. The TxFIFO is
disabled when its depth is 1. It's nice to have TxFIFO enabled if
possible because more characters can be piled and transmitted at once,
which would have less overhead. Besides, we can be blocked because of
qemu_chr_fe_write_all(
On 3/10/20 7:19 PM, LIU Zhiwei wrote:
> Is it serious?
It isn't ideal. I would eventually try to review via your branch, and find a
copy of the patch to reply, or send a reply to the cover letter if no copy of
the patch arrived.
> Is there any way to clear it in the mail list archives?
No.
> C
On Tue, Mar 10, 2020 at 04:07:31PM +1100, Alexey Kardashevskiy wrote:
> At the moment "pseries" starts in SLOF which only expects the FDT blob
> pointer in r3. As we are going to introduce a OpenFirmware support in
> QEMU, we will be booting OF clients directly and these expect a stack
> pointer in
On Tue, Mar 10, 2020 at 11:06:08AM +0100, Cédric Le Goater wrote:
> On 3/3/20 4:43 AM, David Gibson wrote:
> > When we store the Logical Partitioning Control Register (LPCR) we have a
> > big switch statement to work out which are valid bits for the cpu model
> > we're emulating.
> >
> > As well a
Clang static code analyzer show warning:
block/iscsi.c:1920:9: warning: Value stored to 'flags' is never read
flags &= ~BDRV_O_RDWR;
^
In iscsi_allocmap_init() only checks BDRV_O_NOCACHE, which
is the same in both of flags and bs->open_flags.
We can use the fl
** Also affects: ubuntu
Importance: Undecided
Status: New
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https://bugs.launchpad.net/bugs/1866870
Title:
KVM Guest pauses after upgrade to Ubuntu 20.04
Status in QEMU:
Ne
On 2020/3/11 1:15, Alex Williamson wrote:
> vfio_rom_read() relies on memcpy() doing the logically correct thing,
> ie. safely copying zero bytes from a NULL pointer when rom_size is
> zero, rather than the spec definition, which is undefined when the
> source or target pointers are NULL. Resol
Apicid calculation depends on knowing the total number of numa nodes
for EPYC cpu models. Right now, we are calculating the arch_id while
parsing the numa(parse_numa). At this time, it is not known how many
total numa nodes are configured in the system.
Move the arch_id inside x86_cpus_init. At th
Update structures X86CPUTopoIDs and CPUX86State to hold the number of
nodes per package. This is required to build EPYC mode topology.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
Acked-by: Michael S. Tsirkin
---
hw/i386/pc.c |1 +
hw/i386/x86.c |1 +
Check X86CPUDefinition if use_epyc_apic_id_encoding is enabled. If enabled
update X86MachineState with EPYC mode apic_id encoding handlers.
Also update the calling convention to use apic_id handlers from X86MachineState.
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
---
hw/i386/pc.c
The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
This works fine for most standard AMD and other vendors' configurations,
but this decoding sequence does not follow that of AMD's APIC ID enumeration
strictly. In some cases this can cause CPU topology inconsistency.
When
The function pc_cpu_pre_plug takes care of initialization of CPUX86State.
So, remove the initialization here.
Suggested-by: Igor Mammedov
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
Acked-by: Michael S. Tsirkin
---
hw/i386/x86.c |4
1 file changed, 4 deletions(-)
diff --git
If the system is numa configured the pkg_offset needs
to be adjusted for EPYC cpu models. Fix it calling the
model specific handler.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
Acked-by: Michael S. Tsirkin
---
hw/i386/pc.c |1 +
target/i386/cpu.c |4 ++--
target/i386/cpu.
For consistancy rename apicid_from_topo_ids to x86_apicid_from_topo_ids.
No functional change.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
Acked-by: Michael S. Tsirkin
---
hw/i386/pc.c |2 +-
include/hw/i386/topology.h |6 +++---
2 files changed, 4 insertions(+),
Introduce model specific apicid functions inside X86MachineState.
These functions will be loaded from X86CPUDefinition.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
Acked-by: Michael S. Tsirkin
---
hw/i386/x86.c |6 ++
include/hw/i386/x86.h | 11 +++
2 files c
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